Lines Matching refs:CLK_TOP_AXI_SEL
450 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
725 GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8),
727 GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
728 GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
729 GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
730 GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
731 GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
743 GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28),
744 GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
748 GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
750 GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
751 GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
754 GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18),
755 GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
756 GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25),
761 GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3),
763 GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
764 GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27),
770 GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22),
778 GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3),
779 GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7),
788 .muxes_offs = CLK_TOP_AXI_SEL,