Searched refs:CLK_ROOT_ON (Results 1 - 17 of 17) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c390 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
400 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
402 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
404 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
419 clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
422 clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
425 clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
438 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
449 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
455 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
[all...]
H A Dclock_imx8mm.c165 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
168 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
171 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
177 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
179 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
317 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
323 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
329 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
335 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
350 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
[all...]
H A Dclock_slice.c1743 return (val & CLK_ROOT_ON) ? 1 : 0;
/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c89 target = CLK_ROOT_ON |
540 target = CLK_ROOT_ON |
565 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
570 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
575 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
600 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
605 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
610 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
615 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
620 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CL
[all...]
H A Dclock_slice.c715 val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
/u-boot/board/polyhex/imx8mp_debix_model_a/
H A Dspl.c45 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/board/freescale/imx8mp_evk/
H A Dspl.c49 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/board/beacon/imx8mp/
H A Dspl.c56 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/board/toradex/verdin-imx8mp/
H A Dspl.c69 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/board/data_modul/imx8mp_edm_sbc/
H A Dspl.c92 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/board/engicam/imx8mp/
H A Dspl.c109 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h210 #define CLK_ROOT_ON BIT(28) macro
/u-boot/board/phytec/phycore_imx8mp/
H A Dspl.c163 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/board/msc/sm2s_imx8mp/
H A Dspl.c57 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/board/dhelectronics/dh_imx8mp/
H A Dspl.c176 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
/u-boot/drivers/ddr/imx/imx8m/
H A Dddr_init.c333 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) |
/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h2080 #define CLK_ROOT_ON 0x10000000 macro

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