1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2018-2019, 2021 NXP 4 * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> 5 */ 6 7#include <asm/arch/clock.h> 8#include <asm/arch/ddr.h> 9#include <asm/arch/imx8mp_pins.h> 10#include <asm/arch/sys_proto.h> 11#include <asm/global_data.h> 12#include <asm/mach-imx/boot_mode.h> 13#include <asm/sections.h> 14#include <common.h> 15#include <dm/device.h> 16#include <dm/uclass.h> 17#include <hang.h> 18#include <init.h> 19#include <log.h> 20#include <power/pca9450.h> 21#include <power/pmic.h> 22#include <spl.h> 23 24DECLARE_GLOBAL_DATA_PTR; 25 26int spl_board_boot_device(enum boot_device boot_dev_spl) 27{ 28 return BOOT_DEVICE_BOOTROM; 29} 30 31void spl_dram_init(void) 32{ 33 ddr_init(&dram_timing); 34} 35 36void spl_board_init(void) 37{ 38 /* 39 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does 40 * not allow to change it. Should set the clock after PMIC 41 * setting done. Default is 400Mhz (system_pll1_800m with div = 2) 42 * set by ROM for ND VDD_SOC 43 */ 44 clock_enable(CCGR_GIC, 0); 45 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); 46 clock_enable(CCGR_GIC, 1); 47 48 puts("Normal Boot\n"); 49} 50 51static int power_init_board(void) 52{ 53 struct udevice *dev; 54 int ret; 55 56 ret = pmic_get("pmic@25", &dev); 57 if (ret == -ENODEV) { 58 puts("Failed to get PMIC\n"); 59 return 0; 60 } 61 if (ret != 0) 62 return ret; 63 64 /* BUCKxOUT_DVS0/1 control BUCK123 output. */ 65 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); 66 67 /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */ 68 if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) 69 /* Set DVS0 to 0.85V for special case. */ 70 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); 71 else 72 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); 73 74 /* Set DVS1 to 0.85v for suspend. */ 75 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); 76 77 /* 78 * Enable DVS control through PMIC_STBY_REQ and 79 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H). 80 */ 81 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); 82 83 /* 84 * Kernel uses OD/OD frequency for SoC. 85 * To avoid timing risk from SoC to ARM, 86 * increase VDD_ARM to OD voltage 0.95V 87 */ 88 pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); 89 90 return 0; 91} 92 93int board_fit_config_name_match(const char *name) 94{ 95 if (is_imx8mp() && 96 !strcmp(name, "imx8mp-debix-model-a")) 97 return 0; 98 99 return -1; 100} 101 102void board_init_f(ulong dummy) 103{ 104 int ret; 105 106 arch_cpu_init(); 107 108 init_uart_clk(1); 109 110 /* Clear the BSS. */ 111 memset(__bss_start, 0, __bss_end - __bss_start); 112 113 ret = spl_init(); 114 if (ret) { 115 debug("spl_init() failed: %d\n", ret); 116 hang(); 117 } 118 119 preloader_console_init(); 120 121 enable_tzc380(); 122 123 power_init_board(); 124 125 /* DDR initialization */ 126 spl_dram_init(); 127 128 board_init_r(NULL, 0); 129} 130