Searched refs:CLK_DDR (Results 1 - 17 of 17) sorted by relevance
| /u-boot/arch/arm/mach-rockchip/rk3288/ |
| H A D | rk3288.c | 158 { "dpll", CLK_DDR },
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 39 CLK_DDR, enumerator in enum:rk_clk_id
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| /u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_axp_vars.h | 167 u8 div_ratio1to1[CLK_VCO][CLK_DDR] =
196 u8 div_ratio2to1[CLK_VCO][CLK_DDR] =
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| H A D | ddr3_axp.h | 446 #define CLK_DDR 12 macro
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| H A D | ddr3_dfs.c | 41 extern u8 div_ratio[CLK_VCO][CLK_DDR];
45 extern u8 div_ratio1to1[CLK_VCO][CLK_DDR];
46 extern u8 div_ratio2to1[CLK_VCO][CLK_DDR];
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| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1108.c | 55 case CLK_DDR:
182 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
655 dpll = rkclk_pll_get_rate(cru, CLK_DDR);
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| H A D | clk_rk322x.c | 347 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
391 case CLK_DDR:
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| H A D | clk_rk3066.c | 148 rk3066_clk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
554 case CLK_DDR:
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| H A D | clk_rk3188.c | 156 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
510 case CLK_DDR:
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| H A D | clk_rk3288.c | 214 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
807 case CLK_DDR:
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| H A D | clk_rk3368.c | 500 case CLK_DDR:
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| H A D | clk_rk3328.c | 227 case CLK_DDR:
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| /u-boot/drivers/ram/rockchip/ |
| H A D | dmc-rk3368.c | 949 priv->ddr_clk.id = CLK_DDR;
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| H A D | sdram_rk3188.c | 910 priv->ddr_clk.id = CLK_DDR;
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| H A D | sdram_rk3066.c | 843 priv->ddr_clk.id = CLK_DDR;
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| H A D | sdram_rk322x.c | 803 priv->ddr_clk.id = CLK_DDR;
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| H A D | sdram_rk3288.c | 1078 priv->ddr_clk.id = CLK_DDR;
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Completed in 192 milliseconds