1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6#ifndef __DDR3_AXP_H 7#define __DDR3_AXP_H 8 9#include <config.h> 10 11#define MV_78XX0_Z1_REV 0x0 12#define MV_78XX0_A0_REV 0x1 13#define MV_78XX0_B0_REV 0x2 14 15#define SAR_DDR3_FREQ_MASK 0xFE00000 16#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) 17 18#define MAX_CS 4 19 20#define MIN_DIMM_ADDR 0x50 21#define FAR_END_DIMM_ADDR 0x50 22#define MAX_DIMM_ADDR 0x60 23 24#ifndef CFG_SYS_SDRAM_SIZE 25#define SDRAM_CS_SIZE 0xFFFFFFF 26#else 27#define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1) 28#endif 29#define SDRAM_CS_BASE 0x0 30#define SDRAM_DIMM_SIZE 0x80000000 31 32#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) 33#define CPU_MRVL_ID_OFFSET 0x10 34#define SAR1_CPU_CORE_MASK 0x00000018 35#define SAR1_CPU_CORE_OFFSET 3 36 37/* Only enable ECC if the board selects it */ 38#ifdef CONFIG_BOARD_ECC_SUPPORT 39#define ECC_SUPPORT 40#endif 41#define NEW_FABRIC_TWSI_ADDR 0x4E 42#ifdef CONFIG_TARGET_DB_MV784MP_GP 43#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E 44#else 45#define BUS_WIDTH_ECC_TWSI_ADDR 0x4F 46#endif 47#define MV_MAX_DDR3_STATIC_SIZE 50 48#define MV_DDR3_MODES_NUMBER 30 49 50#define RESUME_RL_PATTERNS_ADDR (0xFE0000) 51#define RESUME_RL_PATTERNS_SIZE (0x100) 52#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + RESUME_RL_PATTERNS_SIZE) 53#define RESUME_TRAINING_VALUES_MAX (0xCD0) 54#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000) 55#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000) 56#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4) 57#define SUSPEND_MAGIC_WORD (0xDEADB002) 58#define REGISTER_LIST_END (0xFFFFFFFF) 59 60/* 61 * Registers offset 62 */ 63 64#define REG_SAMPLE_RESET_LOW_ADDR 0x18230 65#define REG_SAMPLE_RESET_HIGH_ADDR 0x18234 66#define REG_SAMPLE_RESET_CPU_FREQ_OFFS 21 67#define REG_SAMPLE_RESET_CPU_FREQ_MASK 0x00E00000 68#define REG_SAMPLE_RESET_FAB_OFFS 24 69#define REG_SAMPLE_RESET_FAB_MASK 0xF000000 70#define REG_SAMPLE_RESET_TCLK_OFFS 28 71#define REG_SAMPLE_RESET_CPU_ARCH_OFFS 31 72#define REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS 20 73 74/* MISC */ 75/* 76 * In mainline U-Boot we're re-configuring the mvebu base address 77 * register to 0xf1000000. So need to use this value for the DDR 78 * training code as well. 79 */ 80#define INTER_REGS_BASE SOC_REGS_PHY_BASE 81 82/* DDR */ 83#define REG_SDRAM_CONFIG_ADDR 0x1400 84#define REG_SDRAM_CONFIG_MASK 0x9FFFFFFF 85#define REG_SDRAM_CONFIG_RFRS_MASK 0x3FFF 86#define REG_SDRAM_CONFIG_WIDTH_OFFS 15 87#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17 88#define REG_SDRAM_CONFIG_ECC_OFFS 18 89#define REG_SDRAM_CONFIG_IERR_OFFS 19 90#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28 91#define REG_SDRAM_CONFIG_RSTRD_OFFS 30 92 93#define REG_DUNIT_CTRL_LOW_ADDR 0x1404 94#define REG_DUNIT_CTRL_LOW_2T_OFFS 3 95#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3 96#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14 97 98#define REG_SDRAM_TIMING_LOW_ADDR 0x1408 99 100#define REG_SDRAM_TIMING_HIGH_ADDR 0x140C 101#define REG_SDRAM_TIMING_H_R2R_OFFS 7 102#define REG_SDRAM_TIMING_H_R2R_MASK 0x3 103#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9 104#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3 105#define REG_SDRAM_TIMING_H_W2W_OFFS 11 106#define REG_SDRAM_TIMING_H_W2W_MASK 0x1F 107#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19 108#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7 109#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22 110#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7 111 112#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410 113#define REG_SDRAM_ADDRESS_SIZE_OFFS 2 114#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18 115#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4 116 117#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414 118#define REG_SDRAM_OPERATION_CS_OFFS 8 119 120#define REG_SDRAM_OPERATION_ADDR 0x1418 121#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24 122#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20 123#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xF 124#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16 125#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xF 126#define REG_SDRAM_OPERATION_CMD_MR0 0xF03 127#define REG_SDRAM_OPERATION_CMD_MR1 0xF04 128#define REG_SDRAM_OPERATION_CMD_MR2 0xF08 129#define REG_SDRAM_OPERATION_CMD_MR3 0xF09 130#define REG_SDRAM_OPERATION_CMD_RFRS 0xF02 131#define REG_SDRAM_OPERATION_CMD_CWA 0xF0E 132#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xF 133#define REG_SDRAM_OPERATION_CMD_MASK 0xF 134#define REG_SDRAM_OPERATION_CS_OFFS 8 135 136#define REG_OUDDR3_TIMING_ADDR 0x142C 137 138#define REG_SDRAM_MODE_ADDR 0x141C 139 140#define REG_SDRAM_EXT_MODE_ADDR 0x1420 141 142#define REG_DDR_CONT_HIGH_ADDR 0x1424 143 144#define REG_ODT_TIME_LOW_ADDR 0x1428 145#define REG_ODT_ON_CTL_RD_OFFS 12 146#define REG_ODT_OFF_CTL_RD_OFFS 16 147#define REG_SDRAM_ERROR_ADDR 0x1454 148#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474 149#define REG_ODT_TIME_HIGH_ADDR 0x147C 150 151#define REG_SDRAM_INIT_CTRL_ADDR 0x1480 152#define REG_SDRAM_INIT_CTRL_OFFS 0 153#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2 154#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3 155 156#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494 157 158#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498 159/*#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0xFFFFFF55 */ 160#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0 161#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3 162 163#define REG_DUNIT_ODT_CTRL_ADDR 0x149C 164#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8 165#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9 166 167#define REG_DRAM_FIFO_CTRL_ADDR 0x14A0 168 169#define REG_DRAM_AXI_CTRL_ADDR 0x14A8 170#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0 171 172#define REG_METAL_MASK_ADDR 0x14B0 173#define REG_METAL_MASK_MASK 0xDFFFFFFF 174#define REG_METAL_MASK_RETRY_OFFS 0 175 176#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14C0 177 178#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14C4 179#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8 180#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14CC 181 182#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8 183 184#define REG_CS_SIZE_SCRATCH_ADDR 0x1504 185#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520 186#define REG_DDR_IO_ADDR 0x1524 187#define REG_DDR_IO_CLK_RATIO_OFFS 15 188 189#define REG_DFS_ADDR 0x1528 190#define REG_DFS_DLLNEXTSTATE_OFFS 0 191#define REG_DFS_BLOCK_OFFS 1 192#define REG_DFS_SR_OFFS 2 193#define REG_DFS_ATSR_OFFS 3 194#define REG_DFS_RECONF_OFFS 4 195#define REG_DFS_CL_NEXT_STATE_OFFS 8 196#define REG_DFS_CL_NEXT_STATE_MASK 0xF 197#define REG_DFS_CWL_NEXT_STATE_OFFS 12 198#define REG_DFS_CWL_NEXT_STATE_MASK 0x7 199 200#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538 201#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1F 202#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8 203 204#define REG_READ_DATA_READY_DELAYS_ADDR 0x153C 205#define REG_READ_DATA_READY_DELAYS_MASK 0x1F 206#define REG_READ_DATA_READY_DELAYS_OFFS 8 207 208#define START_BURST_IN_ADDR 1 209 210#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488 211#define REG_DRAM_TRAINING_ADDR 0x15B0 212#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0 213#define REG_DRAM_TRAINING_PATTERNS_OFFS 4 214#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2 215#define REG_DRAM_TRAINING_WL_OFFS 3 216#define REG_DRAM_TRAINING_RL_OFFS 6 217#define REG_DRAM_TRAINING_DQS_RX_OFFS 15 218#define REG_DRAM_TRAINING_DQS_TX_OFFS 16 219#define REG_DRAM_TRAINING_CS_OFFS 20 220#define REG_DRAM_TRAINING_RETEST_OFFS 24 221#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27 222#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29 223#define REG_DRAM_TRAINING_ERROR_OFFS 30 224#define REG_DRAM_TRAINING_AUTO_OFFS 31 225#define REG_DRAM_TRAINING_RETEST_PAR 0x3 226#define REG_DRAM_TRAINING_RETEST_MASK 0xF8FFFFFF 227#define REG_DRAM_TRAINING_CS_MASK 0xFF0FFFFF 228#define REG_DRAM_TRAINING_PATTERNS_MASK 0xFF0F0000 229 230#define REG_DRAM_TRAINING_1_ADDR 0x15B4 231#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16 232 233#define REG_DRAM_TRAINING_2_ADDR 0x15B8 234#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17 235#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4 236#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3 237#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2 238#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1 239#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0 240 241#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15BC 242#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3 243 244#define REG_TRAINING_DEBUG_2_ADDR 0x15C4 245#define REG_TRAINING_DEBUG_2_OFFS 16 246#define REG_TRAINING_DEBUG_2_MASK 0x3 247 248#define REG_TRAINING_DEBUG_3_ADDR 0x15C8 249#define REG_TRAINING_DEBUG_3_OFFS 3 250#define REG_TRAINING_DEBUG_3_MASK 0x7 251 252#define MR_CS_ADDR_OFFS 4 253 254#define REG_DDR3_MR0_ADDR 0x15D0 255#define REG_DDR3_MR0_CS_ADDR 0x1870 256#define REG_DDR3_MR0_CL_MASK 0x74 257#define REG_DDR3_MR0_CL_OFFS 2 258#define REG_DDR3_MR0_CL_HIGH_OFFS 3 259#define CL_MASK 0xF 260 261#define REG_DDR3_MR1_ADDR 0x15D4 262#define REG_DDR3_MR1_CS_ADDR 0x1874 263#define REG_DDR3_MR1_RTT_MASK 0xFFFFFDBB 264#define REG_DDR3_MR1_DLL_ENA_OFFS 0 265#define REG_DDR3_MR1_RTT_DISABLED 0x0 266#define REG_DDR3_MR1_RTT_RZQ2 0x40 267#define REG_DDR3_MR1_RTT_RZQ4 0x2 268#define REG_DDR3_MR1_RTT_RZQ6 0x42 269#define REG_DDR3_MR1_RTT_RZQ8 0x202 270#define REG_DDR3_MR1_RTT_RZQ12 0x4 271#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */ 272#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12 /* Output Buffer Disabled */ 273#define REG_DDR3_MR1_WL_ENA_OFFS 7 274#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */ 275#define REG_DDR3_MR1_ODT_MASK 0xFFFFFDBB 276 277#define REG_DDR3_MR2_ADDR 0x15D8 278#define REG_DDR3_MR2_CS_ADDR 0x1878 279#define REG_DDR3_MR2_CWL_OFFS 3 280#define REG_DDR3_MR2_CWL_MASK 0x7 281#define REG_DDR3_MR2_ODT_MASK 0xFFFFF9FF 282#define REG_DDR3_MR3_ADDR 0x15DC 283#define REG_DDR3_MR3_CS_ADDR 0x187C 284 285#define REG_DDR3_RANK_CTRL_ADDR 0x15E0 286#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xF 287#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4 288 289#define REG_ZQC_CONF_ADDR 0x15E4 290 291#define REG_DRAM_PHY_CONFIG_ADDR 0x15EC 292#define REG_DRAM_PHY_CONFIG_MASK 0x3FFFFFFF 293 294#define REG_ODPG_CNTRL_ADDR 0x1600 295#define REG_ODPG_CNTRL_OFFS 21 296 297#define REG_PHY_LOCK_MASK_ADDR 0x1670 298#define REG_PHY_LOCK_MASK_MASK 0xFFFFF000 299 300#define REG_PHY_LOCK_STATUS_ADDR 0x1674 301#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9 302#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xFFF 303#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7FF 304 305#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0 306#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xC0000000 307#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000 308#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000 309#define REG_PHY_BC_OFFS 27 310#define REG_PHY_CNTRL_OFFS 26 311#define REG_PHY_CS_OFFS 16 312#define REG_PHY_DQS_REF_DLY_OFFS 10 313#define REG_PHY_PHASE_OFFS 8 314#define REG_PHY_PUP_OFFS 22 315 316#define REG_TRAINING_WL_ADDR 0x16AC 317#define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC 318#define REG_TRAINING_WL_UPD_OFFS 2 319#define REG_TRAINING_WL_CS_DONE_OFFS 3 320#define REG_TRAINING_WL_RATIO_MASK 0xFFFFFF0F 321#define REG_TRAINING_WL_1TO1 0x50 322#define REG_TRAINING_WL_2TO1 0x10 323#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000 324#define REG_TRAINING_WL_RESULTS_MASK 0x000001FF 325#define REG_TRAINING_WL_RESULTS_OFFS 20 326 327#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16D0 328#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15 329#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3F 330/* DLB*/ 331#define REG_STATIC_DRAM_DLB_CONTROL 0x1700 332#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704 333#define DLB_AGING_REGISTER 0x1708 334#define DLB_EVICTION_CONTROL_REG 0x170c 335#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710 336 337#define DLB_ENABLE 0x1 338#define DLB_WRITE_COALESING (0x1 << 2) 339#define DLB_AXI_PREFETCH_EN (0x1 << 3) 340#define DLB_MBUS_PREFETCH_EN (0x1 << 4) 341#define PREFETCH_NLNSZTR (0x1 << 6) 342 343/* CPU */ 344#define REG_BOOTROM_ROUTINE_ADDR 0x182D0 345#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12 346 347#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488 348#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16 349#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200FF 350#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488 351 352#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700 353 354#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704 355#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708 356 357#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870C 358#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xFFFFC0FF 359#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8 360 361#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710 362 363#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718 364#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8 365 366#define REG_CPU_PLL_CTRL_0_ADDR 0x1871C 367#define REG_CPU_PLL_STATUS_0_ADDR 0x18724 368#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740 369#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744 370#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780 371 372#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784 373 374#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858 375#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8 376 377/* DRAM Windows */ 378#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 379#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 380#define REG_XBAR_WIN_4_BASE_ADDR 0x20044 381#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 382#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184 383#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 384 385/* SRAM */ 386#define REG_CDI_CONFIG_ADDR 0x20220 387#define REG_SRAM_WINDOW_0_ADDR 0x20240 388#define REG_SRAM_WINDOW_0_ENA_OFFS 0 389#define REG_SRAM_WINDOW_1_ADDR 0x20244 390#define REG_SRAM_L2_ENA_ADDR 0x8500 391#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87BC 392 393/* PMU */ 394#define REG_PMU_I_F_CTRL_ADDR 0x1C090 395#define REG_PMU_DUNIT_BLK_OFFS 16 396#define REG_PMU_DUNIT_RFRS_OFFS 20 397#define REG_PMU_DUNIT_ACK_OFFS 24 398 399/* MBUS*/ 400#define MBUS_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x420) 401#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x424) 402#define MBUS_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x428) 403#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x42c) 404 405#define REG_PM_STAT_MASK_ADDR 0x2210C 406#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16 407 408#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120 409#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17 410 411#define REG_PM_CTRL_CONFIG_ADDR 0x22104 412#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18 413 414#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218C4 415#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18 416 417/* Controller revision info */ 418#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 419#define PCCRIR_REVID_OFFS 0 /* Revision ID */ 420#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) 421 422/* Power Management Clock Gating Control Register */ 423#define MV_PEX_IF_REGS_OFFSET(if) \ 424 (if < 8 ? (0x40000 + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) \ 425 : (0x42000 + ((if) % 8) * 0x40000)) 426#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) 427#define POWER_MNG_CTRL_REG 0x18220 428#define PEX_DEVICE_AND_VENDOR_ID 0x000 429#define PEX_CFG_DIRECT_ACCESS(if, reg) (MV_PEX_IF_REGS_BASE(if) + (reg)) 430#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port))) 431#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) 432#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) 433#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) 434 435/* TWSI */ 436#define TWSI_DATA_ADDR_MASK 0x7 437#define TWSI_DATA_ADDR_OFFS 1 438 439/* General */ 440#define MAX_CS 4 441 442/* Frequencies */ 443#define FAB_OPT 21 444#define CLK_CPU 12 445#define CLK_VCO (2 * CLK_CPU) 446#define CLK_DDR 12 447 448/* Cpu Frequencies: */ 449#define CLK_CPU_1000 0 450#define CLK_CPU_1066 1 451#define CLK_CPU_1200 2 452#define CLK_CPU_1333 3 453#define CLK_CPU_1500 4 454#define CLK_CPU_1666 5 455#define CLK_CPU_1800 6 456#define CLK_CPU_2000 7 457#define CLK_CPU_600 8 458#define CLK_CPU_667 9 459#define CLK_CPU_800 0xa 460 461/* Extra Cpu Frequencies: */ 462#define CLK_CPU_1600 11 463#define CLK_CPU_2133 12 464#define CLK_CPU_2200 13 465#define CLK_CPU_2400 14 466 467/* DDR3 Frequencies: */ 468#define DDR_100 0 469#define DDR_300 1 470#define DDR_333 1 471#define DDR_360 2 472#define DDR_400 3 473#define DDR_444 4 474#define DDR_500 5 475#define DDR_533 6 476#define DDR_600 7 477#define DDR_640 8 478#define DDR_666 8 479#define DDR_720 9 480#define DDR_750 9 481#define DDR_800 10 482#define DDR_833 11 483#define DDR_HCLK 20 484#define DDR_S 12 485#define DDR_S_1TO1 13 486#define MARGIN_FREQ DDR_400 487#define DFS_MARGIN DDR_100 488 489#define ODT_OPT 16 490#define ODT20 0x200 491#define ODT30 0x204 492#define ODT40 0x44 493#define ODT120 0x40 494#define ODT120D 0x400 495 496#define MRS_DELAY 100 497 498#define SDRAM_WL_SW_OFFS 0x100 499#define SDRAM_RL_OFFS 0x0 500#define SDRAM_PBS_I_OFFS 0x140 501#define SDRAM_PBS_II_OFFS 0x180 502#define SDRAM_PBS_NEXT_OFFS (SDRAM_PBS_II_OFFS - SDRAM_PBS_I_OFFS) 503#define SDRAM_PBS_TX_OFFS 0x180 504#define SDRAM_PBS_TX_DM_OFFS 576 505#define SDRAM_DQS_RX_OFFS 1024 506#define SDRAM_DQS_TX_OFFS 2048 507#define SDRAM_DQS_RX_SPECIAL_OFFS 5120 508 509#define LEN_STD_PATTERN 16 510#define LEN_KILLER_PATTERN 128 511#define LEN_SPECIAL_PATTERN 128 512#define LEN_PBS_PATTERN 16 513 514#endif /* __DDR3_AXP_H */ 515