Searched refs:CFG_SYS_FSL_SEC_ADDR (Results 1 - 19 of 19) sorted by relevance

/u-boot/arch/arm/include/asm/arch-imx8/
H A Dimx-regs.h50 #define CFG_SYS_FSL_SEC_ADDR (0x31400000) macro
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dfsl_icid.h122 CFG_SYS_FSL_SEC_ADDR, \
123 CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
189 CFG_SYS_FSL_SEC_ADDR, \
195 CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
200 CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
H A Dimmap_lsch3.h117 #define CFG_SYS_FSL_SEC_ADDR \ macro
H A Dimmap_lsch2.h179 #define CFG_SYS_FSL_SEC_ADDR \ macro
/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h25 #define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) macro
/u-boot/drivers/crypto/fsl/
H A Djobdesc.c31 ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
61 ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
119 ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
H A Dsec.c131 ccsr_sec_t __iomem *sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
H A Djr.c45 (ulong)((CFG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfdt.c96 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
/u-boot/include/
H A Dfsl_sec.h274 #define JR_BASE_ADDR(x) (CFG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
289 #define CAAM_SMPO_0 (CFG_SYS_FSL_SEC_ADDR + 0x1FBC)
/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dimx-regs.h112 #define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ macro
115 #define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dliodn.c79 ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
H A Dcpu_init.c666 ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
H A Dfdt.c612 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h232 #define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ macro
235 #define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfdt.c642 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h219 #define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ macro
222 #define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h242 #define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ macro
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2643 #define CFG_SYS_FSL_SEC_ADDR \ macro

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