#
d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
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935b60f8 |
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30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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ecc8d425 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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3408d96e |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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cdc5ed8f |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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91092132 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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0c3eec2a |
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22-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: ls104x: Enable eDMA snooping This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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8b549c0b |
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31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
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f1c6dfa4 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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09304473 |
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08-Jun-2022 |
Tom Rini <trini@konsulko.com> |
usb: ehci-fsl: Remove non-DM code The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com> |
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6074a536 |
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21-May-2022 |
Tom Rini <trini@konsulko.com> |
ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini <trini@konsulko.com> |
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be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
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6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
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a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
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0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
da4d620c |
|
05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
|
05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9729dc95 |
|
07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fb522dc |
|
12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
2949ae52 |
|
07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
935b60f8 |
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30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
ecc8d425 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
3408d96e |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
cdc5ed8f |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
91092132 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0c3eec2a |
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22-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: ls104x: Enable eDMA snooping This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
8b549c0b |
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31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f1c6dfa4 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
09304473 |
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08-Jun-2022 |
Tom Rini <trini@konsulko.com> |
usb: ehci-fsl: Remove non-DM code The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6074a536 |
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21-May-2022 |
Tom Rini <trini@konsulko.com> |
ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
2a8a3539 |
|
04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
2ab1553f |
|
04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
65cc0e2a |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
ecc8d425 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
3408d96e |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
cdc5ed8f |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
91092132 |
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16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0c3eec2a |
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22-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: ls104x: Enable eDMA snooping This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
8b549c0b |
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31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f1c6dfa4 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
09304473 |
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08-Jun-2022 |
Tom Rini <trini@konsulko.com> |
usb: ehci-fsl: Remove non-DM code The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6074a536 |
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21-May-2022 |
Tom Rini <trini@konsulko.com> |
ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
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a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
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0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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6cc04547 |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0c3eec2a |
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22-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: ls104x: Enable eDMA snooping This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
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8b549c0b |
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31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f1c6dfa4 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
09304473 |
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08-Jun-2022 |
Tom Rini <trini@konsulko.com> |
usb: ehci-fsl: Remove non-DM code The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6074a536 |
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21-May-2022 |
Tom Rini <trini@konsulko.com> |
ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
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0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0c3eec2a |
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22-Sep-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: ls104x: Enable eDMA snooping This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> |
#
8b549c0b |
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31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f1c6dfa4 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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09304473 |
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08-Jun-2022 |
Tom Rini <trini@konsulko.com> |
usb: ehci-fsl: Remove non-DM code The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com> |
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6074a536 |
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21-May-2022 |
Tom Rini <trini@konsulko.com> |
ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini <trini@konsulko.com> |
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be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
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6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
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a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
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0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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8b549c0b |
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31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f1c6dfa4 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
09304473 |
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08-Jun-2022 |
Tom Rini <trini@konsulko.com> |
usb: ehci-fsl: Remove non-DM code The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com> |
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6074a536 |
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21-May-2022 |
Tom Rini <trini@konsulko.com> |
ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini <trini@konsulko.com> |
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be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
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a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
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6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
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a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
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0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
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b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f1c6dfa4 |
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25-Jun-2022 |
Tom Rini <trini@konsulko.com> |
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
09304473 |
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08-Jun-2022 |
Tom Rini <trini@konsulko.com> |
usb: ehci-fsl: Remove non-DM code The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6074a536 |
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21-May-2022 |
Tom Rini <trini@konsulko.com> |
ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
be7dbb60 |
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12-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_IMMR to Kconfig This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
a954f6fe |
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12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4c417384 |
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05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fae6a1f |
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27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
5651f438 |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
92d2e89c |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa0706ef |
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09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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c4dc68b0 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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c44f8125 |
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08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
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2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com> |
#
63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
#
a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
#
fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com> |
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0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com> |
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9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> |
#
b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
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20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
24cb6f22 |
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16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3d23b6c5 |
|
20-Sep-2019 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
a954f6fe |
|
12-Dec-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4c417384 |
|
05-Nov-2018 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
6fae6a1f |
|
27-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing qe base address define Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
|
#
5651f438 |
|
09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: ls1046a: setup SEC ICIDs and fix up device tree Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
92d2e89c |
|
09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms QMAN_BAR{E} register setup was disabled on ARM platforms, however the register does need to be set. Enable the code also on ARMs and fix the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly enabled code works. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
fa0706ef |
|
09-Aug-2018 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
armv8: fsl-layerscape: add missing register blocks base address defines Add defines for the edma and qdma register block base addresses. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
c4dc68b0 |
|
08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
c44f8125 |
|
08-Mar-2018 |
Calvin Johnson <calvin.johnson@nxp.com> |
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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6b1373f2 |
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08-Mar-2018 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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15d59b53 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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9d1cd910 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-008997 Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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2a8a3539 |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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2ab1553f |
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04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv8: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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63b2316c |
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10-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
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a8ecb39e |
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27-Jul-2017 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> [YS: Revise subject, remove commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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fa18ed76 |
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17-Jan-2017 |
Wenbin Song <wenbin.song@nxp.com> |
armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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904110c7 |
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10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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dd2ad2f1 |
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30-Nov-2016 |
Yuan Yao <yao.yuan@nxp.com> |
armv8: QSPI: Add AHB bus 16MB+ size support The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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86d8000f |
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01-Dec-2016 |
York Sun <york.sun@nxp.com> |
script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com>
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0ea3671d |
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28-Sep-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539 Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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4de6ce15 |
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08-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
armv8: fsl-lsch2: enable snoopable sata read and write By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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9533acf3 |
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26-Sep-2016 |
York Sun <york.sun@nxp.com> |
armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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da4d620c |
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05-Jul-2016 |
Qianyu Gong <qianyu.gong@nxp.com> |
armv8: fsl_lsch2: Add SerDes 2 support New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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79119a4d |
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05-Jul-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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9729dc95 |
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07-Jun-2016 |
Rajesh Bhagat <rajesh.bhagat@nxp.com> |
include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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6fb522dc |
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12-Jun-2016 |
Sriram Dash <sriram.dash@nxp.com> |
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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b7f2bbff |
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03-Jun-2016 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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e99d7193 |
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29-Apr-2016 |
Alex Porosanu <alexandru.porosanu@freescale.com> |
arch/arm: add SEC JR0 offset Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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c238ad0a |
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14-Dec-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
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0d6faf2b |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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2949ae52 |
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07-Dec-2015 |
Mingkai Hu <Mingkai.hu@freescale.com> |
armv8/fsl_lsch2: fix DCSR_DCFG address Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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9711f528 |
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08-Dec-2015 |
Aneesh Bansal <aneesh.bansal@freescale.com> |
armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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70231009 |
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11-Nov-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
armv8/ls1043ardb: add USB support Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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af523a0d |
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11-Nov-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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8281c58f |
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26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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