1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef _FSL_ICID_H_
7#define _FSL_ICID_H_
8
9#include <asm/types.h>
10#include <fsl_qbman.h>
11#include <fsl_sec.h>
12#include <asm/armv8/sec_firmware.h>
13
14struct icid_id_table {
15#ifndef CONFIG_SPL_BUILD
16	const char *compat;
17	phys_addr_t compat_addr;
18#endif
19	phys_addr_t reg_addr;
20	u32 reg;
21#ifndef CONFIG_SPL_BUILD
22	u32 id;
23#endif
24	bool le;
25};
26
27struct fman_icid_id_table {
28	u32 port_id;
29	u32 icid;
30};
31
32u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
33int fdt_get_smmu_phandle(void *blob);
34int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
35void set_icids(void);
36void fdt_fixup_icid(void *blob);
37
38#ifdef CONFIG_SPL_BUILD
39#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
40	{ .reg = regA, \
41	  .reg_addr = addr, \
42	  .le = _le \
43	}
44#else
45#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
46	{ .compat = name, \
47	  .id = idA, \
48	  .reg = regA, \
49	  .compat_addr = compataddr, \
50	  .reg_addr = addr, \
51	  .le = _le \
52	}
53#endif
54
55#ifdef CONFIG_SYS_FSL_SEC_LE
56#define SEC_IS_LE true
57#elif defined(CONFIG_SYS_FSL_SEC_BE)
58#define SEC_IS_LE false
59#endif
60
61#ifdef CONFIG_FSL_LSCH2
62
63#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
64#define SCFG_IS_LE true
65#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
66#define SCFG_IS_LE false
67#endif
68
69#define QDMA_IS_LE false
70
71#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
72	SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
73		offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
74		compataddr, SCFG_IS_LE)
75
76#define SET_USB_ICID(usb_num, compat, streamid) \
77	SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
78		CFG_SYS_XHCI_USB##usb_num##_ADDR)
79
80#define SET_SATA_ICID(compat, streamid) \
81	SET_SCFG_ICID(compat, streamid, sata_icid,\
82		AHCI_BASE_ADDR)
83
84#define SET_SDHC_ICID(streamid) \
85	SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
86		CFG_SYS_FSL_ESDHC_ADDR)
87
88#define SET_EDMA_ICID(streamid) \
89	SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
90		EDMA_BASE_ADDR)
91
92#define SET_ETR_ICID(streamid) \
93	SET_SCFG_ICID(NULL, streamid, etr_icid, 0)
94
95#define SET_DEBUG_ICID(streamid) \
96	SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
97
98#define SET_QE_ICID(streamid) \
99	SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
100		QE_BASE_ADDR)
101
102#define SET_QMAN_ICID(streamid) \
103	SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
104		offsetof(struct ccsr_qman, liodnr) + \
105		CFG_SYS_FSL_QMAN_ADDR, \
106		CFG_SYS_FSL_QMAN_ADDR, false)
107
108#define SET_BMAN_ICID(streamid) \
109	SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
110		offsetof(struct ccsr_bman, liodnr) + \
111		CFG_SYS_FSL_BMAN_ADDR, \
112		CFG_SYS_FSL_BMAN_ADDR, false)
113
114#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
115	{ .port_id = (_port_id), .icid = (streamid) }
116
117#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
118
119#define SET_SEC_QI_ICID(streamid) \
120	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
121		0, offsetof(ccsr_sec_t, qilcr_ls) + \
122		CFG_SYS_FSL_SEC_ADDR, \
123		CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
124
125extern struct fman_icid_id_table fman_icid_tbl[];
126extern int fman_icid_tbl_sz;
127
128#else /* CONFIG_FSL_LSCH2 */
129
130#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
131#define GUR_IS_LE true
132#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
133#define GUR_IS_LE false
134#endif
135
136#define QDMA_IS_LE true
137
138#define SET_GUR_ICID(compat, streamid, name, compataddr) \
139	SET_ICID_ENTRY(compat, streamid, streamid, \
140		offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
141		compataddr, GUR_IS_LE)
142
143#define SET_USB_ICID(usb_num, compat, streamid) \
144	SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
145		CFG_SYS_XHCI_USB##usb_num##_ADDR)
146
147#define SET_SATA_ICID(sata_num, compat, streamid) \
148	SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
149		AHCI_BASE_ADDR##sata_num)
150
151#define SET_SDHC_ICID(sdhc_num, streamid) \
152	SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
153		FSL_ESDHC##sdhc_num##_BASE_ADDR)
154
155#define SET_EDMA_ICID(streamid) \
156	SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
157		EDMA_BASE_ADDR)
158
159#define SET_GPU_ICID(compat, streamid) \
160	SET_GUR_ICID(compat, streamid, misc1_amqr,\
161		GPU_BASE_ADDR)
162
163#define SET_DISPLAY_ICID(streamid) \
164	SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
165		DISPLAY_BASE_ADDR)
166
167#define SEC_ICID_REG_VAL(streamid) (streamid)
168
169#endif /* CONFIG_FSL_LSCH2 */
170
171#define SET_QDMA_ICID(compat, streamid) \
172	SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
173		QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
174		QDMA_BASE_ADDR, QDMA_IS_LE), \
175	SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
176		QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
177		QDMA_BASE_ADDR, QDMA_IS_LE)
178
179#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
180	SET_ICID_ENTRY( \
181		(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
182		(FSL_SEC_JR##jr_num##_OFFSET ==  \
183			SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
184			? NULL \
185			: "fsl,sec-v4.0-job-ring"), \
186		streamid, \
187		SEC_ICID_REG_VAL(streamid), \
188		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
189		CFG_SYS_FSL_SEC_ADDR, \
190		FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
191
192#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
193	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
194		offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
195		CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
196
197#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
198	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
199		offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
200		CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
201
202extern struct icid_id_table icid_tbl[];
203extern int icid_tbl_sz;
204
205#endif
206