1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2007-2011 Freescale Semiconductor, Inc. 4 * 5 * (C) Copyright 2003 Motorola Inc. 6 * Modified by Xianghua Xiao, X.Xiao@motorola.com 7 * 8 * (C) Copyright 2000 9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10 */ 11 12#include <display_options.h> 13#include <env.h> 14#include <init.h> 15#include <net.h> 16#include <watchdog.h> 17#include <asm/processor.h> 18#include <ioports.h> 19#include <sata.h> 20#include <fm_eth.h> 21#include <asm/io.h> 22#include <asm/cache.h> 23#include <asm/mmu.h> 24#include <fsl_errata.h> 25#include <asm/fsl_law.h> 26#include <asm/fsl_serdes.h> 27#include <asm/fsl_srio.h> 28#ifdef CONFIG_FSL_CORENET 29#include <asm/fsl_portals.h> 30#include <asm/fsl_liodn.h> 31#include <fsl_qbman.h> 32#endif 33#include <fsl_usb.h> 34#include <hwconfig.h> 35#include <linux/compiler.h> 36#include <linux/delay.h> 37#include "mp.h" 38#ifdef CONFIG_CHAIN_OF_TRUST 39#include <fsl_validate.h> 40#endif 41#ifdef CONFIG_FSL_CAAM 42#include <fsl_sec.h> 43#endif 44#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) 45#include <asm/fsl_pamu.h> 46#include <fsl_secboot_err.h> 47#endif 48#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 49#include <nand.h> 50#include <errno.h> 51#endif 52#ifndef CONFIG_ARCH_QEMU_E500 53#include <fsl_ddr.h> 54#endif 55#include "../../../../drivers/ata/fsl_sata.h" 56#ifdef CONFIG_U_QE 57#include <fsl_qe.h> 58#endif 59#include <dm.h> 60 61#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 62/* 63 * For deriving usb clock from 100MHz sysclk, reference divisor is set 64 * to a value of 5, which gives an intermediate value 20(100/5). The 65 * multiplication factor integer is set to 24, which when multiplied to 66 * above intermediate value provides clock for usb ip. 67 */ 68void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 69{ 70 sys_info_t sysinfo; 71 72 get_sys_info(&sysinfo); 73 if (sysinfo.diff_sysclk == 1) { 74 clrbits_be32(&usb_phy->pllprg[1], 75 CFG_SYS_FSL_USB_PLLPRG2_MFI); 76 setbits_be32(&usb_phy->pllprg[1], 77 CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 78 CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 79 CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 80 } 81} 82#endif 83 84#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 85void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 86{ 87#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 88 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 89 90 /* Increase Disconnect Threshold by 50mV */ 91 xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 92 INC_DCNT_THRESHOLD_50MV; 93 /* Enable programming of USB High speed Disconnect threshold */ 94 xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 95 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 96 97 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 98 /* Increase Disconnect Threshold by 50mV */ 99 xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 100 INC_DCNT_THRESHOLD_50MV; 101 /* Enable programming of USB High speed Disconnect threshold */ 102 xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 103 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 104#else 105 106 u32 temp = 0; 107 u32 status = in_be32(&usb_phy->status1); 108 109 u32 squelch_prog_rd_0_2 = 110 (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 111 & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK; 112 113 u32 squelch_prog_rd_3_5 = 114 (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 115 & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK; 116 117 setbits_be32(&usb_phy->config1, 118 CFG_SYS_FSL_USB_HS_DISCNCT_INC); 119 setbits_be32(&usb_phy->config2, 120 CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 121 122 temp = squelch_prog_rd_0_2 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 123 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 124 125 temp = squelch_prog_rd_3_5 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 126 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 127#endif 128} 129#endif 130 131 132#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 133extern qe_iop_conf_t qe_iop_conf_tab[]; 134extern void qe_config_iopin(u8 port, u8 pin, int dir, 135 int open_drain, int assign); 136extern void qe_init(uint qe_base); 137extern void qe_reset(void); 138 139static void config_qe_ioports(void) 140{ 141 u8 port, pin; 142 int dir, open_drain, assign; 143 int i; 144 145 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 146 port = qe_iop_conf_tab[i].port; 147 pin = qe_iop_conf_tab[i].pin; 148 dir = qe_iop_conf_tab[i].dir; 149 open_drain = qe_iop_conf_tab[i].open_drain; 150 assign = qe_iop_conf_tab[i].assign; 151 qe_config_iopin(port, pin, dir, open_drain, assign); 152 } 153} 154#endif 155 156#ifdef CONFIG_SYS_FSL_CPC 157#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 158void disable_cpc_sram(void) 159{ 160 int i; 161 162 cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; 163 164 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { 165 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 166 /* find and disable LAW of SRAM */ 167 struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR); 168 169 if (law.index == -1) { 170 printf("\nFatal error happened\n"); 171 return; 172 } 173 disable_law(law.index); 174 175 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 176 out_be32(&cpc->cpccsr0, 0); 177 out_be32(&cpc->cpcsrcr0, 0); 178 } 179 } 180} 181#endif 182 183#if defined(T1040_TDM_QUIRK_CCSR_BASE) 184#ifdef CONFIG_POST 185#error POST memory test cannot be enabled with TDM 186#endif 187static void enable_tdm_law(void) 188{ 189 int ret; 190 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 191 int tdm_hwconfig_enabled = 0; 192 193 /* 194 * Extract hwconfig from environment since environment 195 * is not setup properly yet. Search for tdm entry in 196 * hwconfig. 197 */ 198 ret = env_get_f("hwconfig", buffer, sizeof(buffer)); 199 if (ret > 0) { 200 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 201 /* If tdm is defined in hwconfig, set law for tdm workaround */ 202 if (tdm_hwconfig_enabled) 203 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 204 LAW_TRGT_IF_CCSR); 205 } 206} 207#endif 208 209void enable_cpc(void) 210{ 211 int i; 212 int ret; 213 u32 size = 0; 214 u32 cpccfg0; 215 char buffer[HWCONFIG_BUFFER_SIZE]; 216 char cpc_subarg[16]; 217 bool have_hwconfig = false; 218 int cpc_args = 0; 219 cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; 220 221 /* Extract hwconfig from environment */ 222 ret = env_get_f("hwconfig", buffer, sizeof(buffer)); 223 if (ret > 0) { 224 /* 225 * If "en_cpc" is not defined in hwconfig then by default all 226 * cpcs are enable. If this config is defined then individual 227 * cpcs which have to be enabled should also be defined. 228 * e.g en_cpc:cpc1,cpc2; 229 */ 230 if (hwconfig_f("en_cpc", buffer)) 231 have_hwconfig = true; 232 } 233 234 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { 235 if (have_hwconfig) { 236 sprintf(cpc_subarg, "cpc%u", i + 1); 237 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); 238 if (cpc_args == 0) 239 continue; 240 } 241 cpccfg0 = in_be32(&cpc->cpccfg0); 242 size += CPC_CFG0_SZ_K(cpccfg0); 243 244#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 245 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 246#endif 247#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 248 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 249#endif 250#ifdef CONFIG_SYS_FSL_ERRATUM_A006593 251 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 252#endif 253#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 254 if (has_erratum_a006379()) { 255 setbits_be32(&cpc->cpchdbcr0, 256 CPC_HDBCR0_SPLRU_LEVEL_EN); 257 } 258#endif 259 260 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 261 /* Read back to sync write */ 262 in_be32(&cpc->cpccsr0); 263 264 } 265 266 puts("Corenet Platform Cache: "); 267 print_size(size * 1024, " enabled\n"); 268} 269 270static void invalidate_cpc(void) 271{ 272 int i; 273 cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; 274 275 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { 276 /* skip CPC when it used as all SRAM */ 277 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 278 continue; 279 /* Flash invalidate the CPC and clear all the locks */ 280 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 281 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 282 ; 283 } 284} 285#else 286#define enable_cpc() 287#define invalidate_cpc() 288#define disable_cpc_sram() 289#endif /* CONFIG_SYS_FSL_CPC */ 290 291/* 292 * Breathe some life into the CPU... 293 * 294 * Set up the memory map 295 * initialize a bunch of registers 296 */ 297 298#ifdef CONFIG_FSL_CORENET 299static void corenet_tb_init(void) 300{ 301 volatile ccsr_rcpm_t *rcpm = 302 (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR); 303 volatile ccsr_pic_t *pic = 304 (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); 305 u32 whoami = in_be32(&pic->whoami); 306 307 /* Enable the timebase register for this core */ 308 out_be32(&rcpm->ctbenrl, (1 << whoami)); 309} 310#endif 311 312#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 313void fsl_erratum_a007212_workaround(void) 314{ 315 ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 316 u32 ddr_pll_ratio; 317 u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20); 318 u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28); 319 u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80); 320#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 321 u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40); 322 u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48); 323#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 324 u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60); 325 u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68); 326#endif 327#endif 328 /* 329 * Even this workaround applies to selected version of SoCs, it is 330 * safe to apply to all versions, with the limitation of odd ratios. 331 * If RCW has disabled DDR PLL, we have to apply this workaround, 332 * otherwise DDR will not work. 333 */ 334 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 335 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 336 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 337 /* check if RCW sets ratio to 0, required by this workaround */ 338 if (ddr_pll_ratio != 0) 339 return; 340 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 341 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 342 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 343 /* check if reserved bits have the desired ratio */ 344 if (ddr_pll_ratio == 0) { 345 printf("Error: Unknown DDR PLL ratio!\n"); 346 return; 347 } 348 ddr_pll_ratio >>= 1; 349 350 setbits_be32(plldadcr1, 0x02000001); 351#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 352 setbits_be32(plldadcr2, 0x02000001); 353#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 354 setbits_be32(plldadcr3, 0x02000001); 355#endif 356#endif 357 setbits_be32(dpdovrcr4, 0xe0000000); 358 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 359#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 360 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 361#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 362 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 363#endif 364#endif 365 udelay(100); 366 clrbits_be32(plldadcr1, 0x02000001); 367#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 368 clrbits_be32(plldadcr2, 0x02000001); 369#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 370 clrbits_be32(plldadcr3, 0x02000001); 371#endif 372#endif 373 clrbits_be32(dpdovrcr4, 0xe0000000); 374} 375#endif 376 377ulong cpu_init_f(void) 378{ 379 extern void m8560_cpm_reset (void); 380#ifdef CFG_SYS_DCSRBAR_PHYS 381 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 382#endif 383#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) 384 struct law_entry law; 385#endif 386#ifdef CONFIG_ARCH_MPC8548 387 ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); 388 uint svr = get_svr(); 389 390 /* 391 * CPU2 errata workaround: A core hang possible while executing 392 * a msync instruction and a snoopable transaction from an I/O 393 * master tagged to make quick forward progress is present. 394 * Fixed in silicon rev 2.1. 395 */ 396 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 397 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 398#endif 399 400 disable_tlb(14); 401 disable_tlb(15); 402 403#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) 404 /* Disable the LAW created for NOR flash by the PBI commands */ 405 law = find_law(CFG_SYS_PBI_FLASH_BASE); 406 if (law.index != -1) 407 disable_law(law.index); 408 409#if defined(CONFIG_SYS_CPC_REINIT_F) 410 disable_cpc_sram(); 411#endif 412#endif 413 414 init_early_memctl_regs(); 415 416#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 417 /* Config QE ioports */ 418 config_qe_ioports(); 419#endif 420 421#if defined(CONFIG_FSL_DMA) 422 dma_init(); 423#endif 424#ifdef CONFIG_FSL_CORENET 425 corenet_tb_init(); 426#endif 427 init_used_tlb_cams(); 428 429 /* Invalidate the CPC before DDR gets enabled */ 430 invalidate_cpc(); 431 432 #ifdef CFG_SYS_DCSRBAR_PHYS 433 /* set DCSRCR so that DCSR space is 1G */ 434 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 435 in_be32(&gur->dcsrcr); 436#endif 437 438#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 439 fsl_erratum_a007212_workaround(); 440#endif 441 442 return 0; 443} 444 445/* Implement a dummy function for those platforms w/o SERDES */ 446static void __fsl_serdes__init(void) 447{ 448 return; 449} 450__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 451 452#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 453int enable_cluster_l2(void) 454{ 455 int i = 0; 456 u32 cluster, svr = get_svr(); 457 ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); 458 struct ccsr_cluster_l2 __iomem *l2cache; 459 460 /* only the L2 of first cluster should be enabled as expected on T4080, 461 * but there is no EOC in the first cluster as HW sake, so return here 462 * to skip enabling L2 cache of the 2nd cluster. 463 */ 464 if (SVR_SOC_VER(svr) == SVR_T4080) 465 return 0; 466 467 cluster = in_be32(&gur->tp_cluster[i].lower); 468 if (cluster & TP_CLUSTER_EOC) 469 return 0; 470 471 /* The first cache has already been set up, so skip it */ 472 i++; 473 474 /* Look through the remaining clusters, and set up their caches */ 475 do { 476 int j, cluster_valid = 0; 477 478 l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 479 480 cluster = in_be32(&gur->tp_cluster[i].lower); 481 482 /* check that at least one core/accel is enabled in cluster */ 483 for (j = 0; j < 4; j++) { 484 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 485 u32 type = in_be32(&gur->tp_ityp[idx]); 486 487 if ((type & TP_ITYP_AV) && 488 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 489 cluster_valid = 1; 490 } 491 492 if (cluster_valid) { 493 /* set stash ID to (cluster) * 2 + 32 + 1 */ 494 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 495 496 printf("enable l2 for cluster %d %p\n", i, l2cache); 497 498 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 499 while ((in_be32(&l2cache->l2csr0) 500 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 501 ; 502 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 503 } 504 i++; 505 } while (!(cluster & TP_CLUSTER_EOC)); 506 507 return 0; 508} 509#endif 510 511/* 512 * Initialize L2 as cache. 513 */ 514int l2cache_init(void) 515{ 516 __maybe_unused u32 svr = get_svr(); 517#ifdef CONFIG_L2_CACHE 518 ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR; 519#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 520 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2; 521#endif 522 523 puts ("L2: "); 524 525#if defined(CONFIG_L2_CACHE) 526 volatile uint cache_ctl; 527 uint ver; 528 u32 l2siz_field; 529 530 ver = SVR_SOC_VER(svr); 531 532 asm("msync;isync"); 533 cache_ctl = l2cache->l2ctl; 534 535#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR) 536 if (cache_ctl & MPC85xx_L2CTL_L2E) { 537 /* Clear L2 SRAM memory-mapped base address */ 538 out_be32(&l2cache->l2srbar0, 0x0); 539 out_be32(&l2cache->l2srbar1, 0x0); 540 541 /* set MBECCDIS=0, SBECCDIS=0 */ 542 clrbits_be32(&l2cache->l2errdis, 543 (MPC85xx_L2ERRDIS_MBECC | 544 MPC85xx_L2ERRDIS_SBECC)); 545 546 /* set L2E=0, L2SRAM=0 */ 547 clrbits_be32(&l2cache->l2ctl, 548 (MPC85xx_L2CTL_L2E | 549 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 550 } 551#endif 552 553 l2siz_field = (cache_ctl >> 28) & 0x3; 554 555 switch (l2siz_field) { 556 case 0x0: 557 printf(" unknown size (0x%08x)\n", cache_ctl); 558 return -1; 559 break; 560 case 0x1: 561 if (ver == SVR_8540 || ver == SVR_8560 || 562 ver == SVR_8541 || ver == SVR_8555) { 563 puts("128 KiB "); 564 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 565 cache_ctl = 0xc4000000; 566 } else { 567 puts("256 KiB "); 568 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 569 } 570 break; 571 case 0x2: 572 if (ver == SVR_8540 || ver == SVR_8560 || 573 ver == SVR_8541 || ver == SVR_8555) { 574 puts("256 KiB "); 575 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 576 cache_ctl = 0xc8000000; 577 } else { 578 puts("512 KiB "); 579 /* set L2E=1, L2I=1, & L2SRAM=0 */ 580 cache_ctl = 0xc0000000; 581 } 582 break; 583 case 0x3: 584 puts("1024 KiB "); 585 /* set L2E=1, L2I=1, & L2SRAM=0 */ 586 cache_ctl = 0xc0000000; 587 break; 588 } 589 590 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 591 puts("already enabled"); 592#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE) 593 u32 l2srbar = l2cache->l2srbar0; 594 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 595 && l2srbar >= CFG_SYS_FLASH_BASE) { 596 l2srbar = CFG_SYS_INIT_L2_ADDR; 597 l2cache->l2srbar0 = l2srbar; 598 printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR); 599 } 600#endif /* CFG_SYS_INIT_L2_ADDR */ 601 puts("\n"); 602 } else { 603 asm("msync;isync"); 604 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 605 asm("msync;isync"); 606 puts("enabled\n"); 607 } 608#elif defined(CONFIG_BACKSIDE_L2_CACHE) 609 if (SVR_SOC_VER(svr) == SVR_P2040) { 610 puts("N/A\n"); 611 goto skip_l2; 612 } 613 614 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 615 616 /* invalidate the L2 cache */ 617 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 618 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 619 ; 620 621#ifdef CONFIG_SYS_CACHE_STASHING 622 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 623 mtspr(SPRN_L2CSR1, (32 + 1)); 624#endif 625 626 /* enable the cache */ 627 mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0); 628 629 if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 630 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 631 ; 632 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 633 } 634 635skip_l2: 636#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 637 if (l2cache->l2csr0 & L2CSR0_L2E) 638 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 639 " enabled\n"); 640 641 enable_cluster_l2(); 642#else 643 puts("disabled\n"); 644#endif 645 646 return 0; 647} 648 649/* 650 * 651 * The newer 8548, etc, parts have twice as much cache, but 652 * use the same bit-encoding as the older 8555, etc, parts. 653 * 654 */ 655int cpu_init_r(void) 656{ 657 __maybe_unused u32 svr = get_svr(); 658#ifdef CFG_SYS_LBC_LCRR 659 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 660#endif 661#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 662 extern int spin_table_compat; 663 const char *spin; 664#endif 665#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 666 ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR; 667#endif 668#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 669 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 670 /* 671 * CPU22 and NMG_CPU_A011 share the same workaround. 672 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 673 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 674 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 675 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 676 * be disabled by hwconfig with syntax: 677 * 678 * fsl_cpu_a011:disable 679 */ 680 extern int enable_cpu_a011_workaround; 681#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 682 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 683#else 684 char buffer[HWCONFIG_BUFFER_SIZE]; 685 char *buf = NULL; 686 int n, res; 687 688 n = env_get_f("hwconfig", buffer, sizeof(buffer)); 689 if (n > 0) 690 buf = buffer; 691 692 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 693 if (res > 0) { 694 enable_cpu_a011_workaround = 0; 695 } else { 696 if (n >= HWCONFIG_BUFFER_SIZE) { 697 printf("fsl_cpu_a011 was not found. hwconfig variable " 698 "may be too long\n"); 699 } 700 enable_cpu_a011_workaround = 701 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 702 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 703 } 704#endif 705 if (enable_cpu_a011_workaround) { 706 flush_dcache(); 707 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 708 sync(); 709 } 710#endif 711 712#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 713 flush_dcache(); 714 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); 715 sync(); 716#endif 717 718#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 719 /* 720 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 721 * in write shadow mode. Checking DCWS before setting SPR 976. 722 */ 723 if (mfspr(L1CSR2) & L1CSR2_DCWS) 724 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 725#endif 726 727#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 728 spin = env_get("spin_table_compat"); 729 if (spin && (*spin == 'n')) 730 spin_table_compat = 0; 731 else 732 spin_table_compat = 1; 733#endif 734 735#ifdef CONFIG_FSL_CORENET 736 set_liodns(); 737#ifdef CONFIG_SYS_DPAA_QBMAN 738 setup_qbman_portals(); 739#endif 740#endif 741 742 l2cache_init(); 743#if defined(CONFIG_RAMBOOT_PBL) 744 disable_cpc_sram(); 745#endif 746 enable_cpc(); 747#if defined(T1040_TDM_QUIRK_CCSR_BASE) 748 enable_tdm_law(); 749#endif 750 751#ifndef CONFIG_SYS_FSL_NO_SERDES 752 /* needs to be in ram since code uses global static vars */ 753 fsl_serdes_init(); 754#endif 755 756#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 757#define MCFGR_AXIPIPE 0x000000f0 758 if (IS_SVR_REV(svr, 1, 0)) 759 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); 760#endif 761 762#ifdef CONFIG_SYS_FSL_ERRATUM_A005871 763 if (IS_SVR_REV(svr, 1, 0)) { 764 int i; 765 __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c; 766 767 for (i = 0; i < 12; i++) { 768 p += i + (i > 5 ? 11 : 0); 769 out_be32(p, 0x2); 770 } 771 p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108; 772 out_be32(p, 0x34); 773 } 774#endif 775 776#ifdef CONFIG_SYS_SRIO 777 srio_init(); 778#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 779 char *s = env_get("bootmaster"); 780 if (s) { 781 if (!strcmp(s, "SRIO1")) { 782 srio_boot_master(1); 783 srio_boot_master_release_slave(1); 784 } 785 if (!strcmp(s, "SRIO2")) { 786 srio_boot_master(2); 787 srio_boot_master_release_slave(2); 788 } 789 } 790#endif 791#endif 792 793#if defined(CONFIG_MP) 794 setup_mp(); 795#endif 796 797#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 798 { 799 if (SVR_MAJ(svr) < 3) { 800 void *p; 801 p = (void *)CFG_SYS_DCSRBAR + 0x20520; 802 setbits_be32(p, 1 << (31 - 14)); 803 } 804 } 805#endif 806 807#ifdef CFG_SYS_LBC_LCRR 808 /* 809 * Modify the CLKDIV field of LCRR register to improve the writing 810 * speed for NOR flash. 811 */ 812 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR); 813 __raw_readl(&lbc->lcrr); 814 isync(); 815#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 816 udelay(100); 817#endif 818#endif 819 820#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 821 { 822 struct ccsr_usb_phy __iomem *usb_phy1 = 823 (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; 824#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 825 if (has_erratum_a006261()) 826 fsl_erratum_a006261_workaround(usb_phy1); 827#endif 828 out_be32(&usb_phy1->usb_enable_override, 829 CFG_SYS_FSL_USB_ENABLE_OVERRIDE); 830 } 831#endif 832#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 833 { 834 struct ccsr_usb_phy __iomem *usb_phy2 = 835 (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR; 836#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 837 if (has_erratum_a006261()) 838 fsl_erratum_a006261_workaround(usb_phy2); 839#endif 840 out_be32(&usb_phy2->usb_enable_override, 841 CFG_SYS_FSL_USB_ENABLE_OVERRIDE); 842 } 843#endif 844 845#ifdef CONFIG_SYS_FSL_ERRATUM_USB14 846 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 847 * multi-bit ECC errors which has impact on performance, so software 848 * should disable all ECC reporting from USB1 and USB2. 849 */ 850 if (IS_SVR_REV(get_svr(), 1, 0)) { 851 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 852 (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET); 853 setbits_be32(&dcfg->ecccr1, 854 (DCSR_DCFG_ECC_DISABLE_USB1 | 855 DCSR_DCFG_ECC_DISABLE_USB2)); 856 } 857#endif 858 859#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 860 struct ccsr_usb_phy __iomem *usb_phy = 861 (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; 862 setbits_be32(&usb_phy->pllprg[1], 863 CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 864 CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 865 CFG_SYS_FSL_USB_PLLPRG2_MFI | 866 CFG_SYS_FSL_USB_PLLPRG2_PLL_EN); 867#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 868 usb_single_source_clk_configure(usb_phy); 869#endif 870 setbits_be32(&usb_phy->port1.ctrl, 871 CFG_SYS_FSL_USB_CTRL_PHY_EN); 872 setbits_be32(&usb_phy->port1.drvvbuscfg, 873 CFG_SYS_FSL_USB_DRVVBUS_CR_EN); 874 setbits_be32(&usb_phy->port1.pwrfltcfg, 875 CFG_SYS_FSL_USB_PWRFLT_CR_EN); 876 setbits_be32(&usb_phy->port2.ctrl, 877 CFG_SYS_FSL_USB_CTRL_PHY_EN); 878 setbits_be32(&usb_phy->port2.drvvbuscfg, 879 CFG_SYS_FSL_USB_DRVVBUS_CR_EN); 880 setbits_be32(&usb_phy->port2.pwrfltcfg, 881 CFG_SYS_FSL_USB_PWRFLT_CR_EN); 882 883#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 884 if (has_erratum_a006261()) 885 fsl_erratum_a006261_workaround(usb_phy); 886#endif 887 888#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 889 890#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 891 erratum_a009942_check_cpo(); 892#endif 893 894#ifdef CONFIG_FMAN_ENET 895#ifndef CONFIG_DM_ETH 896 fman_enet_init(); 897#endif 898#endif 899 900#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) 901 if (pamu_init() < 0) 902 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); 903#endif 904 905#ifdef CONFIG_FSL_CAAM 906#if defined(CONFIG_ARCH_C29X) 907 if ((SVR_SOC_VER(svr) == SVR_C292) || 908 (SVR_SOC_VER(svr) == SVR_C293)) 909 sec_init_idx(1); 910 911 if (SVR_SOC_VER(svr) == SVR_C293) 912 sec_init_idx(2); 913#endif 914#endif 915 916#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001) 917 /* 918 * For P1022/1013 Rev1.0 silicon, after power on SATA host 919 * controller is configured in legacy mode instead of the 920 * expected enterprise mode. Software needs to clear bit[28] 921 * of HControl register to change to enterprise mode from 922 * legacy mode. We assume that the controller is offline. 923 */ 924 if (IS_SVR_REV(svr, 1, 0) && 925 ((SVR_SOC_VER(svr) == SVR_P1022) || 926 (SVR_SOC_VER(svr) == SVR_P1013))) { 927 fsl_sata_reg_t *reg; 928 929 /* first SATA controller */ 930 reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR; 931 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 932 933 /* second SATA controller */ 934 reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR; 935 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 936 } 937#endif 938 939 init_used_tlb_cams(); 940 941 return 0; 942} 943 944#ifdef CONFIG_ARCH_MISC_INIT 945int arch_misc_init(void) 946{ 947 if (IS_ENABLED(CONFIG_FSL_CAAM)) { 948 struct udevice *dev; 949 int ret; 950 951 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); 952 if (ret) 953 printf("Failed to initialize caam_jr: %d\n", ret); 954 } 955 956 return 0; 957} 958#endif 959 960void arch_preboot_os(void) 961{ 962 u32 msr; 963 964 /* 965 * We are changing interrupt offsets and are about to boot the OS so 966 * we need to make sure we disable all async interrupts. EE is already 967 * disabled by the time we get called. 968 */ 969 msr = mfmsr(); 970 msr &= ~(MSR_ME|MSR_CE); 971 mtmsr(msr); 972} 973 974int cpu_secondary_init_r(void) 975{ 976#ifdef CONFIG_QE 977#ifdef CONFIG_U_QE 978 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 979#else 980 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 981#endif 982 983 qe_init(qe_base); 984 qe_reset(); 985#endif 986 987 return 0; 988} 989 990#ifdef CONFIG_BOARD_LATE_INIT 991int board_late_init(void) 992{ 993#ifdef CONFIG_CHAIN_OF_TRUST 994 fsl_setenv_chain_of_trust(); 995#endif 996 997 return 0; 998} 999#endif 1000