| /u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_axp_vars.h | 16 {"db_800-400", 0xA, 0x5, 0x0, A0, ddr3_A0_db_400, NULL},
17 {"db_1200-300", 0x2, 0xC, 0x0, A0, ddr3_A0_db_400, NULL},
18 {"db_1200-600", 0x2, 0x5, 0x0, A0, NULL, NULL},
19 {"db_1333-667", 0x3, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_667},
20 {"db_1600-800", 0xB, 0x5, 0x0, A0, ddr3_A0_db_667, ddr3_db_rev2_800},
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| H A D | ddr3_hw_training.h | 301 A0, enumerator in enum:board_rev
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| H A D | ddr3_init.c | 860 chip_board_rev = A0;
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| /u-boot/board/maxbcm/ |
| H A D | maxbcm.c | 80 {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL},
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| /u-boot/board/Synology/ds414/ |
| H A D | ds414.c | 105 {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
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| /u-boot/lib/lzma/ |
| H A D | LzmaDec.c | 24 #define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \
25 { UPDATE_0(p); i = (i + i); A0; } else \
54 #define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \
55 { UPDATE_0_CHECK; i = (i + i); A0; } else \
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| /u-boot/board/theadorable/ |
| H A D | theadorable.c | 107 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
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| /u-boot/drivers/pinctrl/renesas/ |
| H A D | pfc-r8a77970.c | 165 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 PINMUX_IPSR_GPSR(IP0_3_0, A0),
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| H A D | pfc-r8a77990.c | 113 #define GPSR1_0 F_(A0, IP2_31_28)
240 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
657 PINMUX_IPSR_GPSR(IP2_31_28, A0),
5142 [27] = RCAR_GP_PIN(1, 0), /* A0 */
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| H A D | pfc-r8a77980.c | 199 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 PINMUX_IPSR_GPSR(IP0_3_0, A0),
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| H A D | pfc-r8a77965.c | 134 #define GPSR1_0 F_(A0, IP1_31_28)
276 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
743 PINMUX_IPSR_GPSR(IP1_31_28, A0),
5870 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
6136 [12] = RCAR_GP_PIN(1, 0), /* A0 */
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| H A D | pfc-r8a77951.c | 128 #define GPSR1_0 F_(A0, IP1_31_28)
270 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
736 PINMUX_IPSR_GPSR(IP1_31_28, A0),
5673 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5942 [12] = RCAR_GP_PIN(1, 0), /* A0 */
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| H A D | pfc-r8a7796.c | 134 #define GPSR1_0 F_(A0, IP1_31_28)
276 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
741 PINMUX_IPSR_GPSR(IP1_31_28, A0),
5629 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5895 [12] = RCAR_GP_PIN(1, 0), /* A0 */
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| H A D | pfc-r8a7792.c | 376 PINMUX_SINGLE(A0),
2720 [16] = RCAR_GP_PIN(2, 16), /* A0 */
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| H A D | pfc-r8a779a0.c | 359 #define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
794 PINMUX_IPSR_GPSR(IP0SR1_3_0, A0),
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| H A D | pfc-r8a7791.c | 857 PINMUX_IPSR_GPSR(IP0_18_16, A0),
6594 [22] = RCAR_GP_PIN(0, 16), /* A0 */
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| H A D | pfc-r8a7790.c | 904 PINMUX_IPSR_GPSR(IP1_27_26, A0),
5841 [ 0] = RCAR_GP_PIN(0, 16), /* A0 */
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| H A D | pfc-r8a7794.c | 833 PINMUX_IPSR_GPSR(IP1_23_22, A0),
5558 [16] = RCAR_GP_PIN(0, 16), /* A0 */
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