1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R8A779A0 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c 8 */ 9 10#include <dm.h> 11#include <errno.h> 12#include <dm/pinctrl.h> 13#include <linux/bitops.h> 14#include <linux/kernel.h> 15 16#include "sh_pfc.h" 17 18#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 19 20#define CPU_ALL_GP(fn, sfx) \ 21 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \ 22 PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 23 PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 24 PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 25 PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 26 PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 27 PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 28 PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 29 PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 30 PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 31 PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 32 PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 33 PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 34 PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 35 PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 36 PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \ 37 PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 38 PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 39 PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 40 PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 41 PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 42 PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 43 PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 44 PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 45 PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 46 PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 47 PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 48 PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 49 PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 50 PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 51 PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \ 52 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \ 53 PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \ 54 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \ 55 PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \ 56 PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \ 57 PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \ 58 PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \ 59 PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \ 60 PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \ 61 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ 62 PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \ 63 PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \ 64 PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \ 65 PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \ 66 PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \ 67 PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \ 68 PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \ 69 PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \ 70 PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \ 71 PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ 72 PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \ 73 PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \ 74 PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \ 75 PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ 76 PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \ 77 PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \ 78 PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \ 79 PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ 80 PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \ 81 PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \ 82 PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \ 83 PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ 84 PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \ 85 PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \ 86 PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \ 87 PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ 88 PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \ 89 PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \ 90 PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS) 91 92#define CPU_ALL_NOGP(fn) \ 93 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 94 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 95 PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 96 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 97 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 98 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 99 100/* 101 * F_() : just information 102 * FM() : macro for FN_xxx / xxx_MARK 103 */ 104 105/* GPSR0 */ 106#define GPSR0_27 FM(MMC_D7) 107#define GPSR0_26 FM(MMC_D6) 108#define GPSR0_25 FM(MMC_D5) 109#define GPSR0_24 FM(MMC_D4) 110#define GPSR0_23 FM(MMC_SD_CLK) 111#define GPSR0_22 FM(MMC_SD_D3) 112#define GPSR0_21 FM(MMC_SD_D2) 113#define GPSR0_20 FM(MMC_SD_D1) 114#define GPSR0_19 FM(MMC_SD_D0) 115#define GPSR0_18 FM(MMC_SD_CMD) 116#define GPSR0_17 FM(MMC_DS) 117#define GPSR0_16 FM(SD_CD) 118#define GPSR0_15 FM(SD_WP) 119#define GPSR0_14 FM(RPC_INT_N) 120#define GPSR0_13 FM(RPC_WP_N) 121#define GPSR0_12 FM(RPC_RESET_N) 122#define GPSR0_11 FM(QSPI1_SSL) 123#define GPSR0_10 FM(QSPI1_IO3) 124#define GPSR0_9 FM(QSPI1_IO2) 125#define GPSR0_8 FM(QSPI1_MISO_IO1) 126#define GPSR0_7 FM(QSPI1_MOSI_IO0) 127#define GPSR0_6 FM(QSPI1_SPCLK) 128#define GPSR0_5 FM(QSPI0_SSL) 129#define GPSR0_4 FM(QSPI0_IO3) 130#define GPSR0_3 FM(QSPI0_IO2) 131#define GPSR0_2 FM(QSPI0_MISO_IO1) 132#define GPSR0_1 FM(QSPI0_MOSI_IO0) 133#define GPSR0_0 FM(QSPI0_SPCLK) 134 135/* GPSR1 */ 136#define GPSR1_30 F_(GP1_30, IP3SR1_27_24) 137#define GPSR1_29 F_(GP1_29, IP3SR1_23_20) 138#define GPSR1_28 F_(GP1_28, IP3SR1_19_16) 139#define GPSR1_27 F_(IRQ3, IP3SR1_15_12) 140#define GPSR1_26 F_(IRQ2, IP3SR1_11_8) 141#define GPSR1_25 F_(IRQ1, IP3SR1_7_4) 142#define GPSR1_24 F_(IRQ0, IP3SR1_3_0) 143#define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28) 144#define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24) 145#define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20) 146#define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16) 147#define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12) 148#define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8) 149#define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4) 150#define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0) 151#define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28) 152#define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24) 153#define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20) 154#define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16) 155#define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12) 156#define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8) 157#define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4) 158#define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0) 159#define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28) 160#define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24) 161#define GPSR1_5 F_(HTX0, IP0SR1_23_20) 162#define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16) 163#define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12) 164#define GPSR1_2 F_(HSCK0, IP0SR1_11_8) 165#define GPSR1_1 F_(HRX0, IP0SR1_7_4) 166#define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0) 167 168/* GPSR2 */ 169#define GPSR2_24 FM(TCLK2_A) 170#define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28) 171#define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24) 172#define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20) 173#define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16) 174#define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12) 175#define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8) 176#define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4) 177#define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0) 178#define GPSR2_15 F_(GP2_15, IP1SR2_31_28) 179#define GPSR2_14 F_(GP2_14, IP1SR2_27_24) 180#define GPSR2_13 F_(GP2_13, IP1SR2_23_20) 181#define GPSR2_12 F_(GP2_12, IP1SR2_19_16) 182#define GPSR2_11 F_(GP2_11, IP1SR2_15_12) 183#define GPSR2_10 F_(GP2_10, IP1SR2_11_8) 184#define GPSR2_9 F_(GP2_09, IP1SR2_7_4) 185#define GPSR2_8 F_(GP2_08, IP1SR2_3_0) 186#define GPSR2_7 F_(GP2_07, IP0SR2_31_28) 187#define GPSR2_6 F_(GP2_06, IP0SR2_27_24) 188#define GPSR2_5 F_(GP2_05, IP0SR2_23_20) 189#define GPSR2_4 F_(GP2_04, IP0SR2_19_16) 190#define GPSR2_3 F_(GP2_03, IP0SR2_15_12) 191#define GPSR2_2 F_(GP2_02, IP0SR2_11_8) 192#define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4) 193#define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0) 194 195/* GPSR3 */ 196#define GPSR3_16 FM(CANFD7_RX) 197#define GPSR3_15 FM(CANFD7_TX) 198#define GPSR3_14 FM(CANFD6_RX) 199#define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20) 200#define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16) 201#define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12) 202#define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8) 203#define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4) 204#define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0) 205#define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28) 206#define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24) 207#define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20) 208#define GPSR3_4 FM(CANFD1_RX) 209#define GPSR3_3 FM(CANFD1_TX) 210#define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8) 211#define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4) 212#define GPSR3_0 FM(CAN_CLK) 213 214/* GPSR4 */ 215#define GPSR4_26 FM(AVS1) 216#define GPSR4_25 FM(AVS0) 217#define GPSR4_24 FM(PCIE3_CLKREQ_N) 218#define GPSR4_23 FM(PCIE2_CLKREQ_N) 219#define GPSR4_22 FM(PCIE1_CLKREQ_N) 220#define GPSR4_21 FM(PCIE0_CLKREQ_N) 221#define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16) 222#define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12) 223#define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8) 224#define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4) 225#define GPSR4_16 FM(AVB0_PHY_INT) 226#define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28) 227#define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24) 228#define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20) 229#define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16) 230#define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12) 231#define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8) 232#define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4) 233#define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0) 234#define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28) 235#define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24) 236#define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20) 237#define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16) 238#define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12) 239#define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8) 240#define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4) 241#define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0) 242 243/* GPSR5 */ 244#define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16) 245#define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12) 246#define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8) 247#define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4) 248#define GPSR5_16 FM(AVB1_PHY_INT) 249#define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28) 250#define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24) 251#define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20) 252#define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16) 253#define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12) 254#define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8) 255#define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4) 256#define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0) 257#define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28) 258#define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24) 259#define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20) 260#define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16) 261#define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12) 262#define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8) 263#define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4) 264#define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0) 265 266/* GPSR6 */ 267#define GPSR6_20 FM(AVB2_AVTP_PPS) 268#define GPSR6_19 FM(AVB2_AVTP_CAPTURE) 269#define GPSR6_18 FM(AVB2_AVTP_MATCH) 270#define GPSR6_17 FM(AVB2_LINK) 271#define GPSR6_16 FM(AVB2_PHY_INT) 272#define GPSR6_15 FM(AVB2_MAGIC) 273#define GPSR6_14 FM(AVB2_MDC) 274#define GPSR6_13 FM(AVB2_MDIO) 275#define GPSR6_12 FM(AVB2_TXCREFCLK) 276#define GPSR6_11 FM(AVB2_TD3) 277#define GPSR6_10 FM(AVB2_TD2) 278#define GPSR6_9 FM(AVB2_TD1) 279#define GPSR6_8 FM(AVB2_TD0) 280#define GPSR6_7 FM(AVB2_TXC) 281#define GPSR6_6 FM(AVB2_TX_CTL) 282#define GPSR6_5 FM(AVB2_RD3) 283#define GPSR6_4 FM(AVB2_RD2) 284#define GPSR6_3 FM(AVB2_RD1) 285#define GPSR6_2 FM(AVB2_RD0) 286#define GPSR6_1 FM(AVB2_RXC) 287#define GPSR6_0 FM(AVB2_RX_CTL) 288 289/* GPSR7 */ 290#define GPSR7_20 FM(AVB3_AVTP_PPS) 291#define GPSR7_19 FM(AVB3_AVTP_CAPTURE) 292#define GPSR7_18 FM(AVB3_AVTP_MATCH) 293#define GPSR7_17 FM(AVB3_LINK) 294#define GPSR7_16 FM(AVB3_PHY_INT) 295#define GPSR7_15 FM(AVB3_MAGIC) 296#define GPSR7_14 FM(AVB3_MDC) 297#define GPSR7_13 FM(AVB3_MDIO) 298#define GPSR7_12 FM(AVB3_TXCREFCLK) 299#define GPSR7_11 FM(AVB3_TD3) 300#define GPSR7_10 FM(AVB3_TD2) 301#define GPSR7_9 FM(AVB3_TD1) 302#define GPSR7_8 FM(AVB3_TD0) 303#define GPSR7_7 FM(AVB3_TXC) 304#define GPSR7_6 FM(AVB3_TX_CTL) 305#define GPSR7_5 FM(AVB3_RD3) 306#define GPSR7_4 FM(AVB3_RD2) 307#define GPSR7_3 FM(AVB3_RD1) 308#define GPSR7_2 FM(AVB3_RD0) 309#define GPSR7_1 FM(AVB3_RXC) 310#define GPSR7_0 FM(AVB3_RX_CTL) 311 312/* GPSR8 */ 313#define GPSR8_20 FM(AVB4_AVTP_PPS) 314#define GPSR8_19 FM(AVB4_AVTP_CAPTURE) 315#define GPSR8_18 FM(AVB4_AVTP_MATCH) 316#define GPSR8_17 FM(AVB4_LINK) 317#define GPSR8_16 FM(AVB4_PHY_INT) 318#define GPSR8_15 FM(AVB4_MAGIC) 319#define GPSR8_14 FM(AVB4_MDC) 320#define GPSR8_13 FM(AVB4_MDIO) 321#define GPSR8_12 FM(AVB4_TXCREFCLK) 322#define GPSR8_11 FM(AVB4_TD3) 323#define GPSR8_10 FM(AVB4_TD2) 324#define GPSR8_9 FM(AVB4_TD1) 325#define GPSR8_8 FM(AVB4_TD0) 326#define GPSR8_7 FM(AVB4_TXC) 327#define GPSR8_6 FM(AVB4_TX_CTL) 328#define GPSR8_5 FM(AVB4_RD3) 329#define GPSR8_4 FM(AVB4_RD2) 330#define GPSR8_3 FM(AVB4_RD1) 331#define GPSR8_2 FM(AVB4_RD0) 332#define GPSR8_1 FM(AVB4_RXC) 333#define GPSR8_0 FM(AVB4_RX_CTL) 334 335/* GPSR9 */ 336#define GPSR9_20 FM(AVB5_AVTP_PPS) 337#define GPSR9_19 FM(AVB5_AVTP_CAPTURE) 338#define GPSR9_18 FM(AVB5_AVTP_MATCH) 339#define GPSR9_17 FM(AVB5_LINK) 340#define GPSR9_16 FM(AVB5_PHY_INT) 341#define GPSR9_15 FM(AVB5_MAGIC) 342#define GPSR9_14 FM(AVB5_MDC) 343#define GPSR9_13 FM(AVB5_MDIO) 344#define GPSR9_12 FM(AVB5_TXCREFCLK) 345#define GPSR9_11 FM(AVB5_TD3) 346#define GPSR9_10 FM(AVB5_TD2) 347#define GPSR9_9 FM(AVB5_TD1) 348#define GPSR9_8 FM(AVB5_TD0) 349#define GPSR9_7 FM(AVB5_TXC) 350#define GPSR9_6 FM(AVB5_TX_CTL) 351#define GPSR9_5 FM(AVB5_RD3) 352#define GPSR9_4 FM(AVB5_RD2) 353#define GPSR9_3 FM(AVB5_RD1) 354#define GPSR9_2 FM(AVB5_RD0) 355#define GPSR9_1 FM(AVB5_RXC) 356#define GPSR9_0 FM(AVB5_RX_CTL) 357 358/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 359#define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360#define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361#define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362#define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363#define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364#define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365#define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366#define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 368#define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369#define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370#define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371#define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372#define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373#define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374#define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375#define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 377#define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378#define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379#define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380#define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381#define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382#define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383#define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384#define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385 386/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 387#define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388#define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389#define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390#define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 395/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 396#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397#define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398#define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399#define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400#define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401#define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402#define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403#define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 405#define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 406#define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 407#define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 408#define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 409#define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 410#define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411#define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 412#define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 413/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 414#define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 415#define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 416#define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 417#define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 418#define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 419#define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 420#define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 421#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 422 423/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 424#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 425#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 426#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 427#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 428#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 429/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 430#define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 431#define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 432#define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 433#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 434#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 435#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 436 437/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 438#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 439#define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 440#define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 441#define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 442#define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 443#define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 444#define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 445#define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 446/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 447#define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 448#define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 449#define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 450#define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 451#define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 452#define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 453#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 454#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 455/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 456#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 457#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 458#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 459#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 460 461/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 462#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 463#define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 464#define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 465#define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 466#define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 467#define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 468#define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 469#define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 470/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 471#define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 472#define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 473#define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 474#define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 475#define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 476#define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 477#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 478#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 479/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 480#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 481#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 482#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 483#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 484 485#define PINMUX_GPSR \ 486 \ 487 GPSR1_30 \ 488 GPSR1_29 \ 489 GPSR1_28 \ 490GPSR0_27 GPSR1_27 \ 491GPSR0_26 GPSR1_26 GPSR4_26 \ 492GPSR0_25 GPSR1_25 GPSR4_25 \ 493GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \ 494GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \ 495GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \ 496GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ 497GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \ 498GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \ 499GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \ 500GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \ 501GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \ 502GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \ 503GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \ 504GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \ 505GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \ 506GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \ 507GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \ 508GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \ 509GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \ 510GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \ 511GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \ 512GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \ 513GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \ 514GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \ 515GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \ 516GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \ 517GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0 518 519#define PINMUX_IPSR \ 520\ 521FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ 522FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ 523FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ 524FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ 525FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ 526FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ 527FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \ 528FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \ 529\ 530FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \ 531FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ 532FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \ 533FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ 534FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \ 535FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \ 536FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \ 537FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \ 538\ 539 FM(IP1SR3_3_0) IP1SR3_3_0 \ 540FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \ 541FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \ 542 FM(IP1SR3_15_12) IP1SR3_15_12 \ 543 FM(IP1SR3_19_16) IP1SR3_19_16 \ 544FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \ 545FM(IP0SR3_27_24) IP0SR3_27_24 \ 546FM(IP0SR3_31_28) IP0SR3_31_28 \ 547\ 548FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 \ 549FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \ 550FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \ 551FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \ 552FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \ 553FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 \ 554FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \ 555FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 \ 556\ 557FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 \ 558FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ 559FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ 560FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ 561FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ 562FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ 563FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ 564FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 565 566/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 567#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) 568#define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) 569#define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) 570#define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) 571#define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) 572#define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) 573#define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) 574 575#define PINMUX_MOD_SELS \ 576\ 577MOD_SEL2_15_14 \ 578MOD_SEL2_13_12 \ 579MOD_SEL2_11_10 \ 580MOD_SEL2_9_8 \ 581MOD_SEL2_7_6 \ 582MOD_SEL2_5_4 \ 583MOD_SEL2_3_2 584 585#define PINMUX_PHYS \ 586 FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ 587 FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6) 588 589enum { 590 PINMUX_RESERVED = 0, 591 592 PINMUX_DATA_BEGIN, 593 GP_ALL(DATA), 594 PINMUX_DATA_END, 595 596#define F_(x, y) 597#define FM(x) FN_##x, 598 PINMUX_FUNCTION_BEGIN, 599 GP_ALL(FN), 600 PINMUX_GPSR 601 PINMUX_IPSR 602 PINMUX_MOD_SELS 603 PINMUX_FUNCTION_END, 604#undef F_ 605#undef FM 606 607#define F_(x, y) 608#define FM(x) x##_MARK, 609 PINMUX_MARK_BEGIN, 610 PINMUX_GPSR 611 PINMUX_IPSR 612 PINMUX_MOD_SELS 613 PINMUX_PHYS 614 PINMUX_MARK_END, 615#undef F_ 616#undef FM 617}; 618 619static const u16 pinmux_data[] = { 620/* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */ 621#define GP_2_2_FN GP_2_2_FN, FN_SEL_I2C0_0 622#define GP_2_3_FN GP_2_3_FN, FN_SEL_I2C0_0 623#define GP_2_4_FN GP_2_4_FN, FN_SEL_I2C1_0 624#define GP_2_5_FN GP_2_5_FN, FN_SEL_I2C1_0 625#define GP_2_6_FN GP_2_6_FN, FN_SEL_I2C2_0 626#define GP_2_7_FN GP_2_7_FN, FN_SEL_I2C2_0 627#define GP_2_8_FN GP_2_8_FN, FN_SEL_I2C3_0 628#define GP_2_9_FN GP_2_9_FN, FN_SEL_I2C3_0 629#define GP_2_10_FN GP_2_10_FN, FN_SEL_I2C4_0 630#define GP_2_11_FN GP_2_11_FN, FN_SEL_I2C4_0 631#define GP_2_12_FN GP_2_12_FN, FN_SEL_I2C5_0 632#define GP_2_13_FN GP_2_13_FN, FN_SEL_I2C5_0 633#define GP_2_14_FN GP_2_14_FN, FN_SEL_I2C6_0 634#define GP_2_15_FN GP_2_15_FN, FN_SEL_I2C6_0 635 PINMUX_DATA_GP_ALL(), 636#undef GP_2_2_FN 637#undef GP_2_3_FN 638#undef GP_2_4_FN 639#undef GP_2_5_FN 640#undef GP_2_6_FN 641#undef GP_2_7_FN 642#undef GP_2_8_FN 643#undef GP_2_9_FN 644#undef GP_2_10_FN 645#undef GP_2_11_FN 646#undef GP_2_12_FN 647#undef GP_2_13_FN 648#undef GP_2_14_FN 649#undef GP_2_15_FN 650 651 PINMUX_SINGLE(MMC_D7), 652 PINMUX_SINGLE(MMC_D6), 653 PINMUX_SINGLE(MMC_D5), 654 PINMUX_SINGLE(MMC_D4), 655 PINMUX_SINGLE(MMC_SD_CLK), 656 PINMUX_SINGLE(MMC_SD_D3), 657 PINMUX_SINGLE(MMC_SD_D2), 658 PINMUX_SINGLE(MMC_SD_D1), 659 PINMUX_SINGLE(MMC_SD_D0), 660 PINMUX_SINGLE(MMC_SD_CMD), 661 PINMUX_SINGLE(MMC_DS), 662 663 PINMUX_SINGLE(SD_CD), 664 PINMUX_SINGLE(SD_WP), 665 666 PINMUX_SINGLE(RPC_INT_N), 667 PINMUX_SINGLE(RPC_WP_N), 668 PINMUX_SINGLE(RPC_RESET_N), 669 670 PINMUX_SINGLE(QSPI1_SSL), 671 PINMUX_SINGLE(QSPI1_IO3), 672 PINMUX_SINGLE(QSPI1_IO2), 673 PINMUX_SINGLE(QSPI1_MISO_IO1), 674 PINMUX_SINGLE(QSPI1_MOSI_IO0), 675 PINMUX_SINGLE(QSPI1_SPCLK), 676 PINMUX_SINGLE(QSPI0_SSL), 677 PINMUX_SINGLE(QSPI0_IO3), 678 PINMUX_SINGLE(QSPI0_IO2), 679 PINMUX_SINGLE(QSPI0_MISO_IO1), 680 PINMUX_SINGLE(QSPI0_MOSI_IO0), 681 PINMUX_SINGLE(QSPI0_SPCLK), 682 683 PINMUX_SINGLE(TCLK2_A), 684 685 PINMUX_SINGLE(CANFD7_RX), 686 PINMUX_SINGLE(CANFD7_TX), 687 PINMUX_SINGLE(CANFD6_RX), 688 PINMUX_SINGLE(CANFD1_RX), 689 PINMUX_SINGLE(CANFD1_TX), 690 PINMUX_SINGLE(CAN_CLK), 691 692 PINMUX_SINGLE(AVS1), 693 PINMUX_SINGLE(AVS0), 694 695 PINMUX_SINGLE(PCIE3_CLKREQ_N), 696 PINMUX_SINGLE(PCIE2_CLKREQ_N), 697 PINMUX_SINGLE(PCIE1_CLKREQ_N), 698 PINMUX_SINGLE(PCIE0_CLKREQ_N), 699 700 PINMUX_SINGLE(AVB0_PHY_INT), 701 702 PINMUX_SINGLE(AVB1_PHY_INT), 703 704 PINMUX_SINGLE(AVB2_AVTP_PPS), 705 PINMUX_SINGLE(AVB2_AVTP_CAPTURE), 706 PINMUX_SINGLE(AVB2_AVTP_MATCH), 707 PINMUX_SINGLE(AVB2_LINK), 708 PINMUX_SINGLE(AVB2_PHY_INT), 709 PINMUX_SINGLE(AVB2_MAGIC), 710 PINMUX_SINGLE(AVB2_MDC), 711 PINMUX_SINGLE(AVB2_MDIO), 712 PINMUX_SINGLE(AVB2_TXCREFCLK), 713 PINMUX_SINGLE(AVB2_TD3), 714 PINMUX_SINGLE(AVB2_TD2), 715 PINMUX_SINGLE(AVB2_TD1), 716 PINMUX_SINGLE(AVB2_TD0), 717 PINMUX_SINGLE(AVB2_TXC), 718 PINMUX_SINGLE(AVB2_TX_CTL), 719 PINMUX_SINGLE(AVB2_RD3), 720 PINMUX_SINGLE(AVB2_RD2), 721 PINMUX_SINGLE(AVB2_RD1), 722 PINMUX_SINGLE(AVB2_RD0), 723 PINMUX_SINGLE(AVB2_RXC), 724 PINMUX_SINGLE(AVB2_RX_CTL), 725 726 PINMUX_SINGLE(AVB3_AVTP_PPS), 727 PINMUX_SINGLE(AVB3_AVTP_CAPTURE), 728 PINMUX_SINGLE(AVB3_AVTP_MATCH), 729 PINMUX_SINGLE(AVB3_LINK), 730 PINMUX_SINGLE(AVB3_PHY_INT), 731 PINMUX_SINGLE(AVB3_MAGIC), 732 PINMUX_SINGLE(AVB3_MDC), 733 PINMUX_SINGLE(AVB3_MDIO), 734 PINMUX_SINGLE(AVB3_TXCREFCLK), 735 PINMUX_SINGLE(AVB3_TD3), 736 PINMUX_SINGLE(AVB3_TD2), 737 PINMUX_SINGLE(AVB3_TD1), 738 PINMUX_SINGLE(AVB3_TD0), 739 PINMUX_SINGLE(AVB3_TXC), 740 PINMUX_SINGLE(AVB3_TX_CTL), 741 PINMUX_SINGLE(AVB3_RD3), 742 PINMUX_SINGLE(AVB3_RD2), 743 PINMUX_SINGLE(AVB3_RD1), 744 PINMUX_SINGLE(AVB3_RD0), 745 PINMUX_SINGLE(AVB3_RXC), 746 PINMUX_SINGLE(AVB3_RX_CTL), 747 748 PINMUX_SINGLE(AVB4_AVTP_PPS), 749 PINMUX_SINGLE(AVB4_AVTP_CAPTURE), 750 PINMUX_SINGLE(AVB4_AVTP_MATCH), 751 PINMUX_SINGLE(AVB4_LINK), 752 PINMUX_SINGLE(AVB4_PHY_INT), 753 PINMUX_SINGLE(AVB4_MAGIC), 754 PINMUX_SINGLE(AVB4_MDC), 755 PINMUX_SINGLE(AVB4_MDIO), 756 PINMUX_SINGLE(AVB4_TXCREFCLK), 757 PINMUX_SINGLE(AVB4_TD3), 758 PINMUX_SINGLE(AVB4_TD2), 759 PINMUX_SINGLE(AVB4_TD1), 760 PINMUX_SINGLE(AVB4_TD0), 761 PINMUX_SINGLE(AVB4_TXC), 762 PINMUX_SINGLE(AVB4_TX_CTL), 763 PINMUX_SINGLE(AVB4_RD3), 764 PINMUX_SINGLE(AVB4_RD2), 765 PINMUX_SINGLE(AVB4_RD1), 766 PINMUX_SINGLE(AVB4_RD0), 767 PINMUX_SINGLE(AVB4_RXC), 768 PINMUX_SINGLE(AVB4_RX_CTL), 769 770 PINMUX_SINGLE(AVB5_AVTP_PPS), 771 PINMUX_SINGLE(AVB5_AVTP_CAPTURE), 772 PINMUX_SINGLE(AVB5_AVTP_MATCH), 773 PINMUX_SINGLE(AVB5_LINK), 774 PINMUX_SINGLE(AVB5_PHY_INT), 775 PINMUX_SINGLE(AVB5_MAGIC), 776 PINMUX_SINGLE(AVB5_MDC), 777 PINMUX_SINGLE(AVB5_MDIO), 778 PINMUX_SINGLE(AVB5_TXCREFCLK), 779 PINMUX_SINGLE(AVB5_TD3), 780 PINMUX_SINGLE(AVB5_TD2), 781 PINMUX_SINGLE(AVB5_TD1), 782 PINMUX_SINGLE(AVB5_TD0), 783 PINMUX_SINGLE(AVB5_TXC), 784 PINMUX_SINGLE(AVB5_TX_CTL), 785 PINMUX_SINGLE(AVB5_RD3), 786 PINMUX_SINGLE(AVB5_RD2), 787 PINMUX_SINGLE(AVB5_RD1), 788 PINMUX_SINGLE(AVB5_RD0), 789 PINMUX_SINGLE(AVB5_RXC), 790 PINMUX_SINGLE(AVB5_RX_CTL), 791 792 /* IP0SR1 */ 793 PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK), 794 PINMUX_IPSR_GPSR(IP0SR1_3_0, A0), 795 796 PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0), 797 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0), 798 PINMUX_IPSR_GPSR(IP0SR1_7_4, A1), 799 800 PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0), 801 PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0), 802 PINMUX_IPSR_GPSR(IP0SR1_11_8, A2), 803 804 PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N), 805 PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N), 806 PINMUX_IPSR_GPSR(IP0SR1_15_12, A3), 807 808 PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N), 809 PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N), 810 PINMUX_IPSR_GPSR(IP0SR1_19_16, A4), 811 812 PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0), 813 PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0), 814 PINMUX_IPSR_GPSR(IP0SR1_23_20, A5), 815 816 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD), 817 PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2), 818 PINMUX_IPSR_GPSR(IP0SR1_27_24, A6), 819 820 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD), 821 PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3), 822 PINMUX_IPSR_GPSR(IP0SR1_31_28, A7), 823 824 /* IP1SR1 */ 825 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK), 826 PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4), 827 PINMUX_IPSR_GPSR(IP1SR1_3_0, A8), 828 829 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC), 830 PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5), 831 PINMUX_IPSR_GPSR(IP1SR1_7_4, A9), 832 833 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1), 834 PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6), 835 PINMUX_IPSR_GPSR(IP1SR1_11_8, A10), 836 837 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2), 838 PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7), 839 PINMUX_IPSR_GPSR(IP1SR1_15_12, A11), 840 841 PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD), 842 PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2), 843 PINMUX_IPSR_GPSR(IP1SR1_19_16, A12), 844 845 PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD), 846 PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3), 847 PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3), 848 PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3), 849 PINMUX_IPSR_GPSR(IP1SR1_23_20, A13), 850 851 PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK), 852 PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3), 853 PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N), 854 PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4), 855 PINMUX_IPSR_GPSR(IP1SR1_27_24, A14), 856 857 PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC), 858 PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N), 859 PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N), 860 PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5), 861 PINMUX_IPSR_GPSR(IP1SR1_31_28, A15), 862 863 /* IP2SR1 */ 864 PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1), 865 PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N), 866 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3), 867 PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6), 868 PINMUX_IPSR_GPSR(IP2SR1_3_0, A16), 869 870 PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2), 871 PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3), 872 PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3), 873 PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7), 874 PINMUX_IPSR_GPSR(IP2SR1_7_4, A17), 875 876 PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD), 877 PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1), 878 PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1), 879 PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2), 880 PINMUX_IPSR_GPSR(IP2SR1_11_8, A18), 881 882 PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD), 883 PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N), 884 PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N), 885 PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3), 886 PINMUX_IPSR_GPSR(IP2SR1_15_12, A19), 887 888 PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK), 889 PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N), 890 PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N), 891 PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4), 892 PINMUX_IPSR_GPSR(IP2SR1_19_16, A20), 893 894 PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC), 895 PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1), 896 PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A), 897 PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5), 898 PINMUX_IPSR_GPSR(IP2SR1_23_20, A21), 899 900 PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1), 901 PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1), 902 PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A), 903 PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6), 904 PINMUX_IPSR_GPSR(IP2SR1_27_24, A22), 905 906 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2), 907 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B), 908 PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7), 909 PINMUX_IPSR_GPSR(IP2SR1_31_28, A23), 910 911 /* IP3SR1 */ 912 PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0), 913 PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT), 914 PINMUX_IPSR_GPSR(IP3SR1_3_0, A24), 915 916 PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1), 917 PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC), 918 PINMUX_IPSR_GPSR(IP3SR1_7_4, A25), 919 920 PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2), 921 PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC), 922 PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26), 923 924 PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3), 925 PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE), 926 PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N), 927 928 PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28), 929 PINMUX_IPSR_GPSR(IP3SR1_19_16, D0), 930 931 PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29), 932 PINMUX_IPSR_GPSR(IP3SR1_23_20, D1), 933 934 PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30), 935 PINMUX_IPSR_GPSR(IP3SR1_27_24, D2), 936 937 /* IP0SR2 */ 938 PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN), 939 PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN), 940 PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN), 941 942 PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT), 943 PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT), 944 945 /* GP2_02 = SCL0 */ 946 PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0), 947 PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0), 948 PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3), 949 950 /* GP2_03 = SDA0 */ 951 PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0), 952 PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0), 953 PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3), 954 955 /* GP2_04 = SCL1 */ 956 PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0), 957 PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0), 958 PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0), 959 PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3), 960 961 /* GP2_05 = SDA1 */ 962 PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0), 963 PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0), 964 PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0), 965 PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0), 966 PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0), 967 PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3), 968 969 /* GP2_06 = SCL2 */ 970 PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0), 971 PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0), 972 PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0), 973 PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0), 974 PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0), 975 PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3), 976 977 /* GP2_07 = SDA2 */ 978 PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0), 979 PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0), 980 PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0), 981 PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0), 982 PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0), 983 PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3), 984 985 /* GP2_08 = SCL3 */ 986 PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0), 987 PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0), 988 PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0), 989 PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0), 990 PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0), 991 PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3), 992 993 /* GP2_09 = SDA3 */ 994 PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0), 995 PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0), 996 PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0), 997 PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0), 998 PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0), 999 PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3), 1000 1001 /* GP2_10 = SCL4 */ 1002 PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0), 1003 PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0), 1004 PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0), 1005 PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0), 1006 PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3), 1007 1008 /* GP2_11 = SDA4 */ 1009 PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0), 1010 PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0), 1011 PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0), 1012 PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0), 1013 PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3), 1014 1015 /* GP2_12 = SCL5 */ 1016 PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0), 1017 PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0), 1018 PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0), 1019 PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0), 1020 PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3), 1021 1022 /* GP2_13 = SDA5 */ 1023 PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0), 1024 PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0), 1025 PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0), 1026 PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3), 1027 1028 /* GP2_14 = SCL6 */ 1029 PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0), 1030 PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0), 1031 PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0), 1032 PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0), 1033 PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3), 1034 1035 /* GP2_15 = SDA6 */ 1036 PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0), 1037 PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0), 1038 PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0), 1039 PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0), 1040 PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3), 1041 1042 /* IP2SR2 */ 1043 PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A), 1044 PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1), 1045 1046 PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A), 1047 PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2), 1048 PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N), 1049 1050 PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB), 1051 PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD), 1052 PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N), 1053 1054 PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR), 1055 PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD), 1056 PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N), 1057 1058 PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR), 1059 PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK), 1060 PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N), 1061 1062 PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0), 1063 PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC), 1064 PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N), 1065 1066 PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1), 1067 PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT), 1068 1069 PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A), 1070 PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0), 1071 1072 /* IP0SR3 */ 1073 PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX), 1074 PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B), 1075 PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B), 1076 1077 PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX), 1078 PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B), 1079 PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B), 1080 1081 PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX), 1082 PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2), 1083 PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0), 1084 1085 PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX), 1086 PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3), 1087 PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1), 1088 1089 PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX), 1090 PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2), 1091 1092 /* IP1SR3 */ 1093 PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX), 1094 PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3), 1095 1096 PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX), 1097 PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4), 1098 PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1), 1099 1100 PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX), 1101 PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2), 1102 1103 PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX), 1104 PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N), 1105 1106 PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX), 1107 PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N), 1108 1109 PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX), 1110 PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR), 1111 1112 /* IP0SR4 */ 1113 PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL), 1114 PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV), 1115 1116 PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC), 1117 PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC), 1118 1119 PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0), 1120 PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0), 1121 1122 PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1), 1123 PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1), 1124 1125 PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2), 1126 PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2), 1127 1128 PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3), 1129 PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3), 1130 1131 PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL), 1132 PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN), 1133 1134 PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC), 1135 PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC), 1136 1137 /* IP1SR4 */ 1138 PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0), 1139 PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0), 1140 1141 PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1), 1142 PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1), 1143 1144 PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2), 1145 PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2), 1146 1147 PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3), 1148 PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3), 1149 1150 PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK), 1151 1152 PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO), 1153 1154 PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC), 1155 1156 PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC), 1157 1158 /* IP2SR4 */ 1159 PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK), 1160 PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER), 1161 1162 PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH), 1163 PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER), 1164 PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT), 1165 1166 PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE), 1167 PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS), 1168 1169 PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS), 1170 PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL), 1171 1172 /* IP0SR5 */ 1173 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL), 1174 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV), 1175 1176 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC), 1177 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC), 1178 1179 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0), 1180 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0), 1181 1182 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1), 1183 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1), 1184 1185 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2), 1186 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2), 1187 1188 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3), 1189 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3), 1190 1191 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL), 1192 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN), 1193 1194 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC), 1195 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC), 1196 1197 /* IP1SR5 */ 1198 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0), 1199 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0), 1200 1201 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1), 1202 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1), 1203 1204 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2), 1205 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2), 1206 1207 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3), 1208 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3), 1209 1210 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK), 1211 1212 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO), 1213 1214 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC), 1215 1216 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC), 1217 1218 /* IP2SR5 */ 1219 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK), 1220 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER), 1221 1222 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH), 1223 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER), 1224 1225 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE), 1226 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS), 1227 1228 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS), 1229 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL), 1230}; 1231 1232/* 1233 * Pins not associated with a GPIO port. 1234 */ 1235enum { 1236 GP_ASSIGN_LAST(), 1237 NOGP_ALL(), 1238}; 1239 1240static const struct sh_pfc_pin pinmux_pins[] = { 1241 PINMUX_GPIO_GP_ALL(), 1242}; 1243 1244/* - AVB0 ------------------------------------------------ */ 1245static const unsigned int avb0_link_pins[] = { 1246 /* AVB0_LINK */ 1247 RCAR_GP_PIN(4, 17), 1248}; 1249static const unsigned int avb0_link_mux[] = { 1250 AVB0_LINK_MARK, 1251}; 1252static const unsigned int avb0_magic_pins[] = { 1253 /* AVB0_MAGIC */ 1254 RCAR_GP_PIN(4, 15), 1255}; 1256static const unsigned int avb0_magic_mux[] = { 1257 AVB0_MAGIC_MARK, 1258}; 1259static const unsigned int avb0_phy_int_pins[] = { 1260 /* AVB0_PHY_INT */ 1261 RCAR_GP_PIN(4, 16), 1262}; 1263static const unsigned int avb0_phy_int_mux[] = { 1264 AVB0_PHY_INT_MARK, 1265}; 1266static const unsigned int avb0_mdio_pins[] = { 1267 /* AVB0_MDC, AVB0_MDIO */ 1268 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), 1269}; 1270static const unsigned int avb0_mdio_mux[] = { 1271 AVB0_MDC_MARK, AVB0_MDIO_MARK, 1272}; 1273static const unsigned int avb0_rgmii_pins[] = { 1274 /* 1275 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, 1276 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, 1277 */ 1278 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 1279 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1280 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1281 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 1282 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 1283 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1284}; 1285static const unsigned int avb0_rgmii_mux[] = { 1286 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, 1287 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, 1288 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, 1289 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, 1290}; 1291static const unsigned int avb0_txcrefclk_pins[] = { 1292 /* AVB0_TXCREFCLK */ 1293 RCAR_GP_PIN(4, 12), 1294}; 1295static const unsigned int avb0_txcrefclk_mux[] = { 1296 AVB0_TXCREFCLK_MARK, 1297}; 1298static const unsigned int avb0_avtp_pps_pins[] = { 1299 /* AVB0_AVTP_PPS */ 1300 RCAR_GP_PIN(4, 20), 1301}; 1302static const unsigned int avb0_avtp_pps_mux[] = { 1303 AVB0_AVTP_PPS_MARK, 1304}; 1305static const unsigned int avb0_avtp_capture_pins[] = { 1306 /* AVB0_AVTP_CAPTURE */ 1307 RCAR_GP_PIN(4, 19), 1308}; 1309static const unsigned int avb0_avtp_capture_mux[] = { 1310 AVB0_AVTP_CAPTURE_MARK, 1311}; 1312static const unsigned int avb0_avtp_match_pins[] = { 1313 /* AVB0_AVTP_MATCH */ 1314 RCAR_GP_PIN(4, 18), 1315}; 1316static const unsigned int avb0_avtp_match_mux[] = { 1317 AVB0_AVTP_MATCH_MARK, 1318}; 1319 1320/* - AVB1 ------------------------------------------------ */ 1321static const unsigned int avb1_link_pins[] = { 1322 /* AVB1_LINK */ 1323 RCAR_GP_PIN(5, 17), 1324}; 1325static const unsigned int avb1_link_mux[] = { 1326 AVB1_LINK_MARK, 1327}; 1328static const unsigned int avb1_magic_pins[] = { 1329 /* AVB1_MAGIC */ 1330 RCAR_GP_PIN(5, 15), 1331}; 1332static const unsigned int avb1_magic_mux[] = { 1333 AVB1_MAGIC_MARK, 1334}; 1335static const unsigned int avb1_phy_int_pins[] = { 1336 /* AVB1_PHY_INT */ 1337 RCAR_GP_PIN(5, 16), 1338}; 1339static const unsigned int avb1_phy_int_mux[] = { 1340 AVB1_PHY_INT_MARK, 1341}; 1342static const unsigned int avb1_mdio_pins[] = { 1343 /* AVB1_MDC, AVB1_MDIO */ 1344 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13), 1345}; 1346static const unsigned int avb1_mdio_mux[] = { 1347 AVB1_MDC_MARK, AVB1_MDIO_MARK, 1348}; 1349static const unsigned int avb1_rgmii_pins[] = { 1350 /* 1351 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, 1352 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, 1353 */ 1354 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), 1355 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 1356 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 1357 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 1358 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3), 1359 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), 1360}; 1361static const unsigned int avb1_rgmii_mux[] = { 1362 AVB1_TX_CTL_MARK, AVB1_TXC_MARK, 1363 AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK, 1364 AVB1_RX_CTL_MARK, AVB1_RXC_MARK, 1365 AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK, 1366}; 1367static const unsigned int avb1_txcrefclk_pins[] = { 1368 /* AVB1_TXCREFCLK */ 1369 RCAR_GP_PIN(5, 12), 1370}; 1371static const unsigned int avb1_txcrefclk_mux[] = { 1372 AVB1_TXCREFCLK_MARK, 1373}; 1374static const unsigned int avb1_avtp_pps_pins[] = { 1375 /* AVB1_AVTP_PPS */ 1376 RCAR_GP_PIN(5, 20), 1377}; 1378static const unsigned int avb1_avtp_pps_mux[] = { 1379 AVB1_AVTP_PPS_MARK, 1380}; 1381static const unsigned int avb1_avtp_capture_pins[] = { 1382 /* AVB1_AVTP_CAPTURE */ 1383 RCAR_GP_PIN(5, 19), 1384}; 1385static const unsigned int avb1_avtp_capture_mux[] = { 1386 AVB1_AVTP_CAPTURE_MARK, 1387}; 1388static const unsigned int avb1_avtp_match_pins[] = { 1389 /* AVB1_AVTP_MATCH */ 1390 RCAR_GP_PIN(5, 18), 1391}; 1392static const unsigned int avb1_avtp_match_mux[] = { 1393 AVB1_AVTP_MATCH_MARK, 1394}; 1395 1396/* - AVB2 ------------------------------------------------ */ 1397static const unsigned int avb2_link_pins[] = { 1398 /* AVB2_LINK */ 1399 RCAR_GP_PIN(6, 17), 1400}; 1401static const unsigned int avb2_link_mux[] = { 1402 AVB2_LINK_MARK, 1403}; 1404static const unsigned int avb2_magic_pins[] = { 1405 /* AVB2_MAGIC */ 1406 RCAR_GP_PIN(6, 15), 1407}; 1408static const unsigned int avb2_magic_mux[] = { 1409 AVB2_MAGIC_MARK, 1410}; 1411static const unsigned int avb2_phy_int_pins[] = { 1412 /* AVB2_PHY_INT */ 1413 RCAR_GP_PIN(6, 16), 1414}; 1415static const unsigned int avb2_phy_int_mux[] = { 1416 AVB2_PHY_INT_MARK, 1417}; 1418static const unsigned int avb2_mdio_pins[] = { 1419 /* AVB2_MDC, AVB2_MDIO */ 1420 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13), 1421}; 1422static const unsigned int avb2_mdio_mux[] = { 1423 AVB2_MDC_MARK, AVB2_MDIO_MARK, 1424}; 1425static const unsigned int avb2_rgmii_pins[] = { 1426 /* 1427 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, 1428 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, 1429 */ 1430 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), 1431 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1432 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), 1433 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 1434 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), 1435 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), 1436}; 1437static const unsigned int avb2_rgmii_mux[] = { 1438 AVB2_TX_CTL_MARK, AVB2_TXC_MARK, 1439 AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK, 1440 AVB2_RX_CTL_MARK, AVB2_RXC_MARK, 1441 AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK, 1442}; 1443static const unsigned int avb2_txcrefclk_pins[] = { 1444 /* AVB2_TXCREFCLK */ 1445 RCAR_GP_PIN(6, 12), 1446}; 1447static const unsigned int avb2_txcrefclk_mux[] = { 1448 AVB2_TXCREFCLK_MARK, 1449}; 1450static const unsigned int avb2_avtp_pps_pins[] = { 1451 /* AVB2_AVTP_PPS */ 1452 RCAR_GP_PIN(6, 20), 1453}; 1454static const unsigned int avb2_avtp_pps_mux[] = { 1455 AVB2_AVTP_PPS_MARK, 1456}; 1457static const unsigned int avb2_avtp_capture_pins[] = { 1458 /* AVB2_AVTP_CAPTURE */ 1459 RCAR_GP_PIN(6, 19), 1460}; 1461static const unsigned int avb2_avtp_capture_mux[] = { 1462 AVB2_AVTP_CAPTURE_MARK, 1463}; 1464static const unsigned int avb2_avtp_match_pins[] = { 1465 /* AVB2_AVTP_MATCH */ 1466 RCAR_GP_PIN(6, 18), 1467}; 1468static const unsigned int avb2_avtp_match_mux[] = { 1469 AVB2_AVTP_MATCH_MARK, 1470}; 1471 1472/* - AVB3 ------------------------------------------------ */ 1473static const unsigned int avb3_link_pins[] = { 1474 /* AVB3_LINK */ 1475 RCAR_GP_PIN(7, 17), 1476}; 1477static const unsigned int avb3_link_mux[] = { 1478 AVB3_LINK_MARK, 1479}; 1480static const unsigned int avb3_magic_pins[] = { 1481 /* AVB3_MAGIC */ 1482 RCAR_GP_PIN(7, 15), 1483}; 1484static const unsigned int avb3_magic_mux[] = { 1485 AVB3_MAGIC_MARK, 1486}; 1487static const unsigned int avb3_phy_int_pins[] = { 1488 /* AVB3_PHY_INT */ 1489 RCAR_GP_PIN(7, 16), 1490}; 1491static const unsigned int avb3_phy_int_mux[] = { 1492 AVB3_PHY_INT_MARK, 1493}; 1494static const unsigned int avb3_mdio_pins[] = { 1495 /* AVB3_MDC, AVB3_MDIO */ 1496 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13), 1497}; 1498static const unsigned int avb3_mdio_mux[] = { 1499 AVB3_MDC_MARK, AVB3_MDIO_MARK, 1500}; 1501static const unsigned int avb3_rgmii_pins[] = { 1502 /* 1503 * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3, 1504 * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3, 1505 */ 1506 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), 1507 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), 1508 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), 1509 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1), 1510 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3), 1511 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), 1512}; 1513static const unsigned int avb3_rgmii_mux[] = { 1514 AVB3_TX_CTL_MARK, AVB3_TXC_MARK, 1515 AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK, 1516 AVB3_RX_CTL_MARK, AVB3_RXC_MARK, 1517 AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK, 1518}; 1519static const unsigned int avb3_txcrefclk_pins[] = { 1520 /* AVB3_TXCREFCLK */ 1521 RCAR_GP_PIN(7, 12), 1522}; 1523static const unsigned int avb3_txcrefclk_mux[] = { 1524 AVB3_TXCREFCLK_MARK, 1525}; 1526static const unsigned int avb3_avtp_pps_pins[] = { 1527 /* AVB3_AVTP_PPS */ 1528 RCAR_GP_PIN(7, 20), 1529}; 1530static const unsigned int avb3_avtp_pps_mux[] = { 1531 AVB3_AVTP_PPS_MARK, 1532}; 1533static const unsigned int avb3_avtp_capture_pins[] = { 1534 /* AVB3_AVTP_CAPTURE */ 1535 RCAR_GP_PIN(7, 19), 1536}; 1537static const unsigned int avb3_avtp_capture_mux[] = { 1538 AVB3_AVTP_CAPTURE_MARK, 1539}; 1540static const unsigned int avb3_avtp_match_pins[] = { 1541 /* AVB3_AVTP_MATCH */ 1542 RCAR_GP_PIN(7, 18), 1543}; 1544static const unsigned int avb3_avtp_match_mux[] = { 1545 AVB3_AVTP_MATCH_MARK, 1546}; 1547 1548/* - AVB4 ------------------------------------------------ */ 1549static const unsigned int avb4_link_pins[] = { 1550 /* AVB4_LINK */ 1551 RCAR_GP_PIN(8, 17), 1552}; 1553static const unsigned int avb4_link_mux[] = { 1554 AVB4_LINK_MARK, 1555}; 1556static const unsigned int avb4_magic_pins[] = { 1557 /* AVB4_MAGIC */ 1558 RCAR_GP_PIN(8, 15), 1559}; 1560static const unsigned int avb4_magic_mux[] = { 1561 AVB4_MAGIC_MARK, 1562}; 1563static const unsigned int avb4_phy_int_pins[] = { 1564 /* AVB4_PHY_INT */ 1565 RCAR_GP_PIN(8, 16), 1566}; 1567static const unsigned int avb4_phy_int_mux[] = { 1568 AVB4_PHY_INT_MARK, 1569}; 1570static const unsigned int avb4_mdio_pins[] = { 1571 /* AVB4_MDC, AVB4_MDIO */ 1572 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13), 1573}; 1574static const unsigned int avb4_mdio_mux[] = { 1575 AVB4_MDC_MARK, AVB4_MDIO_MARK, 1576}; 1577static const unsigned int avb4_rgmii_pins[] = { 1578 /* 1579 * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3, 1580 * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3, 1581 */ 1582 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), 1583 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), 1584 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), 1585 RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1), 1586 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3), 1587 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), 1588}; 1589static const unsigned int avb4_rgmii_mux[] = { 1590 AVB4_TX_CTL_MARK, AVB4_TXC_MARK, 1591 AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK, 1592 AVB4_RX_CTL_MARK, AVB4_RXC_MARK, 1593 AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK, 1594}; 1595static const unsigned int avb4_txcrefclk_pins[] = { 1596 /* AVB4_TXCREFCLK */ 1597 RCAR_GP_PIN(8, 12), 1598}; 1599static const unsigned int avb4_txcrefclk_mux[] = { 1600 AVB4_TXCREFCLK_MARK, 1601}; 1602static const unsigned int avb4_avtp_pps_pins[] = { 1603 /* AVB4_AVTP_PPS */ 1604 RCAR_GP_PIN(8, 20), 1605}; 1606static const unsigned int avb4_avtp_pps_mux[] = { 1607 AVB4_AVTP_PPS_MARK, 1608}; 1609static const unsigned int avb4_avtp_capture_pins[] = { 1610 /* AVB4_AVTP_CAPTURE */ 1611 RCAR_GP_PIN(8, 19), 1612}; 1613static const unsigned int avb4_avtp_capture_mux[] = { 1614 AVB4_AVTP_CAPTURE_MARK, 1615}; 1616static const unsigned int avb4_avtp_match_pins[] = { 1617 /* AVB4_AVTP_MATCH */ 1618 RCAR_GP_PIN(8, 18), 1619}; 1620static const unsigned int avb4_avtp_match_mux[] = { 1621 AVB4_AVTP_MATCH_MARK, 1622}; 1623 1624/* - AVB5 ------------------------------------------------ */ 1625static const unsigned int avb5_link_pins[] = { 1626 /* AVB5_LINK */ 1627 RCAR_GP_PIN(9, 17), 1628}; 1629static const unsigned int avb5_link_mux[] = { 1630 AVB5_LINK_MARK, 1631}; 1632static const unsigned int avb5_magic_pins[] = { 1633 /* AVB5_MAGIC */ 1634 RCAR_GP_PIN(9, 15), 1635}; 1636static const unsigned int avb5_magic_mux[] = { 1637 AVB5_MAGIC_MARK, 1638}; 1639static const unsigned int avb5_phy_int_pins[] = { 1640 /* AVB5_PHY_INT */ 1641 RCAR_GP_PIN(9, 16), 1642}; 1643static const unsigned int avb5_phy_int_mux[] = { 1644 AVB5_PHY_INT_MARK, 1645}; 1646static const unsigned int avb5_mdio_pins[] = { 1647 /* AVB5_MDC, AVB5_MDIO */ 1648 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13), 1649}; 1650static const unsigned int avb5_mdio_mux[] = { 1651 AVB5_MDC_MARK, AVB5_MDIO_MARK, 1652}; 1653static const unsigned int avb5_rgmii_pins[] = { 1654 /* 1655 * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3, 1656 * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3, 1657 */ 1658 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), 1659 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), 1660 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), 1661 RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1), 1662 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3), 1663 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), 1664}; 1665static const unsigned int avb5_rgmii_mux[] = { 1666 AVB5_TX_CTL_MARK, AVB5_TXC_MARK, 1667 AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK, 1668 AVB5_RX_CTL_MARK, AVB5_RXC_MARK, 1669 AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK, 1670}; 1671static const unsigned int avb5_txcrefclk_pins[] = { 1672 /* AVB5_TXCREFCLK */ 1673 RCAR_GP_PIN(9, 12), 1674}; 1675static const unsigned int avb5_txcrefclk_mux[] = { 1676 AVB5_TXCREFCLK_MARK, 1677}; 1678static const unsigned int avb5_avtp_pps_pins[] = { 1679 /* AVB5_AVTP_PPS */ 1680 RCAR_GP_PIN(9, 20), 1681}; 1682static const unsigned int avb5_avtp_pps_mux[] = { 1683 AVB5_AVTP_PPS_MARK, 1684}; 1685static const unsigned int avb5_avtp_capture_pins[] = { 1686 /* AVB5_AVTP_CAPTURE */ 1687 RCAR_GP_PIN(9, 19), 1688}; 1689static const unsigned int avb5_avtp_capture_mux[] = { 1690 AVB5_AVTP_CAPTURE_MARK, 1691}; 1692static const unsigned int avb5_avtp_match_pins[] = { 1693 /* AVB5_AVTP_MATCH */ 1694 RCAR_GP_PIN(9, 18), 1695}; 1696static const unsigned int avb5_avtp_match_mux[] = { 1697 AVB5_AVTP_MATCH_MARK, 1698}; 1699 1700/* - CANFD0 ----------------------------------------------------------------- */ 1701static const unsigned int canfd0_data_pins[] = { 1702 /* CANFD0_TX, CANFD0_RX */ 1703 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), 1704}; 1705static const unsigned int canfd0_data_mux[] = { 1706 CANFD0_TX_MARK, CANFD0_RX_MARK, 1707}; 1708 1709/* - CANFD1 ----------------------------------------------------------------- */ 1710static const unsigned int canfd1_data_pins[] = { 1711 /* CANFD1_TX, CANFD1_RX */ 1712 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), 1713}; 1714static const unsigned int canfd1_data_mux[] = { 1715 CANFD1_TX_MARK, CANFD1_RX_MARK, 1716}; 1717 1718/* - CANFD2 ----------------------------------------------------------------- */ 1719static const unsigned int canfd2_data_pins[] = { 1720 /* CANFD2_TX, CANFD2_RX */ 1721 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), 1722}; 1723static const unsigned int canfd2_data_mux[] = { 1724 CANFD2_TX_MARK, CANFD2_RX_MARK, 1725}; 1726 1727/* - CANFD3 ----------------------------------------------------------------- */ 1728static const unsigned int canfd3_data_pins[] = { 1729 /* CANFD3_TX, CANFD3_RX */ 1730 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), 1731}; 1732static const unsigned int canfd3_data_mux[] = { 1733 CANFD3_TX_MARK, CANFD3_RX_MARK, 1734}; 1735 1736/* - CANFD4 ----------------------------------------------------------------- */ 1737static const unsigned int canfd4_data_pins[] = { 1738 /* CANFD4_TX, CANFD4_RX */ 1739 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 1740}; 1741static const unsigned int canfd4_data_mux[] = { 1742 CANFD4_TX_MARK, CANFD4_RX_MARK, 1743}; 1744 1745/* - CANFD5 ----------------------------------------------------------------- */ 1746static const unsigned int canfd5_data_pins[] = { 1747 /* CANFD5_TX, CANFD5_RX */ 1748 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 1749}; 1750static const unsigned int canfd5_data_mux[] = { 1751 CANFD5_TX_MARK, CANFD5_RX_MARK, 1752}; 1753 1754/* - CANFD6 ----------------------------------------------------------------- */ 1755static const unsigned int canfd6_data_pins[] = { 1756 /* CANFD6_TX, CANFD6_RX */ 1757 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 1758}; 1759static const unsigned int canfd6_data_mux[] = { 1760 CANFD6_TX_MARK, CANFD6_RX_MARK, 1761}; 1762 1763/* - CANFD7 ----------------------------------------------------------------- */ 1764static const unsigned int canfd7_data_pins[] = { 1765 /* CANFD7_TX, CANFD7_RX */ 1766 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), 1767}; 1768static const unsigned int canfd7_data_mux[] = { 1769 CANFD7_TX_MARK, CANFD7_RX_MARK, 1770}; 1771 1772/* - CANFD Clock ------------------------------------------------------------ */ 1773static const unsigned int can_clk_pins[] = { 1774 /* CAN_CLK */ 1775 RCAR_GP_PIN(3, 0), 1776}; 1777static const unsigned int can_clk_mux[] = { 1778 CAN_CLK_MARK, 1779}; 1780 1781/* - DU --------------------------------------------------------------------- */ 1782static const unsigned int du_rgb888_pins[] = { 1783 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ 1784 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 1785 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 1786 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), 1787 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), 1788 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1789 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1790}; 1791static const unsigned int du_rgb888_mux[] = { 1792 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, 1793 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, 1794 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, 1795 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, 1796 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, 1797 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, 1798}; 1799static const unsigned int du_clk_out_pins[] = { 1800 /* DU_DOTCLKOUT */ 1801 RCAR_GP_PIN(1, 24), 1802}; 1803static const unsigned int du_clk_out_mux[] = { 1804 DU_DOTCLKOUT_MARK, 1805}; 1806static const unsigned int du_sync_pins[] = { 1807 /* DU_HSYNC, DU_VSYNC */ 1808 RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26), 1809}; 1810static const unsigned int du_sync_mux[] = { 1811 DU_HSYNC_MARK, DU_VSYNC_MARK, 1812}; 1813static const unsigned int du_oddf_pins[] = { 1814 /* DU_EXODDF/DU_ODDF/DISP/CDE */ 1815 RCAR_GP_PIN(1, 27), 1816}; 1817static const unsigned int du_oddf_mux[] = { 1818 DU_ODDF_DISP_CDE_MARK, 1819}; 1820 1821/* - HSCIF0 ----------------------------------------------------------------- */ 1822static const unsigned int hscif0_data_pins[] = { 1823 /* HRX0, HTX0 */ 1824 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), 1825}; 1826static const unsigned int hscif0_data_mux[] = { 1827 HRX0_MARK, HTX0_MARK, 1828}; 1829static const unsigned int hscif0_clk_pins[] = { 1830 /* HSCK0 */ 1831 RCAR_GP_PIN(1, 2), 1832}; 1833static const unsigned int hscif0_clk_mux[] = { 1834 HSCK0_MARK, 1835}; 1836static const unsigned int hscif0_ctrl_pins[] = { 1837 /* HRTS0#, HCTS0# */ 1838 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), 1839}; 1840static const unsigned int hscif0_ctrl_mux[] = { 1841 HRTS0_N_MARK, HCTS0_N_MARK, 1842}; 1843 1844/* - HSCIF1 ----------------------------------------------------------------- */ 1845static const unsigned int hscif1_data_pins[] = { 1846 /* HRX1, HTX1 */ 1847 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 1848}; 1849static const unsigned int hscif1_data_mux[] = { 1850 HRX1_MARK, HTX1_MARK, 1851}; 1852static const unsigned int hscif1_clk_pins[] = { 1853 /* HSCK1 */ 1854 RCAR_GP_PIN(1, 18), 1855}; 1856static const unsigned int hscif1_clk_mux[] = { 1857 HSCK1_MARK, 1858}; 1859static const unsigned int hscif1_ctrl_pins[] = { 1860 /* HRTS1#, HCTS1# */ 1861 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), 1862}; 1863static const unsigned int hscif1_ctrl_mux[] = { 1864 HRTS1_N_MARK, HCTS1_N_MARK, 1865}; 1866 1867/* - HSCIF2 ----------------------------------------------------------------- */ 1868static const unsigned int hscif2_data_pins[] = { 1869 /* HRX2, HTX2 */ 1870 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1871}; 1872static const unsigned int hscif2_data_mux[] = { 1873 HRX2_MARK, HTX2_MARK, 1874}; 1875static const unsigned int hscif2_clk_pins[] = { 1876 /* HSCK2 */ 1877 RCAR_GP_PIN(2, 5), 1878}; 1879static const unsigned int hscif2_clk_mux[] = { 1880 HSCK2_MARK, 1881}; 1882static const unsigned int hscif2_ctrl_pins[] = { 1883 /* HRTS2#, HCTS2# */ 1884 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), 1885}; 1886static const unsigned int hscif2_ctrl_mux[] = { 1887 HRTS2_N_MARK, HCTS2_N_MARK, 1888}; 1889 1890/* - HSCIF3 ----------------------------------------------------------------- */ 1891static const unsigned int hscif3_data_pins[] = { 1892 /* HRX3, HTX3 */ 1893 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17), 1894}; 1895static const unsigned int hscif3_data_mux[] = { 1896 HRX3_MARK, HTX3_MARK, 1897}; 1898static const unsigned int hscif3_clk_pins[] = { 1899 /* HSCK3 */ 1900 RCAR_GP_PIN(1, 14), 1901}; 1902static const unsigned int hscif3_clk_mux[] = { 1903 HSCK3_MARK, 1904}; 1905static const unsigned int hscif3_ctrl_pins[] = { 1906 /* HRTS3#, HCTS3# */ 1907 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 1908}; 1909static const unsigned int hscif3_ctrl_mux[] = { 1910 HRTS3_N_MARK, HCTS3_N_MARK, 1911}; 1912 1913/* - I2C0 ------------------------------------------------------------------- */ 1914static const unsigned int i2c0_pins[] = { 1915 /* SDA0, SCL0 */ 1916 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), 1917}; 1918static const unsigned int i2c0_mux[] = { 1919 SDA0_MARK, SCL0_MARK, 1920}; 1921 1922/* - I2C1 ------------------------------------------------------------------- */ 1923static const unsigned int i2c1_pins[] = { 1924 /* SDA1, SCL1 */ 1925 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 1926}; 1927static const unsigned int i2c1_mux[] = { 1928 SDA1_MARK, SCL1_MARK, 1929}; 1930 1931/* - I2C2 ------------------------------------------------------------------- */ 1932static const unsigned int i2c2_pins[] = { 1933 /* SDA2, SCL2 */ 1934 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), 1935}; 1936static const unsigned int i2c2_mux[] = { 1937 SDA2_MARK, SCL2_MARK, 1938}; 1939 1940/* - I2C3 ------------------------------------------------------------------- */ 1941static const unsigned int i2c3_pins[] = { 1942 /* SDA3, SCL3 */ 1943 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), 1944}; 1945static const unsigned int i2c3_mux[] = { 1946 SDA3_MARK, SCL3_MARK, 1947}; 1948 1949/* - I2C4 ------------------------------------------------------------------- */ 1950static const unsigned int i2c4_pins[] = { 1951 /* SDA4, SCL4 */ 1952 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1953}; 1954static const unsigned int i2c4_mux[] = { 1955 SDA4_MARK, SCL4_MARK, 1956}; 1957 1958/* - I2C5 ------------------------------------------------------------------- */ 1959static const unsigned int i2c5_pins[] = { 1960 /* SDA5, SCL5 */ 1961 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), 1962}; 1963static const unsigned int i2c5_mux[] = { 1964 SDA5_MARK, SCL5_MARK, 1965}; 1966 1967/* - I2C6 ------------------------------------------------------------------- */ 1968static const unsigned int i2c6_pins[] = { 1969 /* SDA6, SCL6 */ 1970 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), 1971}; 1972static const unsigned int i2c6_mux[] = { 1973 SDA6_MARK, SCL6_MARK, 1974}; 1975 1976/* - INTC-EX ---------------------------------------------------------------- */ 1977static const unsigned int intc_ex_irq0_pins[] = { 1978 /* IRQ0 */ 1979 RCAR_GP_PIN(1, 24), 1980}; 1981static const unsigned int intc_ex_irq0_mux[] = { 1982 IRQ0_MARK, 1983}; 1984static const unsigned int intc_ex_irq1_pins[] = { 1985 /* IRQ1 */ 1986 RCAR_GP_PIN(1, 25), 1987}; 1988static const unsigned int intc_ex_irq1_mux[] = { 1989 IRQ1_MARK, 1990}; 1991static const unsigned int intc_ex_irq2_pins[] = { 1992 /* IRQ2 */ 1993 RCAR_GP_PIN(1, 26), 1994}; 1995static const unsigned int intc_ex_irq2_mux[] = { 1996 IRQ2_MARK, 1997}; 1998static const unsigned int intc_ex_irq3_pins[] = { 1999 /* IRQ3 */ 2000 RCAR_GP_PIN(1, 27), 2001}; 2002static const unsigned int intc_ex_irq3_mux[] = { 2003 IRQ3_MARK, 2004}; 2005static const unsigned int intc_ex_irq4_pins[] = { 2006 /* IRQ4 */ 2007 RCAR_GP_PIN(2, 14), 2008}; 2009static const unsigned int intc_ex_irq4_mux[] = { 2010 IRQ4_MARK, 2011}; 2012static const unsigned int intc_ex_irq5_pins[] = { 2013 /* IRQ5 */ 2014 RCAR_GP_PIN(2, 15), 2015}; 2016static const unsigned int intc_ex_irq5_mux[] = { 2017 IRQ5_MARK, 2018}; 2019 2020/* - MMC -------------------------------------------------------------------- */ 2021static const unsigned int mmc_data_pins[] = { 2022 /* MMC_SD_D[0:3], MMC_D[4:7] */ 2023 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), 2024 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), 2025 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2026 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27), 2027}; 2028static const unsigned int mmc_data_mux[] = { 2029 MMC_SD_D0_MARK, MMC_SD_D1_MARK, 2030 MMC_SD_D2_MARK, MMC_SD_D3_MARK, 2031 MMC_D4_MARK, MMC_D5_MARK, 2032 MMC_D6_MARK, MMC_D7_MARK, 2033}; 2034static const unsigned int mmc_ctrl_pins[] = { 2035 /* MMC_SD_CLK, MMC_SD_CMD */ 2036 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18), 2037}; 2038static const unsigned int mmc_ctrl_mux[] = { 2039 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, 2040}; 2041static const unsigned int mmc_cd_pins[] = { 2042 /* SD_CD */ 2043 RCAR_GP_PIN(0, 16), 2044}; 2045static const unsigned int mmc_cd_mux[] = { 2046 SD_CD_MARK, 2047}; 2048static const unsigned int mmc_wp_pins[] = { 2049 /* SD_WP */ 2050 RCAR_GP_PIN(0, 15), 2051}; 2052static const unsigned int mmc_wp_mux[] = { 2053 SD_WP_MARK, 2054}; 2055static const unsigned int mmc_ds_pins[] = { 2056 /* MMC_DS */ 2057 RCAR_GP_PIN(0, 17), 2058}; 2059static const unsigned int mmc_ds_mux[] = { 2060 MMC_DS_MARK, 2061}; 2062 2063/* - MSIOF0 ----------------------------------------------------------------- */ 2064static const unsigned int msiof0_clk_pins[] = { 2065 /* MSIOF0_SCK */ 2066 RCAR_GP_PIN(1, 8), 2067}; 2068static const unsigned int msiof0_clk_mux[] = { 2069 MSIOF0_SCK_MARK, 2070}; 2071static const unsigned int msiof0_sync_pins[] = { 2072 /* MSIOF0_SYNC */ 2073 RCAR_GP_PIN(1, 9), 2074}; 2075static const unsigned int msiof0_sync_mux[] = { 2076 MSIOF0_SYNC_MARK, 2077}; 2078static const unsigned int msiof0_ss1_pins[] = { 2079 /* MSIOF0_SS1 */ 2080 RCAR_GP_PIN(1, 10), 2081}; 2082static const unsigned int msiof0_ss1_mux[] = { 2083 MSIOF0_SS1_MARK, 2084}; 2085static const unsigned int msiof0_ss2_pins[] = { 2086 /* MSIOF0_SS2 */ 2087 RCAR_GP_PIN(1, 11), 2088}; 2089static const unsigned int msiof0_ss2_mux[] = { 2090 MSIOF0_SS2_MARK, 2091}; 2092static const unsigned int msiof0_txd_pins[] = { 2093 /* MSIOF0_TXD */ 2094 RCAR_GP_PIN(1, 7), 2095}; 2096static const unsigned int msiof0_txd_mux[] = { 2097 MSIOF0_TXD_MARK, 2098}; 2099static const unsigned int msiof0_rxd_pins[] = { 2100 /* MSIOF0_RXD */ 2101 RCAR_GP_PIN(1, 6), 2102}; 2103static const unsigned int msiof0_rxd_mux[] = { 2104 MSIOF0_RXD_MARK, 2105}; 2106 2107/* - MSIOF1 ----------------------------------------------------------------- */ 2108static const unsigned int msiof1_clk_pins[] = { 2109 /* MSIOF1_SCK */ 2110 RCAR_GP_PIN(1, 14), 2111}; 2112static const unsigned int msiof1_clk_mux[] = { 2113 MSIOF1_SCK_MARK, 2114}; 2115static const unsigned int msiof1_sync_pins[] = { 2116 /* MSIOF1_SYNC */ 2117 RCAR_GP_PIN(1, 15), 2118}; 2119static const unsigned int msiof1_sync_mux[] = { 2120 MSIOF1_SYNC_MARK, 2121}; 2122static const unsigned int msiof1_ss1_pins[] = { 2123 /* MSIOF1_SS1 */ 2124 RCAR_GP_PIN(1, 16), 2125}; 2126static const unsigned int msiof1_ss1_mux[] = { 2127 MSIOF1_SS1_MARK, 2128}; 2129static const unsigned int msiof1_ss2_pins[] = { 2130 /* MSIOF1_SS2 */ 2131 RCAR_GP_PIN(1, 17), 2132}; 2133static const unsigned int msiof1_ss2_mux[] = { 2134 MSIOF1_SS2_MARK, 2135}; 2136static const unsigned int msiof1_txd_pins[] = { 2137 /* MSIOF1_TXD */ 2138 RCAR_GP_PIN(1, 13), 2139}; 2140static const unsigned int msiof1_txd_mux[] = { 2141 MSIOF1_TXD_MARK, 2142}; 2143static const unsigned int msiof1_rxd_pins[] = { 2144 /* MSIOF1_RXD */ 2145 RCAR_GP_PIN(1, 12), 2146}; 2147static const unsigned int msiof1_rxd_mux[] = { 2148 MSIOF1_RXD_MARK, 2149}; 2150 2151/* - MSIOF2 ----------------------------------------------------------------- */ 2152static const unsigned int msiof2_clk_pins[] = { 2153 /* MSIOF2_SCK */ 2154 RCAR_GP_PIN(1, 20), 2155}; 2156static const unsigned int msiof2_clk_mux[] = { 2157 MSIOF2_SCK_MARK, 2158}; 2159static const unsigned int msiof2_sync_pins[] = { 2160 /* MSIOF2_SYNC */ 2161 RCAR_GP_PIN(1, 21), 2162}; 2163static const unsigned int msiof2_sync_mux[] = { 2164 MSIOF2_SYNC_MARK, 2165}; 2166static const unsigned int msiof2_ss1_pins[] = { 2167 /* MSIOF2_SS1 */ 2168 RCAR_GP_PIN(1, 22), 2169}; 2170static const unsigned int msiof2_ss1_mux[] = { 2171 MSIOF2_SS1_MARK, 2172}; 2173static const unsigned int msiof2_ss2_pins[] = { 2174 /* MSIOF2_SS2 */ 2175 RCAR_GP_PIN(1, 23), 2176}; 2177static const unsigned int msiof2_ss2_mux[] = { 2178 MSIOF2_SS2_MARK, 2179}; 2180static const unsigned int msiof2_txd_pins[] = { 2181 /* MSIOF2_TXD */ 2182 RCAR_GP_PIN(1, 19), 2183}; 2184static const unsigned int msiof2_txd_mux[] = { 2185 MSIOF2_TXD_MARK, 2186}; 2187static const unsigned int msiof2_rxd_pins[] = { 2188 /* MSIOF2_RXD */ 2189 RCAR_GP_PIN(1, 18), 2190}; 2191static const unsigned int msiof2_rxd_mux[] = { 2192 MSIOF2_RXD_MARK, 2193}; 2194 2195/* - MSIOF3 ----------------------------------------------------------------- */ 2196static const unsigned int msiof3_clk_pins[] = { 2197 /* MSIOF3_SCK */ 2198 RCAR_GP_PIN(2, 20), 2199}; 2200static const unsigned int msiof3_clk_mux[] = { 2201 MSIOF3_SCK_MARK, 2202}; 2203static const unsigned int msiof3_sync_pins[] = { 2204 /* MSIOF3_SYNC */ 2205 RCAR_GP_PIN(2, 21), 2206}; 2207static const unsigned int msiof3_sync_mux[] = { 2208 MSIOF3_SYNC_MARK, 2209}; 2210static const unsigned int msiof3_ss1_pins[] = { 2211 /* MSIOF3_SS1 */ 2212 RCAR_GP_PIN(2, 16), 2213}; 2214static const unsigned int msiof3_ss1_mux[] = { 2215 MSIOF3_SS1_MARK, 2216}; 2217static const unsigned int msiof3_ss2_pins[] = { 2218 /* MSIOF3_SS2 */ 2219 RCAR_GP_PIN(2, 17), 2220}; 2221static const unsigned int msiof3_ss2_mux[] = { 2222 MSIOF3_SS2_MARK, 2223}; 2224static const unsigned int msiof3_txd_pins[] = { 2225 /* MSIOF3_TXD */ 2226 RCAR_GP_PIN(2, 19), 2227}; 2228static const unsigned int msiof3_txd_mux[] = { 2229 MSIOF3_TXD_MARK, 2230}; 2231static const unsigned int msiof3_rxd_pins[] = { 2232 /* MSIOF3_RXD */ 2233 RCAR_GP_PIN(2, 18), 2234}; 2235static const unsigned int msiof3_rxd_mux[] = { 2236 MSIOF3_RXD_MARK, 2237}; 2238 2239/* - MSIOF4 ----------------------------------------------------------------- */ 2240static const unsigned int msiof4_clk_pins[] = { 2241 /* MSIOF4_SCK */ 2242 RCAR_GP_PIN(2, 6), 2243}; 2244static const unsigned int msiof4_clk_mux[] = { 2245 MSIOF4_SCK_MARK, 2246}; 2247static const unsigned int msiof4_sync_pins[] = { 2248 /* MSIOF4_SYNC */ 2249 RCAR_GP_PIN(2, 7), 2250}; 2251static const unsigned int msiof4_sync_mux[] = { 2252 MSIOF4_SYNC_MARK, 2253}; 2254static const unsigned int msiof4_ss1_pins[] = { 2255 /* MSIOF4_SS1 */ 2256 RCAR_GP_PIN(2, 8), 2257}; 2258static const unsigned int msiof4_ss1_mux[] = { 2259 MSIOF4_SS1_MARK, 2260}; 2261static const unsigned int msiof4_ss2_pins[] = { 2262 /* MSIOF4_SS2 */ 2263 RCAR_GP_PIN(2, 9), 2264}; 2265static const unsigned int msiof4_ss2_mux[] = { 2266 MSIOF4_SS2_MARK, 2267}; 2268static const unsigned int msiof4_txd_pins[] = { 2269 /* MSIOF4_TXD */ 2270 RCAR_GP_PIN(2, 5), 2271}; 2272static const unsigned int msiof4_txd_mux[] = { 2273 MSIOF4_TXD_MARK, 2274}; 2275static const unsigned int msiof4_rxd_pins[] = { 2276 /* MSIOF4_RXD */ 2277 RCAR_GP_PIN(2, 4), 2278}; 2279static const unsigned int msiof4_rxd_mux[] = { 2280 MSIOF4_RXD_MARK, 2281}; 2282 2283/* - MSIOF5 ----------------------------------------------------------------- */ 2284static const unsigned int msiof5_clk_pins[] = { 2285 /* MSIOF5_SCK */ 2286 RCAR_GP_PIN(2, 12), 2287}; 2288static const unsigned int msiof5_clk_mux[] = { 2289 MSIOF5_SCK_MARK, 2290}; 2291static const unsigned int msiof5_sync_pins[] = { 2292 /* MSIOF5_SYNC */ 2293 RCAR_GP_PIN(2, 13), 2294}; 2295static const unsigned int msiof5_sync_mux[] = { 2296 MSIOF5_SYNC_MARK, 2297}; 2298static const unsigned int msiof5_ss1_pins[] = { 2299 /* MSIOF5_SS1 */ 2300 RCAR_GP_PIN(2, 14), 2301}; 2302static const unsigned int msiof5_ss1_mux[] = { 2303 MSIOF5_SS1_MARK, 2304}; 2305static const unsigned int msiof5_ss2_pins[] = { 2306 /* MSIOF5_SS2 */ 2307 RCAR_GP_PIN(2, 15), 2308}; 2309static const unsigned int msiof5_ss2_mux[] = { 2310 MSIOF5_SS2_MARK, 2311}; 2312static const unsigned int msiof5_txd_pins[] = { 2313 /* MSIOF5_TXD */ 2314 RCAR_GP_PIN(2, 11), 2315}; 2316static const unsigned int msiof5_txd_mux[] = { 2317 MSIOF5_TXD_MARK, 2318}; 2319static const unsigned int msiof5_rxd_pins[] = { 2320 /* MSIOF5_RXD */ 2321 RCAR_GP_PIN(2, 10), 2322}; 2323static const unsigned int msiof5_rxd_mux[] = { 2324 MSIOF5_RXD_MARK, 2325}; 2326 2327/* - PWM0 ------------------------------------------------------------------- */ 2328static const unsigned int pwm0_pins[] = { 2329 /* PWM0 */ 2330 RCAR_GP_PIN(3, 5), 2331}; 2332static const unsigned int pwm0_mux[] = { 2333 PWM0_MARK, 2334}; 2335 2336/* - PWM1 ------------------------------------------------------------------- */ 2337static const unsigned int pwm1_pins[] = { 2338 /* PWM1 */ 2339 RCAR_GP_PIN(3, 6), 2340}; 2341static const unsigned int pwm1_mux[] = { 2342 PWM1_MARK, 2343}; 2344 2345/* - PWM2 ------------------------------------------------------------------- */ 2346static const unsigned int pwm2_pins[] = { 2347 /* PWM2 */ 2348 RCAR_GP_PIN(3, 7), 2349}; 2350static const unsigned int pwm2_mux[] = { 2351 PWM2_MARK, 2352}; 2353 2354/* - PWM3 ------------------------------------------------------------------- */ 2355static const unsigned int pwm3_pins[] = { 2356 /* PWM3 */ 2357 RCAR_GP_PIN(3, 8), 2358}; 2359static const unsigned int pwm3_mux[] = { 2360 PWM3_MARK, 2361}; 2362 2363/* - PWM4 ------------------------------------------------------------------- */ 2364static const unsigned int pwm4_pins[] = { 2365 /* PWM4 */ 2366 RCAR_GP_PIN(3, 9), 2367}; 2368static const unsigned int pwm4_mux[] = { 2369 PWM4_MARK, 2370}; 2371 2372/* - QSPI0 ------------------------------------------------------------------ */ 2373static const unsigned int qspi0_ctrl_pins[] = { 2374 /* SPCLK, SSL */ 2375 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5), 2376}; 2377static const unsigned int qspi0_ctrl_mux[] = { 2378 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 2379}; 2380static const unsigned int qspi0_data_pins[] = { 2381 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2382 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), 2383 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), 2384}; 2385static const unsigned int qspi0_data_mux[] = { 2386 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2387 QSPI0_IO2_MARK, QSPI0_IO3_MARK 2388}; 2389 2390/* - QSPI1 ------------------------------------------------------------------ */ 2391static const unsigned int qspi1_ctrl_pins[] = { 2392 /* SPCLK, SSL */ 2393 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11), 2394}; 2395static const unsigned int qspi1_ctrl_mux[] = { 2396 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 2397}; 2398static const unsigned int qspi1_data_pins[] = { 2399 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2400 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), 2401 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 2402}; 2403static const unsigned int qspi1_data_mux[] = { 2404 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2405 QSPI1_IO2_MARK, QSPI1_IO3_MARK 2406}; 2407 2408/* - SCIF0 ------------------------------------------------------------------ */ 2409static const unsigned int scif0_data_pins[] = { 2410 /* RX0, TX0 */ 2411 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), 2412}; 2413static const unsigned int scif0_data_mux[] = { 2414 RX0_MARK, TX0_MARK, 2415}; 2416static const unsigned int scif0_clk_pins[] = { 2417 /* SCK0 */ 2418 RCAR_GP_PIN(1, 2), 2419}; 2420static const unsigned int scif0_clk_mux[] = { 2421 SCK0_MARK, 2422}; 2423static const unsigned int scif0_ctrl_pins[] = { 2424 /* RTS0#, CTS0# */ 2425 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), 2426}; 2427static const unsigned int scif0_ctrl_mux[] = { 2428 RTS0_N_MARK, CTS0_N_MARK, 2429}; 2430 2431/* - SCIF1 ------------------------------------------------------------------ */ 2432static const unsigned int scif1_data_a_pins[] = { 2433 /* RX, TX */ 2434 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 2435}; 2436static const unsigned int scif1_data_a_mux[] = { 2437 RX1_A_MARK, TX1_A_MARK, 2438}; 2439static const unsigned int scif1_data_b_pins[] = { 2440 /* RX, TX */ 2441 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1), 2442}; 2443static const unsigned int scif1_data_b_mux[] = { 2444 RX1_B_MARK, TX1_B_MARK, 2445}; 2446static const unsigned int scif1_clk_pins[] = { 2447 /* SCK1 */ 2448 RCAR_GP_PIN(1, 18), 2449}; 2450static const unsigned int scif1_clk_mux[] = { 2451 SCK1_MARK, 2452}; 2453static const unsigned int scif1_ctrl_pins[] = { 2454 /* RTS1#, CTS1# */ 2455 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), 2456}; 2457static const unsigned int scif1_ctrl_mux[] = { 2458 RTS1_N_MARK, CTS1_N_MARK, 2459}; 2460 2461/* - SCIF3 ------------------------------------------------------------------ */ 2462static const unsigned int scif3_data_pins[] = { 2463 /* RX3, TX3 */ 2464 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2465}; 2466static const unsigned int scif3_data_mux[] = { 2467 RX3_MARK, TX3_MARK, 2468}; 2469static const unsigned int scif3_clk_pins[] = { 2470 /* SCK3 */ 2471 RCAR_GP_PIN(1, 13), 2472}; 2473static const unsigned int scif3_clk_mux[] = { 2474 SCK3_MARK, 2475}; 2476static const unsigned int scif3_ctrl_pins[] = { 2477 /* RTS3#, CTS3# */ 2478 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2479}; 2480static const unsigned int scif3_ctrl_mux[] = { 2481 RTS3_N_MARK, CTS3_N_MARK, 2482}; 2483 2484/* - SCIF4 ------------------------------------------------------------------ */ 2485static const unsigned int scif4_data_pins[] = { 2486 /* RX4, TX4 */ 2487 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 2488}; 2489static const unsigned int scif4_data_mux[] = { 2490 RX4_MARK, TX4_MARK, 2491}; 2492static const unsigned int scif4_clk_pins[] = { 2493 /* SCK4 */ 2494 RCAR_GP_PIN(2, 5), 2495}; 2496static const unsigned int scif4_clk_mux[] = { 2497 SCK4_MARK, 2498}; 2499static const unsigned int scif4_ctrl_pins[] = { 2500 /* RTS4#, CTS4# */ 2501 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), 2502}; 2503static const unsigned int scif4_ctrl_mux[] = { 2504 RTS4_N_MARK, CTS4_N_MARK, 2505}; 2506 2507/* - SCIF Clock ------------------------------------------------------------- */ 2508static const unsigned int scif_clk_pins[] = { 2509 /* SCIF_CLK */ 2510 RCAR_GP_PIN(1, 0), 2511}; 2512static const unsigned int scif_clk_mux[] = { 2513 SCIF_CLK_MARK, 2514}; 2515 2516/* - TMU -------------------------------------------------------------------- */ 2517static const unsigned int tmu_tclk1_a_pins[] = { 2518 /* TCLK1 */ 2519 RCAR_GP_PIN(2, 23), 2520}; 2521static const unsigned int tmu_tclk1_a_mux[] = { 2522 TCLK1_A_MARK, 2523}; 2524static const unsigned int tmu_tclk1_b_pins[] = { 2525 /* TCLK1 */ 2526 RCAR_GP_PIN(1, 23), 2527}; 2528static const unsigned int tmu_tclk1_b_mux[] = { 2529 TCLK1_B_MARK, 2530}; 2531 2532static const unsigned int tmu_tclk2_a_pins[] = { 2533 /* TCLK2 */ 2534 RCAR_GP_PIN(2, 24), 2535}; 2536static const unsigned int tmu_tclk2_a_mux[] = { 2537 TCLK2_A_MARK, 2538}; 2539static const unsigned int tmu_tclk2_b_pins[] = { 2540 /* TCLK2 */ 2541 RCAR_GP_PIN(2, 10), 2542}; 2543static const unsigned int tmu_tclk2_b_mux[] = { 2544 TCLK2_B_MARK, 2545}; 2546 2547static const unsigned int tmu_tclk3_pins[] = { 2548 /* TCLK3 */ 2549 RCAR_GP_PIN(2, 11), 2550}; 2551static const unsigned int tmu_tclk3_mux[] = { 2552 TCLK3_MARK, 2553}; 2554 2555static const unsigned int tmu_tclk4_pins[] = { 2556 /* TCLK4 */ 2557 RCAR_GP_PIN(2, 12), 2558}; 2559static const unsigned int tmu_tclk4_mux[] = { 2560 TCLK4_MARK, 2561}; 2562 2563/* - TPU ------------------------------------------------------------------- */ 2564static const unsigned int tpu_to0_pins[] = { 2565 /* TPU0TO0 */ 2566 RCAR_GP_PIN(2, 21), 2567}; 2568static const unsigned int tpu_to0_mux[] = { 2569 TPU0TO0_MARK, 2570}; 2571static const unsigned int tpu_to1_pins[] = { 2572 /* TPU0TO1 */ 2573 RCAR_GP_PIN(2, 22), 2574}; 2575static const unsigned int tpu_to1_mux[] = { 2576 TPU0TO1_MARK, 2577}; 2578static const unsigned int tpu_to2_pins[] = { 2579 /* TPU0TO2 */ 2580 RCAR_GP_PIN(3, 5), 2581}; 2582static const unsigned int tpu_to2_mux[] = { 2583 TPU0TO2_MARK, 2584}; 2585static const unsigned int tpu_to3_pins[] = { 2586 /* TPU0TO3 */ 2587 RCAR_GP_PIN(3, 6), 2588}; 2589static const unsigned int tpu_to3_mux[] = { 2590 TPU0TO3_MARK, 2591}; 2592 2593static const struct sh_pfc_pin_group pinmux_groups[] = { 2594 SH_PFC_PIN_GROUP(avb0_link), 2595 SH_PFC_PIN_GROUP(avb0_magic), 2596 SH_PFC_PIN_GROUP(avb0_phy_int), 2597 SH_PFC_PIN_GROUP(avb0_mdio), 2598 SH_PFC_PIN_GROUP(avb0_rgmii), 2599 SH_PFC_PIN_GROUP(avb0_txcrefclk), 2600 SH_PFC_PIN_GROUP(avb0_avtp_pps), 2601 SH_PFC_PIN_GROUP(avb0_avtp_capture), 2602 SH_PFC_PIN_GROUP(avb0_avtp_match), 2603 2604 SH_PFC_PIN_GROUP(avb1_link), 2605 SH_PFC_PIN_GROUP(avb1_magic), 2606 SH_PFC_PIN_GROUP(avb1_phy_int), 2607 SH_PFC_PIN_GROUP(avb1_mdio), 2608 SH_PFC_PIN_GROUP(avb1_rgmii), 2609 SH_PFC_PIN_GROUP(avb1_txcrefclk), 2610 SH_PFC_PIN_GROUP(avb1_avtp_pps), 2611 SH_PFC_PIN_GROUP(avb1_avtp_capture), 2612 SH_PFC_PIN_GROUP(avb1_avtp_match), 2613 2614 SH_PFC_PIN_GROUP(avb2_link), 2615 SH_PFC_PIN_GROUP(avb2_magic), 2616 SH_PFC_PIN_GROUP(avb2_phy_int), 2617 SH_PFC_PIN_GROUP(avb2_mdio), 2618 SH_PFC_PIN_GROUP(avb2_rgmii), 2619 SH_PFC_PIN_GROUP(avb2_txcrefclk), 2620 SH_PFC_PIN_GROUP(avb2_avtp_pps), 2621 SH_PFC_PIN_GROUP(avb2_avtp_capture), 2622 SH_PFC_PIN_GROUP(avb2_avtp_match), 2623 2624 SH_PFC_PIN_GROUP(avb3_link), 2625 SH_PFC_PIN_GROUP(avb3_magic), 2626 SH_PFC_PIN_GROUP(avb3_phy_int), 2627 SH_PFC_PIN_GROUP(avb3_mdio), 2628 SH_PFC_PIN_GROUP(avb3_rgmii), 2629 SH_PFC_PIN_GROUP(avb3_txcrefclk), 2630 SH_PFC_PIN_GROUP(avb3_avtp_pps), 2631 SH_PFC_PIN_GROUP(avb3_avtp_capture), 2632 SH_PFC_PIN_GROUP(avb3_avtp_match), 2633 2634 SH_PFC_PIN_GROUP(avb4_link), 2635 SH_PFC_PIN_GROUP(avb4_magic), 2636 SH_PFC_PIN_GROUP(avb4_phy_int), 2637 SH_PFC_PIN_GROUP(avb4_mdio), 2638 SH_PFC_PIN_GROUP(avb4_rgmii), 2639 SH_PFC_PIN_GROUP(avb4_txcrefclk), 2640 SH_PFC_PIN_GROUP(avb4_avtp_pps), 2641 SH_PFC_PIN_GROUP(avb4_avtp_capture), 2642 SH_PFC_PIN_GROUP(avb4_avtp_match), 2643 2644 SH_PFC_PIN_GROUP(avb5_link), 2645 SH_PFC_PIN_GROUP(avb5_magic), 2646 SH_PFC_PIN_GROUP(avb5_phy_int), 2647 SH_PFC_PIN_GROUP(avb5_mdio), 2648 SH_PFC_PIN_GROUP(avb5_rgmii), 2649 SH_PFC_PIN_GROUP(avb5_txcrefclk), 2650 SH_PFC_PIN_GROUP(avb5_avtp_pps), 2651 SH_PFC_PIN_GROUP(avb5_avtp_capture), 2652 SH_PFC_PIN_GROUP(avb5_avtp_match), 2653 2654 SH_PFC_PIN_GROUP(canfd0_data), 2655 SH_PFC_PIN_GROUP(canfd1_data), 2656 SH_PFC_PIN_GROUP(canfd2_data), 2657 SH_PFC_PIN_GROUP(canfd3_data), 2658 SH_PFC_PIN_GROUP(canfd4_data), 2659 SH_PFC_PIN_GROUP(canfd5_data), 2660 SH_PFC_PIN_GROUP(canfd6_data), 2661 SH_PFC_PIN_GROUP(canfd7_data), 2662 SH_PFC_PIN_GROUP(can_clk), 2663 2664 SH_PFC_PIN_GROUP(du_rgb888), 2665 SH_PFC_PIN_GROUP(du_clk_out), 2666 SH_PFC_PIN_GROUP(du_sync), 2667 SH_PFC_PIN_GROUP(du_oddf), 2668 2669 SH_PFC_PIN_GROUP(hscif0_data), 2670 SH_PFC_PIN_GROUP(hscif0_clk), 2671 SH_PFC_PIN_GROUP(hscif0_ctrl), 2672 SH_PFC_PIN_GROUP(hscif1_data), 2673 SH_PFC_PIN_GROUP(hscif1_clk), 2674 SH_PFC_PIN_GROUP(hscif1_ctrl), 2675 SH_PFC_PIN_GROUP(hscif2_data), 2676 SH_PFC_PIN_GROUP(hscif2_clk), 2677 SH_PFC_PIN_GROUP(hscif2_ctrl), 2678 SH_PFC_PIN_GROUP(hscif3_data), 2679 SH_PFC_PIN_GROUP(hscif3_clk), 2680 SH_PFC_PIN_GROUP(hscif3_ctrl), 2681 2682 SH_PFC_PIN_GROUP(i2c0), 2683 SH_PFC_PIN_GROUP(i2c1), 2684 SH_PFC_PIN_GROUP(i2c2), 2685 SH_PFC_PIN_GROUP(i2c3), 2686 SH_PFC_PIN_GROUP(i2c4), 2687 SH_PFC_PIN_GROUP(i2c5), 2688 SH_PFC_PIN_GROUP(i2c6), 2689 2690 SH_PFC_PIN_GROUP(intc_ex_irq0), 2691 SH_PFC_PIN_GROUP(intc_ex_irq1), 2692 SH_PFC_PIN_GROUP(intc_ex_irq2), 2693 SH_PFC_PIN_GROUP(intc_ex_irq3), 2694 SH_PFC_PIN_GROUP(intc_ex_irq4), 2695 SH_PFC_PIN_GROUP(intc_ex_irq5), 2696 2697 BUS_DATA_PIN_GROUP(mmc_data, 1), 2698 BUS_DATA_PIN_GROUP(mmc_data, 4), 2699 BUS_DATA_PIN_GROUP(mmc_data, 8), 2700 SH_PFC_PIN_GROUP(mmc_ctrl), 2701 SH_PFC_PIN_GROUP(mmc_cd), 2702 SH_PFC_PIN_GROUP(mmc_wp), 2703 SH_PFC_PIN_GROUP(mmc_ds), 2704 2705 SH_PFC_PIN_GROUP(msiof0_clk), 2706 SH_PFC_PIN_GROUP(msiof0_sync), 2707 SH_PFC_PIN_GROUP(msiof0_ss1), 2708 SH_PFC_PIN_GROUP(msiof0_ss2), 2709 SH_PFC_PIN_GROUP(msiof0_txd), 2710 SH_PFC_PIN_GROUP(msiof0_rxd), 2711 SH_PFC_PIN_GROUP(msiof1_clk), 2712 SH_PFC_PIN_GROUP(msiof1_sync), 2713 SH_PFC_PIN_GROUP(msiof1_ss1), 2714 SH_PFC_PIN_GROUP(msiof1_ss2), 2715 SH_PFC_PIN_GROUP(msiof1_txd), 2716 SH_PFC_PIN_GROUP(msiof1_rxd), 2717 SH_PFC_PIN_GROUP(msiof2_clk), 2718 SH_PFC_PIN_GROUP(msiof2_sync), 2719 SH_PFC_PIN_GROUP(msiof2_ss1), 2720 SH_PFC_PIN_GROUP(msiof2_ss2), 2721 SH_PFC_PIN_GROUP(msiof2_txd), 2722 SH_PFC_PIN_GROUP(msiof2_rxd), 2723 SH_PFC_PIN_GROUP(msiof3_clk), 2724 SH_PFC_PIN_GROUP(msiof3_sync), 2725 SH_PFC_PIN_GROUP(msiof3_ss1), 2726 SH_PFC_PIN_GROUP(msiof3_ss2), 2727 SH_PFC_PIN_GROUP(msiof3_txd), 2728 SH_PFC_PIN_GROUP(msiof3_rxd), 2729 SH_PFC_PIN_GROUP(msiof4_clk), 2730 SH_PFC_PIN_GROUP(msiof4_sync), 2731 SH_PFC_PIN_GROUP(msiof4_ss1), 2732 SH_PFC_PIN_GROUP(msiof4_ss2), 2733 SH_PFC_PIN_GROUP(msiof4_txd), 2734 SH_PFC_PIN_GROUP(msiof4_rxd), 2735 SH_PFC_PIN_GROUP(msiof5_clk), 2736 SH_PFC_PIN_GROUP(msiof5_sync), 2737 SH_PFC_PIN_GROUP(msiof5_ss1), 2738 SH_PFC_PIN_GROUP(msiof5_ss2), 2739 SH_PFC_PIN_GROUP(msiof5_txd), 2740 SH_PFC_PIN_GROUP(msiof5_rxd), 2741 2742 SH_PFC_PIN_GROUP(pwm0), 2743 SH_PFC_PIN_GROUP(pwm1), 2744 SH_PFC_PIN_GROUP(pwm2), 2745 SH_PFC_PIN_GROUP(pwm3), 2746 SH_PFC_PIN_GROUP(pwm4), 2747 2748 SH_PFC_PIN_GROUP(qspi0_ctrl), 2749 BUS_DATA_PIN_GROUP(qspi0_data, 2), 2750 BUS_DATA_PIN_GROUP(qspi0_data, 4), 2751 SH_PFC_PIN_GROUP(qspi1_ctrl), 2752 BUS_DATA_PIN_GROUP(qspi1_data, 2), 2753 BUS_DATA_PIN_GROUP(qspi1_data, 4), 2754 2755 SH_PFC_PIN_GROUP(scif0_data), 2756 SH_PFC_PIN_GROUP(scif0_clk), 2757 SH_PFC_PIN_GROUP(scif0_ctrl), 2758 SH_PFC_PIN_GROUP(scif1_data_a), 2759 SH_PFC_PIN_GROUP(scif1_data_b), 2760 SH_PFC_PIN_GROUP(scif1_clk), 2761 SH_PFC_PIN_GROUP(scif1_ctrl), 2762 SH_PFC_PIN_GROUP(scif3_data), 2763 SH_PFC_PIN_GROUP(scif3_clk), 2764 SH_PFC_PIN_GROUP(scif3_ctrl), 2765 SH_PFC_PIN_GROUP(scif4_data), 2766 SH_PFC_PIN_GROUP(scif4_clk), 2767 SH_PFC_PIN_GROUP(scif4_ctrl), 2768 SH_PFC_PIN_GROUP(scif_clk), 2769 2770 SH_PFC_PIN_GROUP(tmu_tclk1_a), 2771 SH_PFC_PIN_GROUP(tmu_tclk1_b), 2772 SH_PFC_PIN_GROUP(tmu_tclk2_a), 2773 SH_PFC_PIN_GROUP(tmu_tclk2_b), 2774 SH_PFC_PIN_GROUP(tmu_tclk3), 2775 SH_PFC_PIN_GROUP(tmu_tclk4), 2776 2777 SH_PFC_PIN_GROUP(tpu_to0), 2778 SH_PFC_PIN_GROUP(tpu_to1), 2779 SH_PFC_PIN_GROUP(tpu_to2), 2780 SH_PFC_PIN_GROUP(tpu_to3), 2781}; 2782 2783static const char * const avb0_groups[] = { 2784 "avb0_link", 2785 "avb0_magic", 2786 "avb0_phy_int", 2787 "avb0_mdio", 2788 "avb0_rgmii", 2789 "avb0_txcrefclk", 2790 "avb0_avtp_pps", 2791 "avb0_avtp_capture", 2792 "avb0_avtp_match", 2793}; 2794 2795static const char * const avb1_groups[] = { 2796 "avb1_link", 2797 "avb1_magic", 2798 "avb1_phy_int", 2799 "avb1_mdio", 2800 "avb1_rgmii", 2801 "avb1_txcrefclk", 2802 "avb1_avtp_pps", 2803 "avb1_avtp_capture", 2804 "avb1_avtp_match", 2805}; 2806 2807static const char * const avb2_groups[] = { 2808 "avb2_link", 2809 "avb2_magic", 2810 "avb2_phy_int", 2811 "avb2_mdio", 2812 "avb2_rgmii", 2813 "avb2_txcrefclk", 2814 "avb2_avtp_pps", 2815 "avb2_avtp_capture", 2816 "avb2_avtp_match", 2817}; 2818 2819static const char * const avb3_groups[] = { 2820 "avb3_link", 2821 "avb3_magic", 2822 "avb3_phy_int", 2823 "avb3_mdio", 2824 "avb3_rgmii", 2825 "avb3_txcrefclk", 2826 "avb3_avtp_pps", 2827 "avb3_avtp_capture", 2828 "avb3_avtp_match", 2829}; 2830 2831static const char * const avb4_groups[] = { 2832 "avb4_link", 2833 "avb4_magic", 2834 "avb4_phy_int", 2835 "avb4_mdio", 2836 "avb4_rgmii", 2837 "avb4_txcrefclk", 2838 "avb4_avtp_pps", 2839 "avb4_avtp_capture", 2840 "avb4_avtp_match", 2841}; 2842 2843static const char * const avb5_groups[] = { 2844 "avb5_link", 2845 "avb5_magic", 2846 "avb5_phy_int", 2847 "avb5_mdio", 2848 "avb5_rgmii", 2849 "avb5_txcrefclk", 2850 "avb5_avtp_pps", 2851 "avb5_avtp_capture", 2852 "avb5_avtp_match", 2853}; 2854 2855static const char * const canfd0_groups[] = { 2856 "canfd0_data", 2857}; 2858 2859static const char * const canfd1_groups[] = { 2860 "canfd1_data", 2861}; 2862 2863static const char * const canfd2_groups[] = { 2864 "canfd2_data", 2865}; 2866 2867static const char * const canfd3_groups[] = { 2868 "canfd3_data", 2869}; 2870 2871static const char * const canfd4_groups[] = { 2872 "canfd4_data", 2873}; 2874 2875static const char * const canfd5_groups[] = { 2876 "canfd5_data", 2877}; 2878 2879static const char * const canfd6_groups[] = { 2880 "canfd6_data", 2881}; 2882 2883static const char * const canfd7_groups[] = { 2884 "canfd7_data", 2885}; 2886 2887static const char * const can_clk_groups[] = { 2888 "can_clk", 2889}; 2890 2891static const char * const du_groups[] = { 2892 "du_rgb888", 2893 "du_clk_out", 2894 "du_sync", 2895 "du_oddf", 2896}; 2897 2898static const char * const hscif0_groups[] = { 2899 "hscif0_data", 2900 "hscif0_clk", 2901 "hscif0_ctrl", 2902}; 2903 2904static const char * const hscif1_groups[] = { 2905 "hscif1_data", 2906 "hscif1_clk", 2907 "hscif1_ctrl", 2908}; 2909 2910static const char * const hscif2_groups[] = { 2911 "hscif2_data", 2912 "hscif2_clk", 2913 "hscif2_ctrl", 2914}; 2915 2916static const char * const hscif3_groups[] = { 2917 "hscif3_data", 2918 "hscif3_clk", 2919 "hscif3_ctrl", 2920}; 2921 2922static const char * const i2c0_groups[] = { 2923 "i2c0", 2924}; 2925 2926static const char * const i2c1_groups[] = { 2927 "i2c1", 2928}; 2929 2930static const char * const i2c2_groups[] = { 2931 "i2c2", 2932}; 2933 2934static const char * const i2c3_groups[] = { 2935 "i2c3", 2936}; 2937 2938static const char * const i2c4_groups[] = { 2939 "i2c4", 2940}; 2941 2942static const char * const i2c5_groups[] = { 2943 "i2c5", 2944}; 2945 2946static const char * const i2c6_groups[] = { 2947 "i2c6", 2948}; 2949 2950static const char * const intc_ex_groups[] = { 2951 "intc_ex_irq0", 2952 "intc_ex_irq1", 2953 "intc_ex_irq2", 2954 "intc_ex_irq3", 2955 "intc_ex_irq4", 2956 "intc_ex_irq5", 2957}; 2958 2959static const char * const mmc_groups[] = { 2960 "mmc_data1", 2961 "mmc_data4", 2962 "mmc_data8", 2963 "mmc_ctrl", 2964 "mmc_cd", 2965 "mmc_wp", 2966 "mmc_ds", 2967}; 2968 2969static const char * const msiof0_groups[] = { 2970 "msiof0_clk", 2971 "msiof0_sync", 2972 "msiof0_ss1", 2973 "msiof0_ss2", 2974 "msiof0_txd", 2975 "msiof0_rxd", 2976}; 2977 2978static const char * const msiof1_groups[] = { 2979 "msiof1_clk", 2980 "msiof1_sync", 2981 "msiof1_ss1", 2982 "msiof1_ss2", 2983 "msiof1_txd", 2984 "msiof1_rxd", 2985}; 2986 2987static const char * const msiof2_groups[] = { 2988 "msiof2_clk", 2989 "msiof2_sync", 2990 "msiof2_ss1", 2991 "msiof2_ss2", 2992 "msiof2_txd", 2993 "msiof2_rxd", 2994}; 2995 2996static const char * const msiof3_groups[] = { 2997 "msiof3_clk", 2998 "msiof3_sync", 2999 "msiof3_ss1", 3000 "msiof3_ss2", 3001 "msiof3_txd", 3002 "msiof3_rxd", 3003}; 3004 3005static const char * const msiof4_groups[] = { 3006 "msiof4_clk", 3007 "msiof4_sync", 3008 "msiof4_ss1", 3009 "msiof4_ss2", 3010 "msiof4_txd", 3011 "msiof4_rxd", 3012}; 3013 3014static const char * const msiof5_groups[] = { 3015 "msiof5_clk", 3016 "msiof5_sync", 3017 "msiof5_ss1", 3018 "msiof5_ss2", 3019 "msiof5_txd", 3020 "msiof5_rxd", 3021}; 3022 3023static const char * const pwm0_groups[] = { 3024 "pwm0", 3025}; 3026 3027static const char * const pwm1_groups[] = { 3028 "pwm1", 3029}; 3030 3031static const char * const pwm2_groups[] = { 3032 "pwm2", 3033}; 3034 3035static const char * const pwm3_groups[] = { 3036 "pwm3", 3037}; 3038 3039static const char * const pwm4_groups[] = { 3040 "pwm4", 3041}; 3042 3043static const char * const qspi0_groups[] = { 3044 "qspi0_ctrl", 3045 "qspi0_data2", 3046 "qspi0_data4", 3047}; 3048 3049static const char * const qspi1_groups[] = { 3050 "qspi1_ctrl", 3051 "qspi1_data2", 3052 "qspi1_data4", 3053}; 3054 3055static const char * const scif0_groups[] = { 3056 "scif0_data", 3057 "scif0_clk", 3058 "scif0_ctrl", 3059}; 3060 3061static const char * const scif1_groups[] = { 3062 "scif1_data_a", 3063 "scif1_data_b", 3064 "scif1_clk", 3065 "scif1_ctrl", 3066}; 3067 3068static const char * const scif3_groups[] = { 3069 "scif3_data", 3070 "scif3_clk", 3071 "scif3_ctrl", 3072}; 3073 3074static const char * const scif4_groups[] = { 3075 "scif4_data", 3076 "scif4_clk", 3077 "scif4_ctrl", 3078}; 3079 3080static const char * const scif_clk_groups[] = { 3081 "scif_clk", 3082}; 3083 3084static const char * const tmu_groups[] = { 3085 "tmu_tclk1_a", 3086 "tmu_tclk1_b", 3087 "tmu_tclk2_a", 3088 "tmu_tclk2_b", 3089 "tmu_tclk3", 3090 "tmu_tclk4", 3091}; 3092 3093static const char * const tpu_groups[] = { 3094 "tpu_to0", 3095 "tpu_to1", 3096 "tpu_to2", 3097 "tpu_to3", 3098}; 3099 3100static const struct sh_pfc_function pinmux_functions[] = { 3101 SH_PFC_FUNCTION(avb0), 3102 SH_PFC_FUNCTION(avb1), 3103 SH_PFC_FUNCTION(avb2), 3104 SH_PFC_FUNCTION(avb3), 3105 SH_PFC_FUNCTION(avb4), 3106 SH_PFC_FUNCTION(avb5), 3107 3108 SH_PFC_FUNCTION(canfd0), 3109 SH_PFC_FUNCTION(canfd1), 3110 SH_PFC_FUNCTION(canfd2), 3111 SH_PFC_FUNCTION(canfd3), 3112 SH_PFC_FUNCTION(canfd4), 3113 SH_PFC_FUNCTION(canfd5), 3114 SH_PFC_FUNCTION(canfd6), 3115 SH_PFC_FUNCTION(canfd7), 3116 SH_PFC_FUNCTION(can_clk), 3117 3118 SH_PFC_FUNCTION(du), 3119 3120 SH_PFC_FUNCTION(hscif0), 3121 SH_PFC_FUNCTION(hscif1), 3122 SH_PFC_FUNCTION(hscif2), 3123 SH_PFC_FUNCTION(hscif3), 3124 3125 SH_PFC_FUNCTION(i2c0), 3126 SH_PFC_FUNCTION(i2c1), 3127 SH_PFC_FUNCTION(i2c2), 3128 SH_PFC_FUNCTION(i2c3), 3129 SH_PFC_FUNCTION(i2c4), 3130 SH_PFC_FUNCTION(i2c5), 3131 SH_PFC_FUNCTION(i2c6), 3132 3133 SH_PFC_FUNCTION(intc_ex), 3134 3135 SH_PFC_FUNCTION(mmc), 3136 3137 SH_PFC_FUNCTION(msiof0), 3138 SH_PFC_FUNCTION(msiof1), 3139 SH_PFC_FUNCTION(msiof2), 3140 SH_PFC_FUNCTION(msiof3), 3141 SH_PFC_FUNCTION(msiof4), 3142 SH_PFC_FUNCTION(msiof5), 3143 3144 SH_PFC_FUNCTION(pwm0), 3145 SH_PFC_FUNCTION(pwm1), 3146 SH_PFC_FUNCTION(pwm2), 3147 SH_PFC_FUNCTION(pwm3), 3148 SH_PFC_FUNCTION(pwm4), 3149 3150 SH_PFC_FUNCTION(qspi0), 3151 SH_PFC_FUNCTION(qspi1), 3152 3153 SH_PFC_FUNCTION(scif0), 3154 SH_PFC_FUNCTION(scif1), 3155 SH_PFC_FUNCTION(scif3), 3156 SH_PFC_FUNCTION(scif4), 3157 SH_PFC_FUNCTION(scif_clk), 3158 3159 SH_PFC_FUNCTION(tmu), 3160 3161 SH_PFC_FUNCTION(tpu), 3162}; 3163 3164static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3165#define F_(x, y) FN_##y 3166#define FM(x) FN_##x 3167 { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP( 3168 0, 0, 3169 0, 0, 3170 0, 0, 3171 0, 0, 3172 GP_0_27_FN, GPSR0_27, 3173 GP_0_26_FN, GPSR0_26, 3174 GP_0_25_FN, GPSR0_25, 3175 GP_0_24_FN, GPSR0_24, 3176 GP_0_23_FN, GPSR0_23, 3177 GP_0_22_FN, GPSR0_22, 3178 GP_0_21_FN, GPSR0_21, 3179 GP_0_20_FN, GPSR0_20, 3180 GP_0_19_FN, GPSR0_19, 3181 GP_0_18_FN, GPSR0_18, 3182 GP_0_17_FN, GPSR0_17, 3183 GP_0_16_FN, GPSR0_16, 3184 GP_0_15_FN, GPSR0_15, 3185 GP_0_14_FN, GPSR0_14, 3186 GP_0_13_FN, GPSR0_13, 3187 GP_0_12_FN, GPSR0_12, 3188 GP_0_11_FN, GPSR0_11, 3189 GP_0_10_FN, GPSR0_10, 3190 GP_0_9_FN, GPSR0_9, 3191 GP_0_8_FN, GPSR0_8, 3192 GP_0_7_FN, GPSR0_7, 3193 GP_0_6_FN, GPSR0_6, 3194 GP_0_5_FN, GPSR0_5, 3195 GP_0_4_FN, GPSR0_4, 3196 GP_0_3_FN, GPSR0_3, 3197 GP_0_2_FN, GPSR0_2, 3198 GP_0_1_FN, GPSR0_1, 3199 GP_0_0_FN, GPSR0_0, )) 3200 }, 3201 { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP( 3202 0, 0, 3203 GP_1_30_FN, GPSR1_30, 3204 GP_1_29_FN, GPSR1_29, 3205 GP_1_28_FN, GPSR1_28, 3206 GP_1_27_FN, GPSR1_27, 3207 GP_1_26_FN, GPSR1_26, 3208 GP_1_25_FN, GPSR1_25, 3209 GP_1_24_FN, GPSR1_24, 3210 GP_1_23_FN, GPSR1_23, 3211 GP_1_22_FN, GPSR1_22, 3212 GP_1_21_FN, GPSR1_21, 3213 GP_1_20_FN, GPSR1_20, 3214 GP_1_19_FN, GPSR1_19, 3215 GP_1_18_FN, GPSR1_18, 3216 GP_1_17_FN, GPSR1_17, 3217 GP_1_16_FN, GPSR1_16, 3218 GP_1_15_FN, GPSR1_15, 3219 GP_1_14_FN, GPSR1_14, 3220 GP_1_13_FN, GPSR1_13, 3221 GP_1_12_FN, GPSR1_12, 3222 GP_1_11_FN, GPSR1_11, 3223 GP_1_10_FN, GPSR1_10, 3224 GP_1_9_FN, GPSR1_9, 3225 GP_1_8_FN, GPSR1_8, 3226 GP_1_7_FN, GPSR1_7, 3227 GP_1_6_FN, GPSR1_6, 3228 GP_1_5_FN, GPSR1_5, 3229 GP_1_4_FN, GPSR1_4, 3230 GP_1_3_FN, GPSR1_3, 3231 GP_1_2_FN, GPSR1_2, 3232 GP_1_1_FN, GPSR1_1, 3233 GP_1_0_FN, GPSR1_0, )) 3234 }, 3235 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32, 3236 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3238 GROUP( 3239 /* GP2_31_25 RESERVED */ 3240 GP_2_24_FN, GPSR2_24, 3241 GP_2_23_FN, GPSR2_23, 3242 GP_2_22_FN, GPSR2_22, 3243 GP_2_21_FN, GPSR2_21, 3244 GP_2_20_FN, GPSR2_20, 3245 GP_2_19_FN, GPSR2_19, 3246 GP_2_18_FN, GPSR2_18, 3247 GP_2_17_FN, GPSR2_17, 3248 GP_2_16_FN, GPSR2_16, 3249 GP_2_15_FN, GPSR2_15, 3250 GP_2_14_FN, GPSR2_14, 3251 GP_2_13_FN, GPSR2_13, 3252 GP_2_12_FN, GPSR2_12, 3253 GP_2_11_FN, GPSR2_11, 3254 GP_2_10_FN, GPSR2_10, 3255 GP_2_9_FN, GPSR2_9, 3256 GP_2_8_FN, GPSR2_8, 3257 GP_2_7_FN, GPSR2_7, 3258 GP_2_6_FN, GPSR2_6, 3259 GP_2_5_FN, GPSR2_5, 3260 GP_2_4_FN, GPSR2_4, 3261 GP_2_3_FN, GPSR2_3, 3262 GP_2_2_FN, GPSR2_2, 3263 GP_2_1_FN, GPSR2_1, 3264 GP_2_0_FN, GPSR2_0, )) 3265 }, 3266 { PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32, 3267 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3268 1, 1, 1, 1, 1, 1), 3269 GROUP( 3270 /* GP3_31_17 RESERVED */ 3271 GP_3_16_FN, GPSR3_16, 3272 GP_3_15_FN, GPSR3_15, 3273 GP_3_14_FN, GPSR3_14, 3274 GP_3_13_FN, GPSR3_13, 3275 GP_3_12_FN, GPSR3_12, 3276 GP_3_11_FN, GPSR3_11, 3277 GP_3_10_FN, GPSR3_10, 3278 GP_3_9_FN, GPSR3_9, 3279 GP_3_8_FN, GPSR3_8, 3280 GP_3_7_FN, GPSR3_7, 3281 GP_3_6_FN, GPSR3_6, 3282 GP_3_5_FN, GPSR3_5, 3283 GP_3_4_FN, GPSR3_4, 3284 GP_3_3_FN, GPSR3_3, 3285 GP_3_2_FN, GPSR3_2, 3286 GP_3_1_FN, GPSR3_1, 3287 GP_3_0_FN, GPSR3_0, )) 3288 }, 3289 { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP( 3290 0, 0, 3291 0, 0, 3292 0, 0, 3293 0, 0, 3294 0, 0, 3295 GP_4_26_FN, GPSR4_26, 3296 GP_4_25_FN, GPSR4_25, 3297 GP_4_24_FN, GPSR4_24, 3298 GP_4_23_FN, GPSR4_23, 3299 GP_4_22_FN, GPSR4_22, 3300 GP_4_21_FN, GPSR4_21, 3301 GP_4_20_FN, GPSR4_20, 3302 GP_4_19_FN, GPSR4_19, 3303 GP_4_18_FN, GPSR4_18, 3304 GP_4_17_FN, GPSR4_17, 3305 GP_4_16_FN, GPSR4_16, 3306 GP_4_15_FN, GPSR4_15, 3307 GP_4_14_FN, GPSR4_14, 3308 GP_4_13_FN, GPSR4_13, 3309 GP_4_12_FN, GPSR4_12, 3310 GP_4_11_FN, GPSR4_11, 3311 GP_4_10_FN, GPSR4_10, 3312 GP_4_9_FN, GPSR4_9, 3313 GP_4_8_FN, GPSR4_8, 3314 GP_4_7_FN, GPSR4_7, 3315 GP_4_6_FN, GPSR4_6, 3316 GP_4_5_FN, GPSR4_5, 3317 GP_4_4_FN, GPSR4_4, 3318 GP_4_3_FN, GPSR4_3, 3319 GP_4_2_FN, GPSR4_2, 3320 GP_4_1_FN, GPSR4_1, 3321 GP_4_0_FN, GPSR4_0, )) 3322 }, 3323 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32, 3324 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3325 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3326 GROUP( 3327 /* GP5_31_21 RESERVED */ 3328 GP_5_20_FN, GPSR5_20, 3329 GP_5_19_FN, GPSR5_19, 3330 GP_5_18_FN, GPSR5_18, 3331 GP_5_17_FN, GPSR5_17, 3332 GP_5_16_FN, GPSR5_16, 3333 GP_5_15_FN, GPSR5_15, 3334 GP_5_14_FN, GPSR5_14, 3335 GP_5_13_FN, GPSR5_13, 3336 GP_5_12_FN, GPSR5_12, 3337 GP_5_11_FN, GPSR5_11, 3338 GP_5_10_FN, GPSR5_10, 3339 GP_5_9_FN, GPSR5_9, 3340 GP_5_8_FN, GPSR5_8, 3341 GP_5_7_FN, GPSR5_7, 3342 GP_5_6_FN, GPSR5_6, 3343 GP_5_5_FN, GPSR5_5, 3344 GP_5_4_FN, GPSR5_4, 3345 GP_5_3_FN, GPSR5_3, 3346 GP_5_2_FN, GPSR5_2, 3347 GP_5_1_FN, GPSR5_1, 3348 GP_5_0_FN, GPSR5_0, )) 3349 }, 3350 { PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32, 3351 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3352 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3353 GROUP( 3354 /* GP6_31_21 RESERVED */ 3355 GP_6_20_FN, GPSR6_20, 3356 GP_6_19_FN, GPSR6_19, 3357 GP_6_18_FN, GPSR6_18, 3358 GP_6_17_FN, GPSR6_17, 3359 GP_6_16_FN, GPSR6_16, 3360 GP_6_15_FN, GPSR6_15, 3361 GP_6_14_FN, GPSR6_14, 3362 GP_6_13_FN, GPSR6_13, 3363 GP_6_12_FN, GPSR6_12, 3364 GP_6_11_FN, GPSR6_11, 3365 GP_6_10_FN, GPSR6_10, 3366 GP_6_9_FN, GPSR6_9, 3367 GP_6_8_FN, GPSR6_8, 3368 GP_6_7_FN, GPSR6_7, 3369 GP_6_6_FN, GPSR6_6, 3370 GP_6_5_FN, GPSR6_5, 3371 GP_6_4_FN, GPSR6_4, 3372 GP_6_3_FN, GPSR6_3, 3373 GP_6_2_FN, GPSR6_2, 3374 GP_6_1_FN, GPSR6_1, 3375 GP_6_0_FN, GPSR6_0, )) 3376 }, 3377 { PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32, 3378 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3379 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3380 GROUP( 3381 /* GP7_31_21 RESERVED */ 3382 GP_7_20_FN, GPSR7_20, 3383 GP_7_19_FN, GPSR7_19, 3384 GP_7_18_FN, GPSR7_18, 3385 GP_7_17_FN, GPSR7_17, 3386 GP_7_16_FN, GPSR7_16, 3387 GP_7_15_FN, GPSR7_15, 3388 GP_7_14_FN, GPSR7_14, 3389 GP_7_13_FN, GPSR7_13, 3390 GP_7_12_FN, GPSR7_12, 3391 GP_7_11_FN, GPSR7_11, 3392 GP_7_10_FN, GPSR7_10, 3393 GP_7_9_FN, GPSR7_9, 3394 GP_7_8_FN, GPSR7_8, 3395 GP_7_7_FN, GPSR7_7, 3396 GP_7_6_FN, GPSR7_6, 3397 GP_7_5_FN, GPSR7_5, 3398 GP_7_4_FN, GPSR7_4, 3399 GP_7_3_FN, GPSR7_3, 3400 GP_7_2_FN, GPSR7_2, 3401 GP_7_1_FN, GPSR7_1, 3402 GP_7_0_FN, GPSR7_0, )) 3403 }, 3404 { PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32, 3405 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3407 GROUP( 3408 /* GP8_31_21 RESERVED */ 3409 GP_8_20_FN, GPSR8_20, 3410 GP_8_19_FN, GPSR8_19, 3411 GP_8_18_FN, GPSR8_18, 3412 GP_8_17_FN, GPSR8_17, 3413 GP_8_16_FN, GPSR8_16, 3414 GP_8_15_FN, GPSR8_15, 3415 GP_8_14_FN, GPSR8_14, 3416 GP_8_13_FN, GPSR8_13, 3417 GP_8_12_FN, GPSR8_12, 3418 GP_8_11_FN, GPSR8_11, 3419 GP_8_10_FN, GPSR8_10, 3420 GP_8_9_FN, GPSR8_9, 3421 GP_8_8_FN, GPSR8_8, 3422 GP_8_7_FN, GPSR8_7, 3423 GP_8_6_FN, GPSR8_6, 3424 GP_8_5_FN, GPSR8_5, 3425 GP_8_4_FN, GPSR8_4, 3426 GP_8_3_FN, GPSR8_3, 3427 GP_8_2_FN, GPSR8_2, 3428 GP_8_1_FN, GPSR8_1, 3429 GP_8_0_FN, GPSR8_0, )) 3430 }, 3431 { PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32, 3432 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3434 GROUP( 3435 /* GP9_31_21 RESERVED */ 3436 GP_9_20_FN, GPSR9_20, 3437 GP_9_19_FN, GPSR9_19, 3438 GP_9_18_FN, GPSR9_18, 3439 GP_9_17_FN, GPSR9_17, 3440 GP_9_16_FN, GPSR9_16, 3441 GP_9_15_FN, GPSR9_15, 3442 GP_9_14_FN, GPSR9_14, 3443 GP_9_13_FN, GPSR9_13, 3444 GP_9_12_FN, GPSR9_12, 3445 GP_9_11_FN, GPSR9_11, 3446 GP_9_10_FN, GPSR9_10, 3447 GP_9_9_FN, GPSR9_9, 3448 GP_9_8_FN, GPSR9_8, 3449 GP_9_7_FN, GPSR9_7, 3450 GP_9_6_FN, GPSR9_6, 3451 GP_9_5_FN, GPSR9_5, 3452 GP_9_4_FN, GPSR9_4, 3453 GP_9_3_FN, GPSR9_3, 3454 GP_9_2_FN, GPSR9_2, 3455 GP_9_1_FN, GPSR9_1, 3456 GP_9_0_FN, GPSR9_0, )) 3457 }, 3458#undef F_ 3459#undef FM 3460 3461#define F_(x, y) x, 3462#define FM(x) FN_##x, 3463 { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP( 3464 IP0SR1_31_28 3465 IP0SR1_27_24 3466 IP0SR1_23_20 3467 IP0SR1_19_16 3468 IP0SR1_15_12 3469 IP0SR1_11_8 3470 IP0SR1_7_4 3471 IP0SR1_3_0)) 3472 }, 3473 { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP( 3474 IP1SR1_31_28 3475 IP1SR1_27_24 3476 IP1SR1_23_20 3477 IP1SR1_19_16 3478 IP1SR1_15_12 3479 IP1SR1_11_8 3480 IP1SR1_7_4 3481 IP1SR1_3_0)) 3482 }, 3483 { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP( 3484 IP2SR1_31_28 3485 IP2SR1_27_24 3486 IP2SR1_23_20 3487 IP2SR1_19_16 3488 IP2SR1_15_12 3489 IP2SR1_11_8 3490 IP2SR1_7_4 3491 IP2SR1_3_0)) 3492 }, 3493 { PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32, 3494 GROUP(-4, 4, 4, 4, 4, 4, 4, 4), 3495 GROUP( 3496 /* IP3SR1_31_28 RESERVED */ 3497 IP3SR1_27_24 3498 IP3SR1_23_20 3499 IP3SR1_19_16 3500 IP3SR1_15_12 3501 IP3SR1_11_8 3502 IP3SR1_7_4 3503 IP3SR1_3_0)) 3504 }, 3505 { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP( 3506 IP0SR2_31_28 3507 IP0SR2_27_24 3508 IP0SR2_23_20 3509 IP0SR2_19_16 3510 IP0SR2_15_12 3511 IP0SR2_11_8 3512 IP0SR2_7_4 3513 IP0SR2_3_0)) 3514 }, 3515 { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP( 3516 IP1SR2_31_28 3517 IP1SR2_27_24 3518 IP1SR2_23_20 3519 IP1SR2_19_16 3520 IP1SR2_15_12 3521 IP1SR2_11_8 3522 IP1SR2_7_4 3523 IP1SR2_3_0)) 3524 }, 3525 { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP( 3526 IP2SR2_31_28 3527 IP2SR2_27_24 3528 IP2SR2_23_20 3529 IP2SR2_19_16 3530 IP2SR2_15_12 3531 IP2SR2_11_8 3532 IP2SR2_7_4 3533 IP2SR2_3_0)) 3534 }, 3535 { PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32, 3536 GROUP(4, 4, 4, -8, 4, 4, -4), 3537 GROUP( 3538 IP0SR3_31_28 3539 IP0SR3_27_24 3540 IP0SR3_23_20 3541 /* IP0SR3_19_12 RESERVED */ 3542 IP0SR3_11_8 3543 IP0SR3_7_4 3544 /* IP0SR3_3_0 RESERVED */ )) 3545 }, 3546 { PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32, 3547 GROUP(-8, 4, 4, 4, 4, 4, 4), 3548 GROUP( 3549 /* IP1SR3_31_24 RESERVED */ 3550 IP1SR3_23_20 3551 IP1SR3_19_16 3552 IP1SR3_15_12 3553 IP1SR3_11_8 3554 IP1SR3_7_4 3555 IP1SR3_3_0)) 3556 }, 3557 { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP( 3558 IP0SR4_31_28 3559 IP0SR4_27_24 3560 IP0SR4_23_20 3561 IP0SR4_19_16 3562 IP0SR4_15_12 3563 IP0SR4_11_8 3564 IP0SR4_7_4 3565 IP0SR4_3_0)) 3566 }, 3567 { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP( 3568 IP1SR4_31_28 3569 IP1SR4_27_24 3570 IP1SR4_23_20 3571 IP1SR4_19_16 3572 IP1SR4_15_12 3573 IP1SR4_11_8 3574 IP1SR4_7_4 3575 IP1SR4_3_0)) 3576 }, 3577 { PINMUX_CFG_REG_VAR("IP2SR4", 0xe6060068, 32, 3578 GROUP(-12, 4, 4, 4, 4, -4), 3579 GROUP( 3580 /* IP2SR4_31_20 RESERVED */ 3581 IP2SR4_19_16 3582 IP2SR4_15_12 3583 IP2SR4_11_8 3584 IP2SR4_7_4 3585 /* IP2SR4_3_0 RESERVED */ )) 3586 }, 3587 { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP( 3588 IP0SR5_31_28 3589 IP0SR5_27_24 3590 IP0SR5_23_20 3591 IP0SR5_19_16 3592 IP0SR5_15_12 3593 IP0SR5_11_8 3594 IP0SR5_7_4 3595 IP0SR5_3_0)) 3596 }, 3597 { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP( 3598 IP1SR5_31_28 3599 IP1SR5_27_24 3600 IP1SR5_23_20 3601 IP1SR5_19_16 3602 IP1SR5_15_12 3603 IP1SR5_11_8 3604 IP1SR5_7_4 3605 IP1SR5_3_0)) 3606 }, 3607 { PINMUX_CFG_REG_VAR("IP2SR5", 0xe6060868, 32, 3608 GROUP(-12, 4, 4, 4, 4, -4), 3609 GROUP( 3610 /* IP2SR5_31_20 RESERVED */ 3611 IP2SR5_19_16 3612 IP2SR5_15_12 3613 IP2SR5_11_8 3614 IP2SR5_7_4 3615 /* IP2SR5_3_0 RESERVED */ )) 3616 }, 3617#undef F_ 3618#undef FM 3619 3620#define F_(x, y) x, 3621#define FM(x) FN_##x, 3622 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32, 3623 GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2), 3624 GROUP( 3625 /* RESERVED 31-16 */ 3626 MOD_SEL2_15_14 3627 MOD_SEL2_13_12 3628 MOD_SEL2_11_10 3629 MOD_SEL2_9_8 3630 MOD_SEL2_7_6 3631 MOD_SEL2_5_4 3632 MOD_SEL2_3_2 3633 /* RESERVED 1-0 */ )) 3634 }, 3635 { /* sentinel */ } 3636}; 3637 3638static const struct pinmux_drive_reg pinmux_drive_regs[] = { 3639 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) { 3640 { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */ 3641 { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */ 3642 { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */ 3643 { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */ 3644 { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */ 3645 { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */ 3646 { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */ 3647 { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */ 3648 } }, 3649 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) { 3650 { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */ 3651 { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */ 3652 { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */ 3653 { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */ 3654 { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */ 3655 { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */ 3656 { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */ 3657 { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */ 3658 } }, 3659 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) { 3660 { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */ 3661 { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */ 3662 { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */ 3663 { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */ 3664 { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */ 3665 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */ 3666 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */ 3667 { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */ 3668 } }, 3669 { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) { 3670 { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */ 3671 { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */ 3672 { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */ 3673 { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */ 3674 } }, 3675 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) { 3676 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */ 3677 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */ 3678 { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */ 3679 { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */ 3680 { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */ 3681 { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */ 3682 { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */ 3683 { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */ 3684 } }, 3685 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) { 3686 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */ 3687 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */ 3688 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */ 3689 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */ 3690 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */ 3691 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */ 3692 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */ 3693 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */ 3694 } }, 3695 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) { 3696 { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */ 3697 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */ 3698 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */ 3699 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */ 3700 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */ 3701 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */ 3702 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */ 3703 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */ 3704 } }, 3705 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) { 3706 { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */ 3707 { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */ 3708 { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */ 3709 { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */ 3710 { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */ 3711 { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */ 3712 { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */ 3713 } }, 3714 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) { 3715 { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */ 3716 { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */ 3717 { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */ 3718 { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */ 3719 { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */ 3720 { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */ 3721 { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */ 3722 { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */ 3723 } }, 3724 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) { 3725 { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */ 3726 { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */ 3727 { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */ 3728 { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */ 3729 { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */ 3730 { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */ 3731 { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */ 3732 { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */ 3733 } }, 3734 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) { 3735 { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */ 3736 { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */ 3737 { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */ 3738 { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */ 3739 { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */ 3740 { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */ 3741 { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */ 3742 { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */ 3743 } }, 3744 { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) { 3745 { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */ 3746 } }, 3747 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) { 3748 { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */ 3749 { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */ 3750 { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */ 3751 { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */ 3752 { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */ 3753 { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */ 3754 { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */ 3755 { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */ 3756 } }, 3757 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) { 3758 { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */ 3759 { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */ 3760 { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */ 3761 { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */ 3762 { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */ 3763 { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */ 3764 { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */ 3765 { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */ 3766 } }, 3767 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) { 3768 { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */ 3769 } }, 3770 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) { 3771 { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */ 3772 { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */ 3773 { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */ 3774 { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */ 3775 { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */ 3776 { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */ 3777 { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */ 3778 { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */ 3779 } }, 3780 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) { 3781 { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */ 3782 { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */ 3783 { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */ 3784 { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */ 3785 { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */ 3786 { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */ 3787 { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/ 3788 { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */ 3789 } }, 3790 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) { 3791 { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */ 3792 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */ 3793 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ 3794 { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */ 3795 { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */ 3796 { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */ 3797 { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */ 3798 { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */ 3799 } }, 3800 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) { 3801 { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */ 3802 { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */ 3803 { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */ 3804 } }, 3805 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) { 3806 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */ 3807 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */ 3808 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */ 3809 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */ 3810 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */ 3811 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */ 3812 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */ 3813 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */ 3814 } }, 3815 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) { 3816 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */ 3817 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */ 3818 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */ 3819 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */ 3820 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */ 3821 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */ 3822 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/ 3823 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */ 3824 } }, 3825 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) { 3826 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */ 3827 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */ 3828 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */ 3829 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */ 3830 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */ 3831 } }, 3832 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) { 3833 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */ 3834 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */ 3835 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */ 3836 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */ 3837 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */ 3838 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */ 3839 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */ 3840 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */ 3841 } }, 3842 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) { 3843 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */ 3844 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */ 3845 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */ 3846 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */ 3847 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */ 3848 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */ 3849 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/ 3850 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */ 3851 } }, 3852 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) { 3853 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */ 3854 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */ 3855 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */ 3856 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */ 3857 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */ 3858 } }, 3859 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) { 3860 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */ 3861 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */ 3862 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */ 3863 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */ 3864 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */ 3865 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */ 3866 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */ 3867 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */ 3868 } }, 3869 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) { 3870 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */ 3871 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */ 3872 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */ 3873 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */ 3874 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */ 3875 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */ 3876 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/ 3877 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */ 3878 } }, 3879 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) { 3880 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */ 3881 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */ 3882 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */ 3883 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */ 3884 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */ 3885 } }, 3886 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) { 3887 { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */ 3888 { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */ 3889 { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */ 3890 { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */ 3891 { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */ 3892 { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */ 3893 { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */ 3894 { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */ 3895 } }, 3896 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) { 3897 { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */ 3898 { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */ 3899 { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */ 3900 { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */ 3901 { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */ 3902 { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */ 3903 { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/ 3904 { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */ 3905 } }, 3906 { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) { 3907 { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */ 3908 { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */ 3909 { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */ 3910 { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */ 3911 { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */ 3912 } }, 3913 { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) { 3914 { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */ 3915 { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */ 3916 { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */ 3917 { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */ 3918 { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */ 3919 { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */ 3920 { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */ 3921 { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */ 3922 } }, 3923 { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) { 3924 { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */ 3925 { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */ 3926 { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */ 3927 { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */ 3928 { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */ 3929 { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */ 3930 { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/ 3931 { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */ 3932 } }, 3933 { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) { 3934 { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */ 3935 { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */ 3936 { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */ 3937 { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */ 3938 { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */ 3939 } }, 3940 { /* sentinel */ } 3941}; 3942 3943enum ioctrl_regs { 3944 POC0, 3945 POC1, 3946 POC2, 3947 POC4, 3948 POC5, 3949 POC6, 3950 POC7, 3951 POC8, 3952 POC9, 3953 TD1SEL0, 3954}; 3955 3956static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 3957 [POC0] = { 0xe60580a0, }, 3958 [POC1] = { 0xe60500a0, }, 3959 [POC2] = { 0xe60508a0, }, 3960 [POC4] = { 0xe60600a0, }, 3961 [POC5] = { 0xe60608a0, }, 3962 [POC6] = { 0xe60680a0, }, 3963 [POC7] = { 0xe60688a0, }, 3964 [POC8] = { 0xe60690a0, }, 3965 [POC9] = { 0xe60698a0, }, 3966 [TD1SEL0] = { 0xe6058124, }, 3967 { /* sentinel */ } 3968}; 3969 3970static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 3971{ 3972 int bit = pin & 0x1f; 3973 3974 *pocctrl = pinmux_ioctrl_regs[POC0].reg; 3975 if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27)) 3976 return bit; 3977 3978 *pocctrl = pinmux_ioctrl_regs[POC1].reg; 3979 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30)) 3980 return bit; 3981 3982 *pocctrl = pinmux_ioctrl_regs[POC2].reg; 3983 if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15)) 3984 return bit; 3985 3986 *pocctrl = pinmux_ioctrl_regs[POC4].reg; 3987 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 3988 return bit; 3989 3990 *pocctrl = pinmux_ioctrl_regs[POC5].reg; 3991 if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17)) 3992 return bit; 3993 3994 *pocctrl = pinmux_ioctrl_regs[POC6].reg; 3995 if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17)) 3996 return bit; 3997 3998 *pocctrl = pinmux_ioctrl_regs[POC7].reg; 3999 if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17)) 4000 return bit; 4001 4002 *pocctrl = pinmux_ioctrl_regs[POC8].reg; 4003 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17)) 4004 return bit; 4005 4006 *pocctrl = pinmux_ioctrl_regs[POC9].reg; 4007 if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17)) 4008 return bit; 4009 4010 return -EINVAL; 4011} 4012 4013static const struct pinmux_bias_reg pinmux_bias_regs[] = { 4014 { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) { 4015 [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */ 4016 [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */ 4017 [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */ 4018 [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */ 4019 [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */ 4020 [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */ 4021 [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */ 4022 [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */ 4023 [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */ 4024 [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */ 4025 [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */ 4026 [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */ 4027 [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */ 4028 [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */ 4029 [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */ 4030 [15] = RCAR_GP_PIN(0, 15), /* SD_WP */ 4031 [16] = RCAR_GP_PIN(0, 16), /* SD_CD */ 4032 [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */ 4033 [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */ 4034 [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */ 4035 [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */ 4036 [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */ 4037 [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */ 4038 [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */ 4039 [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */ 4040 [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */ 4041 [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */ 4042 [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */ 4043 [28] = SH_PFC_PIN_NONE, 4044 [29] = SH_PFC_PIN_NONE, 4045 [30] = SH_PFC_PIN_NONE, 4046 [31] = SH_PFC_PIN_NONE, 4047 } }, 4048 { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) { 4049 [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */ 4050 [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */ 4051 [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */ 4052 [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */ 4053 [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */ 4054 [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */ 4055 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */ 4056 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */ 4057 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */ 4058 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */ 4059 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */ 4060 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */ 4061 [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */ 4062 [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */ 4063 [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */ 4064 [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */ 4065 [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */ 4066 [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */ 4067 [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */ 4068 [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */ 4069 [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */ 4070 [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */ 4071 [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */ 4072 [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */ 4073 [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */ 4074 [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */ 4075 [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */ 4076 [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */ 4077 [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */ 4078 [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */ 4079 [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */ 4080 [31] = SH_PFC_PIN_NONE, 4081 } }, 4082 { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) { 4083 [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */ 4084 [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */ 4085 [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */ 4086 [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */ 4087 [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */ 4088 [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */ 4089 [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */ 4090 [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */ 4091 [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */ 4092 [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */ 4093 [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */ 4094 [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */ 4095 [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */ 4096 [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */ 4097 [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */ 4098 [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */ 4099 [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */ 4100 [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */ 4101 [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */ 4102 [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */ 4103 [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */ 4104 [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */ 4105 [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */ 4106 [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */ 4107 [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */ 4108 [25] = SH_PFC_PIN_NONE, 4109 [26] = SH_PFC_PIN_NONE, 4110 [27] = SH_PFC_PIN_NONE, 4111 [28] = SH_PFC_PIN_NONE, 4112 [29] = SH_PFC_PIN_NONE, 4113 [30] = SH_PFC_PIN_NONE, 4114 [31] = SH_PFC_PIN_NONE, 4115 } }, 4116 { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) { 4117 [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */ 4118 [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */ 4119 [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */ 4120 [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */ 4121 [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */ 4122 [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */ 4123 [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */ 4124 [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */ 4125 [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */ 4126 [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */ 4127 [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */ 4128 [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */ 4129 [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */ 4130 [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */ 4131 [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */ 4132 [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */ 4133 [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */ 4134 [17] = SH_PFC_PIN_NONE, 4135 [18] = SH_PFC_PIN_NONE, 4136 [19] = SH_PFC_PIN_NONE, 4137 [20] = SH_PFC_PIN_NONE, 4138 [21] = SH_PFC_PIN_NONE, 4139 [22] = SH_PFC_PIN_NONE, 4140 [23] = SH_PFC_PIN_NONE, 4141 [24] = SH_PFC_PIN_NONE, 4142 [25] = SH_PFC_PIN_NONE, 4143 [26] = SH_PFC_PIN_NONE, 4144 [27] = SH_PFC_PIN_NONE, 4145 [28] = SH_PFC_PIN_NONE, 4146 [29] = SH_PFC_PIN_NONE, 4147 [30] = SH_PFC_PIN_NONE, 4148 [31] = SH_PFC_PIN_NONE, 4149 } }, 4150 { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) { 4151 [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */ 4152 [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */ 4153 [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */ 4154 [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */ 4155 [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */ 4156 [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */ 4157 [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */ 4158 [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */ 4159 [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */ 4160 [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */ 4161 [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */ 4162 [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */ 4163 [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */ 4164 [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */ 4165 [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */ 4166 [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */ 4167 [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */ 4168 [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */ 4169 [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */ 4170 [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */ 4171 [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */ 4172 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ 4173 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */ 4174 [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */ 4175 [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */ 4176 [25] = RCAR_GP_PIN(4, 25), /* AVS0 */ 4177 [26] = RCAR_GP_PIN(4, 26), /* AVS1 */ 4178 [27] = SH_PFC_PIN_NONE, 4179 [28] = SH_PFC_PIN_NONE, 4180 [29] = SH_PFC_PIN_NONE, 4181 [30] = SH_PFC_PIN_NONE, 4182 [31] = SH_PFC_PIN_NONE, 4183 } }, 4184 { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) { 4185 [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */ 4186 [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */ 4187 [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */ 4188 [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */ 4189 [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */ 4190 [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */ 4191 [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */ 4192 [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */ 4193 [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */ 4194 [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */ 4195 [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */ 4196 [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */ 4197 [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */ 4198 [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */ 4199 [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */ 4200 [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */ 4201 [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */ 4202 [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */ 4203 [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */ 4204 [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */ 4205 [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */ 4206 [21] = SH_PFC_PIN_NONE, 4207 [22] = SH_PFC_PIN_NONE, 4208 [23] = SH_PFC_PIN_NONE, 4209 [24] = SH_PFC_PIN_NONE, 4210 [25] = SH_PFC_PIN_NONE, 4211 [26] = SH_PFC_PIN_NONE, 4212 [27] = SH_PFC_PIN_NONE, 4213 [28] = SH_PFC_PIN_NONE, 4214 [29] = SH_PFC_PIN_NONE, 4215 [30] = SH_PFC_PIN_NONE, 4216 [31] = SH_PFC_PIN_NONE, 4217 } }, 4218 { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) { 4219 [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */ 4220 [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */ 4221 [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */ 4222 [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */ 4223 [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */ 4224 [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */ 4225 [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */ 4226 [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */ 4227 [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */ 4228 [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */ 4229 [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */ 4230 [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */ 4231 [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */ 4232 [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */ 4233 [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */ 4234 [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */ 4235 [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */ 4236 [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */ 4237 [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */ 4238 [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */ 4239 [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */ 4240 [21] = SH_PFC_PIN_NONE, 4241 [22] = SH_PFC_PIN_NONE, 4242 [23] = SH_PFC_PIN_NONE, 4243 [24] = SH_PFC_PIN_NONE, 4244 [25] = SH_PFC_PIN_NONE, 4245 [26] = SH_PFC_PIN_NONE, 4246 [27] = SH_PFC_PIN_NONE, 4247 [28] = SH_PFC_PIN_NONE, 4248 [29] = SH_PFC_PIN_NONE, 4249 [30] = SH_PFC_PIN_NONE, 4250 [31] = SH_PFC_PIN_NONE, 4251 } }, 4252 { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) { 4253 [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */ 4254 [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */ 4255 [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */ 4256 [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */ 4257 [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */ 4258 [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */ 4259 [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */ 4260 [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */ 4261 [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */ 4262 [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */ 4263 [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */ 4264 [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */ 4265 [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */ 4266 [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */ 4267 [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */ 4268 [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */ 4269 [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */ 4270 [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */ 4271 [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */ 4272 [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */ 4273 [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */ 4274 [21] = SH_PFC_PIN_NONE, 4275 [22] = SH_PFC_PIN_NONE, 4276 [23] = SH_PFC_PIN_NONE, 4277 [24] = SH_PFC_PIN_NONE, 4278 [25] = SH_PFC_PIN_NONE, 4279 [26] = SH_PFC_PIN_NONE, 4280 [27] = SH_PFC_PIN_NONE, 4281 [28] = SH_PFC_PIN_NONE, 4282 [29] = SH_PFC_PIN_NONE, 4283 [30] = SH_PFC_PIN_NONE, 4284 [31] = SH_PFC_PIN_NONE, 4285 } }, 4286 { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) { 4287 [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */ 4288 [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */ 4289 [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */ 4290 [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */ 4291 [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */ 4292 [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */ 4293 [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */ 4294 [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */ 4295 [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */ 4296 [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */ 4297 [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */ 4298 [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */ 4299 [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */ 4300 [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */ 4301 [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */ 4302 [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */ 4303 [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */ 4304 [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */ 4305 [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */ 4306 [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */ 4307 [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */ 4308 [21] = SH_PFC_PIN_NONE, 4309 [22] = SH_PFC_PIN_NONE, 4310 [23] = SH_PFC_PIN_NONE, 4311 [24] = SH_PFC_PIN_NONE, 4312 [25] = SH_PFC_PIN_NONE, 4313 [26] = SH_PFC_PIN_NONE, 4314 [27] = SH_PFC_PIN_NONE, 4315 [28] = SH_PFC_PIN_NONE, 4316 [29] = SH_PFC_PIN_NONE, 4317 [30] = SH_PFC_PIN_NONE, 4318 [31] = SH_PFC_PIN_NONE, 4319 } }, 4320 { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) { 4321 [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */ 4322 [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */ 4323 [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */ 4324 [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */ 4325 [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */ 4326 [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */ 4327 [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */ 4328 [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */ 4329 [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */ 4330 [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */ 4331 [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */ 4332 [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */ 4333 [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */ 4334 [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */ 4335 [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */ 4336 [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */ 4337 [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */ 4338 [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */ 4339 [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */ 4340 [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */ 4341 [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */ 4342 [21] = SH_PFC_PIN_NONE, 4343 [22] = SH_PFC_PIN_NONE, 4344 [23] = SH_PFC_PIN_NONE, 4345 [24] = SH_PFC_PIN_NONE, 4346 [25] = SH_PFC_PIN_NONE, 4347 [26] = SH_PFC_PIN_NONE, 4348 [27] = SH_PFC_PIN_NONE, 4349 [28] = SH_PFC_PIN_NONE, 4350 [29] = SH_PFC_PIN_NONE, 4351 [30] = SH_PFC_PIN_NONE, 4352 [31] = SH_PFC_PIN_NONE, 4353 } }, 4354 { /* sentinel */ } 4355}; 4356 4357static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = { 4358 .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, 4359 .get_bias = rcar_pinmux_get_bias, 4360 .set_bias = rcar_pinmux_set_bias, 4361}; 4362 4363const struct sh_pfc_soc_info r8a779a0_pinmux_info = { 4364 .name = "r8a779a0_pfc", 4365 .ops = &r8a779a0_pfc_ops, 4366 .unlock_reg = 0x1ff, /* PMMRn mask */ 4367 4368 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 4369 4370 .pins = pinmux_pins, 4371 .nr_pins = ARRAY_SIZE(pinmux_pins), 4372 .groups = pinmux_groups, 4373 .nr_groups = ARRAY_SIZE(pinmux_groups), 4374 .functions = pinmux_functions, 4375 .nr_functions = ARRAY_SIZE(pinmux_functions), 4376 4377 .cfg_regs = pinmux_config_regs, 4378 .drive_regs = pinmux_drive_regs, 4379 .bias_regs = pinmux_bias_regs, 4380 .ioctrl_regs = pinmux_ioctrl_regs, 4381 4382 .pinmux_data = pinmux_data, 4383 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 4384}; 4385