1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R8A77965 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * Copyright (C) 2016-2019 Renesas Electronics Corp. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15#include <dm.h> 16#include <errno.h> 17#include <dm/pinctrl.h> 18#include <linux/kernel.h> 19 20#include "sh_pfc.h" 21 22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 23 24#define CPU_ALL_GP(fn, sfx) \ 25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 37 38#define CPU_ALL_NOGP(fn) \ 39 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 57 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 58 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 72 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 75 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 76 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 77 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 78 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 79 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 80 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 81 82/* 83 * F_() : just information 84 * FM() : macro for FN_xxx / xxx_MARK 85 */ 86 87/* GPSR0 */ 88#define GPSR0_15 F_(D15, IP7_11_8) 89#define GPSR0_14 F_(D14, IP7_7_4) 90#define GPSR0_13 F_(D13, IP7_3_0) 91#define GPSR0_12 F_(D12, IP6_31_28) 92#define GPSR0_11 F_(D11, IP6_27_24) 93#define GPSR0_10 F_(D10, IP6_23_20) 94#define GPSR0_9 F_(D9, IP6_19_16) 95#define GPSR0_8 F_(D8, IP6_15_12) 96#define GPSR0_7 F_(D7, IP6_11_8) 97#define GPSR0_6 F_(D6, IP6_7_4) 98#define GPSR0_5 F_(D5, IP6_3_0) 99#define GPSR0_4 F_(D4, IP5_31_28) 100#define GPSR0_3 F_(D3, IP5_27_24) 101#define GPSR0_2 F_(D2, IP5_23_20) 102#define GPSR0_1 F_(D1, IP5_19_16) 103#define GPSR0_0 F_(D0, IP5_15_12) 104 105/* GPSR1 */ 106#define GPSR1_28 FM(CLKOUT) 107#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 108#define GPSR1_26 F_(WE1_N, IP5_7_4) 109#define GPSR1_25 F_(WE0_N, IP5_3_0) 110#define GPSR1_24 F_(RD_WR_N, IP4_31_28) 111#define GPSR1_23 F_(RD_N, IP4_27_24) 112#define GPSR1_22 F_(BS_N, IP4_23_20) 113#define GPSR1_21 F_(CS1_N, IP4_19_16) 114#define GPSR1_20 F_(CS0_N, IP4_15_12) 115#define GPSR1_19 F_(A19, IP4_11_8) 116#define GPSR1_18 F_(A18, IP4_7_4) 117#define GPSR1_17 F_(A17, IP4_3_0) 118#define GPSR1_16 F_(A16, IP3_31_28) 119#define GPSR1_15 F_(A15, IP3_27_24) 120#define GPSR1_14 F_(A14, IP3_23_20) 121#define GPSR1_13 F_(A13, IP3_19_16) 122#define GPSR1_12 F_(A12, IP3_15_12) 123#define GPSR1_11 F_(A11, IP3_11_8) 124#define GPSR1_10 F_(A10, IP3_7_4) 125#define GPSR1_9 F_(A9, IP3_3_0) 126#define GPSR1_8 F_(A8, IP2_31_28) 127#define GPSR1_7 F_(A7, IP2_27_24) 128#define GPSR1_6 F_(A6, IP2_23_20) 129#define GPSR1_5 F_(A5, IP2_19_16) 130#define GPSR1_4 F_(A4, IP2_15_12) 131#define GPSR1_3 F_(A3, IP2_11_8) 132#define GPSR1_2 F_(A2, IP2_7_4) 133#define GPSR1_1 F_(A1, IP2_3_0) 134#define GPSR1_0 F_(A0, IP1_31_28) 135 136/* GPSR2 */ 137#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 138#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 139#define GPSR2_12 F_(AVB_LINK, IP0_15_12) 140#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 141#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 142#define GPSR2_9 F_(AVB_MDC, IP0_3_0) 143#define GPSR2_8 F_(PWM2_A, IP1_27_24) 144#define GPSR2_7 F_(PWM1_A, IP1_23_20) 145#define GPSR2_6 F_(PWM0, IP1_19_16) 146#define GPSR2_5 F_(IRQ5, IP1_15_12) 147#define GPSR2_4 F_(IRQ4, IP1_11_8) 148#define GPSR2_3 F_(IRQ3, IP1_7_4) 149#define GPSR2_2 F_(IRQ2, IP1_3_0) 150#define GPSR2_1 F_(IRQ1, IP0_31_28) 151#define GPSR2_0 F_(IRQ0, IP0_27_24) 152 153/* GPSR3 */ 154#define GPSR3_15 F_(SD1_WP, IP11_23_20) 155#define GPSR3_14 F_(SD1_CD, IP11_19_16) 156#define GPSR3_13 F_(SD0_WP, IP11_15_12) 157#define GPSR3_12 F_(SD0_CD, IP11_11_8) 158#define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 159#define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 160#define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 161#define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 162#define GPSR3_7 F_(SD1_CMD, IP8_15_12) 163#define GPSR3_6 F_(SD1_CLK, IP8_11_8) 164#define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 165#define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 166#define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 167#define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 168#define GPSR3_1 F_(SD0_CMD, IP7_23_20) 169#define GPSR3_0 F_(SD0_CLK, IP7_19_16) 170 171/* GPSR4 */ 172#define GPSR4_17 F_(SD3_DS, IP11_7_4) 173#define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 174#define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 175#define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 176#define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 177#define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 178#define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 179#define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 180#define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 181#define GPSR4_8 F_(SD3_CMD, IP10_3_0) 182#define GPSR4_7 F_(SD3_CLK, IP9_31_28) 183#define GPSR4_6 F_(SD2_DS, IP9_27_24) 184#define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 185#define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 186#define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 187#define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 188#define GPSR4_1 F_(SD2_CMD, IP9_7_4) 189#define GPSR4_0 F_(SD2_CLK, IP9_3_0) 190 191/* GPSR5 */ 192#define GPSR5_25 F_(MLB_DAT, IP14_19_16) 193#define GPSR5_24 F_(MLB_SIG, IP14_15_12) 194#define GPSR5_23 F_(MLB_CLK, IP14_11_8) 195#define GPSR5_22 FM(MSIOF0_RXD) 196#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 197#define GPSR5_20 FM(MSIOF0_TXD) 198#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 199#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 200#define GPSR5_17 FM(MSIOF0_SCK) 201#define GPSR5_16 F_(HRTS0_N, IP13_27_24) 202#define GPSR5_15 F_(HCTS0_N, IP13_23_20) 203#define GPSR5_14 F_(HTX0, IP13_19_16) 204#define GPSR5_13 F_(HRX0, IP13_15_12) 205#define GPSR5_12 F_(HSCK0, IP13_11_8) 206#define GPSR5_11 F_(RX2_A, IP13_7_4) 207#define GPSR5_10 F_(TX2_A, IP13_3_0) 208#define GPSR5_9 F_(SCK2, IP12_31_28) 209#define GPSR5_8 F_(RTS1_N, IP12_27_24) 210#define GPSR5_7 F_(CTS1_N, IP12_23_20) 211#define GPSR5_6 F_(TX1_A, IP12_19_16) 212#define GPSR5_5 F_(RX1_A, IP12_15_12) 213#define GPSR5_4 F_(RTS0_N, IP12_11_8) 214#define GPSR5_3 F_(CTS0_N, IP12_7_4) 215#define GPSR5_2 F_(TX0, IP12_3_0) 216#define GPSR5_1 F_(RX0, IP11_31_28) 217#define GPSR5_0 F_(SCK0, IP11_27_24) 218 219/* GPSR6 */ 220#define GPSR6_31 F_(GP6_31, IP18_7_4) 221#define GPSR6_30 F_(GP6_30, IP18_3_0) 222#define GPSR6_29 F_(USB30_OVC, IP17_31_28) 223#define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 224#define GPSR6_27 F_(USB1_OVC, IP17_23_20) 225#define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 226#define GPSR6_25 F_(USB0_OVC, IP17_15_12) 227#define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 228#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 229#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 230#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 231#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 232#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 233#define GPSR6_18 F_(SSI_WS78, IP16_19_16) 234#define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 235#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 236#define GPSR6_15 F_(SSI_WS6, IP16_7_4) 237#define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 238#define GPSR6_13 FM(SSI_SDATA5) 239#define GPSR6_12 FM(SSI_WS5) 240#define GPSR6_11 FM(SSI_SCK5) 241#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 242#define GPSR6_9 F_(SSI_WS4, IP15_27_24) 243#define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 244#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 245#define GPSR6_6 F_(SSI_WS349, IP15_15_12) 246#define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 247#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 248#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 249#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 250#define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 251#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 252 253/* GPSR7 */ 254#define GPSR7_3 FM(GP7_03) 255#define GPSR7_2 FM(GP7_02) 256#define GPSR7_1 FM(AVS2) 257#define GPSR7_0 FM(AVS1) 258 259 260/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 261#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 289/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 290#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319 320/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 321#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 356/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 357#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 378#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385 386/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 387#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 405#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 406#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 407#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 408#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 409#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 410#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 411#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 412#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 413#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 414 415#define PINMUX_GPSR \ 416\ 417 GPSR6_31 \ 418 GPSR6_30 \ 419 GPSR6_29 \ 420 GPSR1_28 GPSR6_28 \ 421 GPSR1_27 GPSR6_27 \ 422 GPSR1_26 GPSR6_26 \ 423 GPSR1_25 GPSR5_25 GPSR6_25 \ 424 GPSR1_24 GPSR5_24 GPSR6_24 \ 425 GPSR1_23 GPSR5_23 GPSR6_23 \ 426 GPSR1_22 GPSR5_22 GPSR6_22 \ 427 GPSR1_21 GPSR5_21 GPSR6_21 \ 428 GPSR1_20 GPSR5_20 GPSR6_20 \ 429 GPSR1_19 GPSR5_19 GPSR6_19 \ 430 GPSR1_18 GPSR5_18 GPSR6_18 \ 431 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 432 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 433GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 434GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 435GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 436GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 437GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 438GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 439GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 440GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 441GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 442GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 443GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 444GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 445GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 446GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 447GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 448GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 449 450#define PINMUX_IPSR \ 451\ 452FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 453FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 454FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 455FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 456FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 457FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 458FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 459FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 460\ 461FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 462FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 463FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 464FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 465FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 466FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 467FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 468FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 469\ 470FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 471FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 472FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 473FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 474FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 475FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 476FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 477FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 478\ 479FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 480FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 481FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 482FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 483FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 484FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 485FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 486FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 487\ 488FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 489FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 490FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 491FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 492FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 493FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 494FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 495FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 496 497/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 498#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 499#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 500#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 501#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 502#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 503#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 504#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 505#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 506#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 507#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 508#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 509#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 510#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 511#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 512#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 513#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 514#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 515#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 516 517/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 518#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 519#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 520#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 521#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 522#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 523#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 524#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 525#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 526#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 527#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 528#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 529#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 530#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 531#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 532#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 533#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 534#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 535#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 536#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 537#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 538#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 539#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 540 541/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 542#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 543#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 544#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 545#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 546#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 547#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 548#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 549#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 550#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 551#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 552#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 553#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 554#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 555 556#define PINMUX_MOD_SELS \ 557\ 558MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 559 MOD_SEL2_30 \ 560 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 561MOD_SEL0_28_27 MOD_SEL2_28_27 \ 562MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 563 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 564MOD_SEL0_23 MOD_SEL1_23_22_21 \ 565MOD_SEL0_22 MOD_SEL2_22 \ 566MOD_SEL0_21 MOD_SEL2_21 \ 567MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 568MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 569MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 570 MOD_SEL2_17 \ 571MOD_SEL0_16 MOD_SEL1_16 \ 572 MOD_SEL1_15_14 \ 573MOD_SEL0_14_13 \ 574 MOD_SEL1_13 \ 575MOD_SEL0_12 MOD_SEL1_12 \ 576MOD_SEL0_11 MOD_SEL1_11 \ 577MOD_SEL0_10 MOD_SEL1_10 \ 578MOD_SEL0_9_8 MOD_SEL1_9 \ 579MOD_SEL0_7_6 \ 580 MOD_SEL1_6 \ 581MOD_SEL0_5 MOD_SEL1_5 \ 582MOD_SEL0_4_3 MOD_SEL1_4 \ 583 MOD_SEL1_3 \ 584 MOD_SEL1_2 \ 585 MOD_SEL1_1 \ 586 MOD_SEL1_0 MOD_SEL2_0 587 588/* 589 * These pins are not able to be muxed but have other properties 590 * that can be set, such as drive-strength or pull-up/pull-down enable. 591 */ 592#define PINMUX_STATIC \ 593 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 594 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 595 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 596 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 597 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 598 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 599 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 600 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 601 FM(PRESETOUT) \ 602 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ 603 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 604 605#define PINMUX_PHYS \ 606 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 607 608enum { 609 PINMUX_RESERVED = 0, 610 611 PINMUX_DATA_BEGIN, 612 GP_ALL(DATA), 613 PINMUX_DATA_END, 614 615#define F_(x, y) 616#define FM(x) FN_##x, 617 PINMUX_FUNCTION_BEGIN, 618 GP_ALL(FN), 619 PINMUX_GPSR 620 PINMUX_IPSR 621 PINMUX_MOD_SELS 622 PINMUX_FUNCTION_END, 623#undef F_ 624#undef FM 625 626#define F_(x, y) 627#define FM(x) x##_MARK, 628 PINMUX_MARK_BEGIN, 629 PINMUX_GPSR 630 PINMUX_IPSR 631 PINMUX_MOD_SELS 632 PINMUX_STATIC 633 PINMUX_PHYS 634 PINMUX_MARK_END, 635#undef F_ 636#undef FM 637}; 638 639static const u16 pinmux_data[] = { 640 PINMUX_DATA_GP_ALL(), 641 642 PINMUX_SINGLE(AVS1), 643 PINMUX_SINGLE(AVS2), 644 PINMUX_SINGLE(CLKOUT), 645 PINMUX_SINGLE(GP7_03), 646 PINMUX_SINGLE(GP7_02), 647 PINMUX_SINGLE(MSIOF0_RXD), 648 PINMUX_SINGLE(MSIOF0_SCK), 649 PINMUX_SINGLE(MSIOF0_TXD), 650 PINMUX_SINGLE(SSI_SCK5), 651 PINMUX_SINGLE(SSI_SDATA5), 652 PINMUX_SINGLE(SSI_WS5), 653 654 /* IPSR0 */ 655 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 656 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 657 658 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 659 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 660 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 661 662 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 663 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 664 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 665 666 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 667 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 668 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 669 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), 670 671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 673 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 674 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 675 676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 678 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 679 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 680 681 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 682 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 683 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 684 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 685 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 686 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 687 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 688 689 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 690 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 691 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 692 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 693 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 694 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 695 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 696 697 /* IPSR1 */ 698 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 699 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 700 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 701 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 702 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 703 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 704 705 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 706 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 707 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 708 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 709 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 710 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 711 712 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 713 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 714 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 715 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 716 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 717 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 718 719 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 720 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 721 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 722 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 723 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 724 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 725 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 726 727 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 728 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 729 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 730 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 731 732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 735 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 736 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 737 738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 740 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 741 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 742 743 PINMUX_IPSR_GPSR(IP1_31_28, A0), 744 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 745 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 746 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 747 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 748 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 749 750 /* IPSR2 */ 751 PINMUX_IPSR_GPSR(IP2_3_0, A1), 752 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 753 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 754 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 755 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 756 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 757 758 PINMUX_IPSR_GPSR(IP2_7_4, A2), 759 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 760 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 761 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 762 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 763 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 764 765 PINMUX_IPSR_GPSR(IP2_11_8, A3), 766 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 767 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 768 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 769 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 770 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 771 772 PINMUX_IPSR_GPSR(IP2_15_12, A4), 773 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 774 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 775 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 776 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 777 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 778 779 PINMUX_IPSR_GPSR(IP2_19_16, A5), 780 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 781 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 782 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 783 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 784 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 785 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 786 787 PINMUX_IPSR_GPSR(IP2_23_20, A6), 788 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 789 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 790 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 791 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 792 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 793 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 794 795 PINMUX_IPSR_GPSR(IP2_27_24, A7), 796 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 797 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 798 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 799 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 800 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 801 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 802 803 PINMUX_IPSR_GPSR(IP2_31_28, A8), 804 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 805 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 806 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 807 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 808 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 809 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 810 811 /* IPSR3 */ 812 PINMUX_IPSR_GPSR(IP3_3_0, A9), 813 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 814 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 815 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 816 817 PINMUX_IPSR_GPSR(IP3_7_4, A10), 818 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 819 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 820 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 821 822 PINMUX_IPSR_GPSR(IP3_11_8, A11), 823 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 824 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 825 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 826 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 827 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 828 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 829 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 830 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 831 832 PINMUX_IPSR_GPSR(IP3_15_12, A12), 833 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 834 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 835 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 836 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 837 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 838 839 PINMUX_IPSR_GPSR(IP3_19_16, A13), 840 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 841 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 842 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 843 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 844 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 845 846 PINMUX_IPSR_GPSR(IP3_23_20, A14), 847 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 848 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 849 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 850 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 851 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 852 853 PINMUX_IPSR_GPSR(IP3_27_24, A15), 854 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 855 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 856 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 857 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 858 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 859 860 PINMUX_IPSR_GPSR(IP3_31_28, A16), 861 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 862 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 863 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 864 865 /* IPSR4 */ 866 PINMUX_IPSR_GPSR(IP4_3_0, A17), 867 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 868 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 869 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 870 871 PINMUX_IPSR_GPSR(IP4_7_4, A18), 872 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 873 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 874 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 875 876 PINMUX_IPSR_GPSR(IP4_11_8, A19), 877 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 878 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 879 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 880 881 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 882 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 883 884 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 885 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 886 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 887 888 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 889 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 890 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 891 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 892 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 893 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 894 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 895 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 896 897 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 898 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 899 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 900 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 901 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 902 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 903 904 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 905 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 906 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 907 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 908 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 909 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 910 911 /* IPSR5 */ 912 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 913 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 914 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 915 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 916 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 917 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 918 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 919 920 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 921 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 922 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 923 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 924 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 925 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 926 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 927 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 928 929 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 930 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 931 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 932 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 933 934 PINMUX_IPSR_GPSR(IP5_15_12, D0), 935 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 936 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 937 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 938 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 939 940 PINMUX_IPSR_GPSR(IP5_19_16, D1), 941 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 942 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 943 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 944 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 945 946 PINMUX_IPSR_GPSR(IP5_23_20, D2), 947 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 948 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 949 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 950 951 PINMUX_IPSR_GPSR(IP5_27_24, D3), 952 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 953 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 954 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 955 956 PINMUX_IPSR_GPSR(IP5_31_28, D4), 957 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 958 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 959 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 960 961 /* IPSR6 */ 962 PINMUX_IPSR_GPSR(IP6_3_0, D5), 963 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 964 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 965 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 966 967 PINMUX_IPSR_GPSR(IP6_7_4, D6), 968 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 969 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 970 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 971 972 PINMUX_IPSR_GPSR(IP6_11_8, D7), 973 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 974 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 975 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 976 977 PINMUX_IPSR_GPSR(IP6_15_12, D8), 978 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 979 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 980 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 981 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 982 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 983 984 PINMUX_IPSR_GPSR(IP6_19_16, D9), 985 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 986 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 987 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 988 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 989 990 PINMUX_IPSR_GPSR(IP6_23_20, D10), 991 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 992 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 993 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 994 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 995 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 996 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 997 998 PINMUX_IPSR_GPSR(IP6_27_24, D11), 999 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 1000 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 1001 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 1002 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1003 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 1004 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1005 1006 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1007 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1008 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1009 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1010 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1011 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1012 1013 /* IPSR7 */ 1014 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1015 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1016 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1017 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1018 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1019 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1020 1021 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1022 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1023 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1024 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1025 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1026 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1027 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1028 1029 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1030 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1031 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1032 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1033 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1034 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1035 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1036 1037 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1038 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1039 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1040 1041 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1042 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1043 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1044 1045 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1046 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1047 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1048 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1049 1050 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1051 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1052 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1053 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1054 1055 /* IPSR8 */ 1056 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1057 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1058 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1059 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1060 1061 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1062 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1063 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1064 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1065 1066 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1067 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1068 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1069 1070 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1071 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1072 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1073 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1074 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1075 1076 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1077 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1078 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1079 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1080 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1081 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1082 1083 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1084 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1085 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1086 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1087 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1088 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1089 1090 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1091 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1092 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1093 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1094 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1095 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1096 1097 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1098 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1099 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1100 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1101 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1102 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1103 1104 /* IPSR9 */ 1105 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1106 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1107 1108 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1109 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1110 1111 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1112 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1113 1114 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1115 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1116 1117 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1118 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1119 1120 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1121 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1122 1123 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1124 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1125 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1126 1127 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1128 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1129 1130 /* IPSR10 */ 1131 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1132 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1133 1134 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1135 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1136 1137 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1138 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1139 1140 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1141 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1142 1143 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1144 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1145 1146 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1147 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1148 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1149 1150 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1151 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1152 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1153 1154 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1155 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1156 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1157 1158 /* IPSR11 */ 1159 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1160 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1161 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1162 1163 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1164 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1165 1166 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1167 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1168 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1169 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1170 1171 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1172 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1173 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1174 1175 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1176 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1177 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1178 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1179 1180 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1181 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1182 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1183 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1184 1185 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1186 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1187 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1188 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1189 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1190 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1191 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1192 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1193 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1194 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1195 1196 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1197 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1198 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1199 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1200 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1201 1202 /* IPSR12 */ 1203 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1204 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1205 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1206 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1207 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1208 1209 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1210 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1211 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1212 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1213 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1214 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1215 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1216 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1217 1218 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1219 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1220 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1221 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1222 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1223 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1224 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1225 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1226 1227 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1228 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1229 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1230 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1231 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1232 1233 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1234 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1235 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1236 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1237 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1238 1239 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1240 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1241 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1242 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1243 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1244 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1245 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1246 1247 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1248 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1249 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1250 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1251 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1252 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1253 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1254 1255 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1256 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1257 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1258 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1259 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1260 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1261 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1262 1263 /* IPSR13 */ 1264 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1265 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1266 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1267 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1268 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1269 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1270 1271 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1272 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1273 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1274 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1275 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1276 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1277 1278 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1279 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1280 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1281 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1282 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1283 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1284 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1285 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1286 1287 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1288 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1289 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1290 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1291 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1292 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1293 1294 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1295 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1296 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1297 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1298 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1299 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1300 1301 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1302 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1303 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1304 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1305 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1306 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1307 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1308 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1309 1310 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1311 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1312 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1313 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1314 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1315 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1316 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1317 1318 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1319 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1320 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1321 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1322 1323 /* IPSR14 */ 1324 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1325 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1326 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1327 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1328 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1329 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1330 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1331 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1332 1333 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1334 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1335 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1336 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1337 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1338 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1339 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1340 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1341 1342 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1343 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1344 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1345 1346 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1347 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1348 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1349 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1350 1351 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1352 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1353 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1354 1355 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1356 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1357 1358 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1359 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1360 1361 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1362 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1363 1364 /* IPSR15 */ 1365 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1366 1367 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1368 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1369 1370 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1371 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1372 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1373 1374 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1375 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1376 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1377 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1378 1379 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1380 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1381 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1382 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1383 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1384 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1385 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1386 1387 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1388 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1389 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1390 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1391 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1392 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1393 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1394 1395 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1396 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1397 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1398 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1399 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1400 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1401 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1402 1403 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1404 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1405 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1406 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1407 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1408 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1409 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1410 1411 /* IPSR16 */ 1412 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1413 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1414 1415 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1416 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1417 1418 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1419 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1420 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1421 1422 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1423 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1424 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1425 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1426 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1427 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1428 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1429 1430 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1431 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1432 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1433 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1434 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1435 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1436 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1437 1438 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1439 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1440 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1441 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1442 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1443 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1444 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1445 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1446 1447 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1448 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1449 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1450 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1451 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1452 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1453 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1454 1455 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1456 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1457 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1458 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1459 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1460 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1461 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1462 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1463 1464 /* IPSR17 */ 1465 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1466 1467 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1468 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1469 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1470 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1471 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1472 1473 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1474 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1475 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1476 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1477 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1478 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1479 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1480 1481 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1482 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1483 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1484 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1485 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1486 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1487 1488 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1489 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1490 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1491 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1492 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1493 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1494 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1495 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1496 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1497 1498 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1499 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1500 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1501 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1502 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1503 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1504 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1505 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1506 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1507 1508 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1509 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1510 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1511 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1512 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1513 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1514 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1515 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1516 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1517 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1518 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1519 1520 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1521 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1522 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1523 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1524 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1525 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1526 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1527 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1528 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1529 1530 /* IPSR18 */ 1531 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1532 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1533 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1534 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1535 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1536 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1537 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1538 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1539 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1540 1541 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1542 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1543 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1544 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1545 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1546 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1547 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1548 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1549 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1550 1551/* 1552 * Static pins can not be muxed between different functions but 1553 * still need mark entries in the pinmux list. Add each static 1554 * pin to the list without an associated function. The sh-pfc 1555 * core will do the right thing and skip trying to mux the pin 1556 * while still applying configuration to it. 1557 */ 1558#define FM(x) PINMUX_DATA(x##_MARK, 0), 1559 PINMUX_STATIC 1560#undef FM 1561}; 1562 1563/* 1564 * Pins not associated with a GPIO port. 1565 */ 1566enum { 1567 GP_ASSIGN_LAST(), 1568 NOGP_ALL(), 1569}; 1570 1571static const struct sh_pfc_pin pinmux_pins[] = { 1572 PINMUX_GPIO_GP_ALL(), 1573 PINMUX_NOGP_ALL(), 1574}; 1575 1576/* - AUDIO CLOCK ------------------------------------------------------------ */ 1577static const unsigned int audio_clk_a_a_pins[] = { 1578 /* CLK A */ 1579 RCAR_GP_PIN(6, 22), 1580}; 1581static const unsigned int audio_clk_a_a_mux[] = { 1582 AUDIO_CLKA_A_MARK, 1583}; 1584static const unsigned int audio_clk_a_b_pins[] = { 1585 /* CLK A */ 1586 RCAR_GP_PIN(5, 4), 1587}; 1588static const unsigned int audio_clk_a_b_mux[] = { 1589 AUDIO_CLKA_B_MARK, 1590}; 1591static const unsigned int audio_clk_a_c_pins[] = { 1592 /* CLK A */ 1593 RCAR_GP_PIN(5, 19), 1594}; 1595static const unsigned int audio_clk_a_c_mux[] = { 1596 AUDIO_CLKA_C_MARK, 1597}; 1598static const unsigned int audio_clk_b_a_pins[] = { 1599 /* CLK B */ 1600 RCAR_GP_PIN(5, 12), 1601}; 1602static const unsigned int audio_clk_b_a_mux[] = { 1603 AUDIO_CLKB_A_MARK, 1604}; 1605static const unsigned int audio_clk_b_b_pins[] = { 1606 /* CLK B */ 1607 RCAR_GP_PIN(6, 23), 1608}; 1609static const unsigned int audio_clk_b_b_mux[] = { 1610 AUDIO_CLKB_B_MARK, 1611}; 1612static const unsigned int audio_clk_c_a_pins[] = { 1613 /* CLK C */ 1614 RCAR_GP_PIN(5, 21), 1615}; 1616static const unsigned int audio_clk_c_a_mux[] = { 1617 AUDIO_CLKC_A_MARK, 1618}; 1619static const unsigned int audio_clk_c_b_pins[] = { 1620 /* CLK C */ 1621 RCAR_GP_PIN(5, 0), 1622}; 1623static const unsigned int audio_clk_c_b_mux[] = { 1624 AUDIO_CLKC_B_MARK, 1625}; 1626static const unsigned int audio_clkout_a_pins[] = { 1627 /* CLKOUT */ 1628 RCAR_GP_PIN(5, 18), 1629}; 1630static const unsigned int audio_clkout_a_mux[] = { 1631 AUDIO_CLKOUT_A_MARK, 1632}; 1633static const unsigned int audio_clkout_b_pins[] = { 1634 /* CLKOUT */ 1635 RCAR_GP_PIN(6, 28), 1636}; 1637static const unsigned int audio_clkout_b_mux[] = { 1638 AUDIO_CLKOUT_B_MARK, 1639}; 1640static const unsigned int audio_clkout_c_pins[] = { 1641 /* CLKOUT */ 1642 RCAR_GP_PIN(5, 3), 1643}; 1644static const unsigned int audio_clkout_c_mux[] = { 1645 AUDIO_CLKOUT_C_MARK, 1646}; 1647static const unsigned int audio_clkout_d_pins[] = { 1648 /* CLKOUT */ 1649 RCAR_GP_PIN(5, 21), 1650}; 1651static const unsigned int audio_clkout_d_mux[] = { 1652 AUDIO_CLKOUT_D_MARK, 1653}; 1654static const unsigned int audio_clkout1_a_pins[] = { 1655 /* CLKOUT1 */ 1656 RCAR_GP_PIN(5, 15), 1657}; 1658static const unsigned int audio_clkout1_a_mux[] = { 1659 AUDIO_CLKOUT1_A_MARK, 1660}; 1661static const unsigned int audio_clkout1_b_pins[] = { 1662 /* CLKOUT1 */ 1663 RCAR_GP_PIN(6, 29), 1664}; 1665static const unsigned int audio_clkout1_b_mux[] = { 1666 AUDIO_CLKOUT1_B_MARK, 1667}; 1668static const unsigned int audio_clkout2_a_pins[] = { 1669 /* CLKOUT2 */ 1670 RCAR_GP_PIN(5, 16), 1671}; 1672static const unsigned int audio_clkout2_a_mux[] = { 1673 AUDIO_CLKOUT2_A_MARK, 1674}; 1675static const unsigned int audio_clkout2_b_pins[] = { 1676 /* CLKOUT2 */ 1677 RCAR_GP_PIN(6, 30), 1678}; 1679static const unsigned int audio_clkout2_b_mux[] = { 1680 AUDIO_CLKOUT2_B_MARK, 1681}; 1682 1683static const unsigned int audio_clkout3_a_pins[] = { 1684 /* CLKOUT3 */ 1685 RCAR_GP_PIN(5, 19), 1686}; 1687static const unsigned int audio_clkout3_a_mux[] = { 1688 AUDIO_CLKOUT3_A_MARK, 1689}; 1690static const unsigned int audio_clkout3_b_pins[] = { 1691 /* CLKOUT3 */ 1692 RCAR_GP_PIN(6, 31), 1693}; 1694static const unsigned int audio_clkout3_b_mux[] = { 1695 AUDIO_CLKOUT3_B_MARK, 1696}; 1697 1698/* - EtherAVB --------------------------------------------------------------- */ 1699static const unsigned int avb_link_pins[] = { 1700 /* AVB_LINK */ 1701 RCAR_GP_PIN(2, 12), 1702}; 1703static const unsigned int avb_link_mux[] = { 1704 AVB_LINK_MARK, 1705}; 1706static const unsigned int avb_magic_pins[] = { 1707 /* AVB_MAGIC_ */ 1708 RCAR_GP_PIN(2, 10), 1709}; 1710static const unsigned int avb_magic_mux[] = { 1711 AVB_MAGIC_MARK, 1712}; 1713static const unsigned int avb_phy_int_pins[] = { 1714 /* AVB_PHY_INT */ 1715 RCAR_GP_PIN(2, 11), 1716}; 1717static const unsigned int avb_phy_int_mux[] = { 1718 AVB_PHY_INT_MARK, 1719}; 1720static const unsigned int avb_mdio_pins[] = { 1721 /* AVB_MDC, AVB_MDIO */ 1722 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1723}; 1724static const unsigned int avb_mdio_mux[] = { 1725 AVB_MDC_MARK, AVB_MDIO_MARK, 1726}; 1727static const unsigned int avb_mii_pins[] = { 1728 /* 1729 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1730 * AVB_TD1, AVB_TD2, AVB_TD3, 1731 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1732 * AVB_RD1, AVB_RD2, AVB_RD3, 1733 * AVB_TXCREFCLK 1734 */ 1735 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1736 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1737 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1738 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1739 PIN_AVB_TXCREFCLK, 1740}; 1741static const unsigned int avb_mii_mux[] = { 1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1746 AVB_TXCREFCLK_MARK, 1747}; 1748static const unsigned int avb_avtp_pps_pins[] = { 1749 /* AVB_AVTP_PPS */ 1750 RCAR_GP_PIN(2, 6), 1751}; 1752static const unsigned int avb_avtp_pps_mux[] = { 1753 AVB_AVTP_PPS_MARK, 1754}; 1755static const unsigned int avb_avtp_match_a_pins[] = { 1756 /* AVB_AVTP_MATCH_A */ 1757 RCAR_GP_PIN(2, 13), 1758}; 1759static const unsigned int avb_avtp_match_a_mux[] = { 1760 AVB_AVTP_MATCH_A_MARK, 1761}; 1762static const unsigned int avb_avtp_capture_a_pins[] = { 1763 /* AVB_AVTP_CAPTURE_A */ 1764 RCAR_GP_PIN(2, 14), 1765}; 1766static const unsigned int avb_avtp_capture_a_mux[] = { 1767 AVB_AVTP_CAPTURE_A_MARK, 1768}; 1769static const unsigned int avb_avtp_match_b_pins[] = { 1770 /* AVB_AVTP_MATCH_B */ 1771 RCAR_GP_PIN(1, 8), 1772}; 1773static const unsigned int avb_avtp_match_b_mux[] = { 1774 AVB_AVTP_MATCH_B_MARK, 1775}; 1776static const unsigned int avb_avtp_capture_b_pins[] = { 1777 /* AVB_AVTP_CAPTURE_B */ 1778 RCAR_GP_PIN(1, 11), 1779}; 1780static const unsigned int avb_avtp_capture_b_mux[] = { 1781 AVB_AVTP_CAPTURE_B_MARK, 1782}; 1783 1784/* - CAN ------------------------------------------------------------------ */ 1785static const unsigned int can0_data_a_pins[] = { 1786 /* TX, RX */ 1787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1788}; 1789 1790static const unsigned int can0_data_a_mux[] = { 1791 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1792}; 1793 1794static const unsigned int can0_data_b_pins[] = { 1795 /* TX, RX */ 1796 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1797}; 1798 1799static const unsigned int can0_data_b_mux[] = { 1800 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1801}; 1802 1803static const unsigned int can1_data_pins[] = { 1804 /* TX, RX */ 1805 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1806}; 1807 1808static const unsigned int can1_data_mux[] = { 1809 CAN1_TX_MARK, CAN1_RX_MARK, 1810}; 1811 1812/* - CAN Clock -------------------------------------------------------------- */ 1813static const unsigned int can_clk_pins[] = { 1814 /* CLK */ 1815 RCAR_GP_PIN(1, 25), 1816}; 1817 1818static const unsigned int can_clk_mux[] = { 1819 CAN_CLK_MARK, 1820}; 1821 1822/* - CAN FD --------------------------------------------------------------- */ 1823static const unsigned int canfd0_data_a_pins[] = { 1824 /* TX, RX */ 1825 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1826}; 1827 1828static const unsigned int canfd0_data_a_mux[] = { 1829 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1830}; 1831 1832static const unsigned int canfd0_data_b_pins[] = { 1833 /* TX, RX */ 1834 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1835}; 1836 1837static const unsigned int canfd0_data_b_mux[] = { 1838 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1839}; 1840 1841static const unsigned int canfd1_data_pins[] = { 1842 /* TX, RX */ 1843 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1844}; 1845 1846static const unsigned int canfd1_data_mux[] = { 1847 CANFD1_TX_MARK, CANFD1_RX_MARK, 1848}; 1849 1850#ifdef CONFIG_PINCTRL_PFC_R8A77965 1851/* - DRIF0 --------------------------------------------------------------- */ 1852static const unsigned int drif0_ctrl_a_pins[] = { 1853 /* CLK, SYNC */ 1854 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1855}; 1856 1857static const unsigned int drif0_ctrl_a_mux[] = { 1858 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1859}; 1860 1861static const unsigned int drif0_data0_a_pins[] = { 1862 /* D0 */ 1863 RCAR_GP_PIN(6, 10), 1864}; 1865 1866static const unsigned int drif0_data0_a_mux[] = { 1867 RIF0_D0_A_MARK, 1868}; 1869 1870static const unsigned int drif0_data1_a_pins[] = { 1871 /* D1 */ 1872 RCAR_GP_PIN(6, 7), 1873}; 1874 1875static const unsigned int drif0_data1_a_mux[] = { 1876 RIF0_D1_A_MARK, 1877}; 1878 1879static const unsigned int drif0_ctrl_b_pins[] = { 1880 /* CLK, SYNC */ 1881 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1882}; 1883 1884static const unsigned int drif0_ctrl_b_mux[] = { 1885 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1886}; 1887 1888static const unsigned int drif0_data0_b_pins[] = { 1889 /* D0 */ 1890 RCAR_GP_PIN(5, 1), 1891}; 1892 1893static const unsigned int drif0_data0_b_mux[] = { 1894 RIF0_D0_B_MARK, 1895}; 1896 1897static const unsigned int drif0_data1_b_pins[] = { 1898 /* D1 */ 1899 RCAR_GP_PIN(5, 2), 1900}; 1901 1902static const unsigned int drif0_data1_b_mux[] = { 1903 RIF0_D1_B_MARK, 1904}; 1905 1906static const unsigned int drif0_ctrl_c_pins[] = { 1907 /* CLK, SYNC */ 1908 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1909}; 1910 1911static const unsigned int drif0_ctrl_c_mux[] = { 1912 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1913}; 1914 1915static const unsigned int drif0_data0_c_pins[] = { 1916 /* D0 */ 1917 RCAR_GP_PIN(5, 13), 1918}; 1919 1920static const unsigned int drif0_data0_c_mux[] = { 1921 RIF0_D0_C_MARK, 1922}; 1923 1924static const unsigned int drif0_data1_c_pins[] = { 1925 /* D1 */ 1926 RCAR_GP_PIN(5, 14), 1927}; 1928 1929static const unsigned int drif0_data1_c_mux[] = { 1930 RIF0_D1_C_MARK, 1931}; 1932 1933/* - DRIF1 --------------------------------------------------------------- */ 1934static const unsigned int drif1_ctrl_a_pins[] = { 1935 /* CLK, SYNC */ 1936 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1937}; 1938 1939static const unsigned int drif1_ctrl_a_mux[] = { 1940 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1941}; 1942 1943static const unsigned int drif1_data0_a_pins[] = { 1944 /* D0 */ 1945 RCAR_GP_PIN(6, 19), 1946}; 1947 1948static const unsigned int drif1_data0_a_mux[] = { 1949 RIF1_D0_A_MARK, 1950}; 1951 1952static const unsigned int drif1_data1_a_pins[] = { 1953 /* D1 */ 1954 RCAR_GP_PIN(6, 20), 1955}; 1956 1957static const unsigned int drif1_data1_a_mux[] = { 1958 RIF1_D1_A_MARK, 1959}; 1960 1961static const unsigned int drif1_ctrl_b_pins[] = { 1962 /* CLK, SYNC */ 1963 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1964}; 1965 1966static const unsigned int drif1_ctrl_b_mux[] = { 1967 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1968}; 1969 1970static const unsigned int drif1_data0_b_pins[] = { 1971 /* D0 */ 1972 RCAR_GP_PIN(5, 7), 1973}; 1974 1975static const unsigned int drif1_data0_b_mux[] = { 1976 RIF1_D0_B_MARK, 1977}; 1978 1979static const unsigned int drif1_data1_b_pins[] = { 1980 /* D1 */ 1981 RCAR_GP_PIN(5, 8), 1982}; 1983 1984static const unsigned int drif1_data1_b_mux[] = { 1985 RIF1_D1_B_MARK, 1986}; 1987 1988static const unsigned int drif1_ctrl_c_pins[] = { 1989 /* CLK, SYNC */ 1990 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1991}; 1992 1993static const unsigned int drif1_ctrl_c_mux[] = { 1994 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1995}; 1996 1997static const unsigned int drif1_data0_c_pins[] = { 1998 /* D0 */ 1999 RCAR_GP_PIN(5, 6), 2000}; 2001 2002static const unsigned int drif1_data0_c_mux[] = { 2003 RIF1_D0_C_MARK, 2004}; 2005 2006static const unsigned int drif1_data1_c_pins[] = { 2007 /* D1 */ 2008 RCAR_GP_PIN(5, 10), 2009}; 2010 2011static const unsigned int drif1_data1_c_mux[] = { 2012 RIF1_D1_C_MARK, 2013}; 2014 2015/* - DRIF2 --------------------------------------------------------------- */ 2016static const unsigned int drif2_ctrl_a_pins[] = { 2017 /* CLK, SYNC */ 2018 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2019}; 2020 2021static const unsigned int drif2_ctrl_a_mux[] = { 2022 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 2023}; 2024 2025static const unsigned int drif2_data0_a_pins[] = { 2026 /* D0 */ 2027 RCAR_GP_PIN(6, 7), 2028}; 2029 2030static const unsigned int drif2_data0_a_mux[] = { 2031 RIF2_D0_A_MARK, 2032}; 2033 2034static const unsigned int drif2_data1_a_pins[] = { 2035 /* D1 */ 2036 RCAR_GP_PIN(6, 10), 2037}; 2038 2039static const unsigned int drif2_data1_a_mux[] = { 2040 RIF2_D1_A_MARK, 2041}; 2042 2043static const unsigned int drif2_ctrl_b_pins[] = { 2044 /* CLK, SYNC */ 2045 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 2046}; 2047 2048static const unsigned int drif2_ctrl_b_mux[] = { 2049 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 2050}; 2051 2052static const unsigned int drif2_data0_b_pins[] = { 2053 /* D0 */ 2054 RCAR_GP_PIN(6, 30), 2055}; 2056 2057static const unsigned int drif2_data0_b_mux[] = { 2058 RIF2_D0_B_MARK, 2059}; 2060 2061static const unsigned int drif2_data1_b_pins[] = { 2062 /* D1 */ 2063 RCAR_GP_PIN(6, 31), 2064}; 2065 2066static const unsigned int drif2_data1_b_mux[] = { 2067 RIF2_D1_B_MARK, 2068}; 2069 2070/* - DRIF3 --------------------------------------------------------------- */ 2071static const unsigned int drif3_ctrl_a_pins[] = { 2072 /* CLK, SYNC */ 2073 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2074}; 2075 2076static const unsigned int drif3_ctrl_a_mux[] = { 2077 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2078}; 2079 2080static const unsigned int drif3_data0_a_pins[] = { 2081 /* D0 */ 2082 RCAR_GP_PIN(6, 19), 2083}; 2084 2085static const unsigned int drif3_data0_a_mux[] = { 2086 RIF3_D0_A_MARK, 2087}; 2088 2089static const unsigned int drif3_data1_a_pins[] = { 2090 /* D1 */ 2091 RCAR_GP_PIN(6, 20), 2092}; 2093 2094static const unsigned int drif3_data1_a_mux[] = { 2095 RIF3_D1_A_MARK, 2096}; 2097 2098static const unsigned int drif3_ctrl_b_pins[] = { 2099 /* CLK, SYNC */ 2100 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2101}; 2102 2103static const unsigned int drif3_ctrl_b_mux[] = { 2104 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2105}; 2106 2107static const unsigned int drif3_data0_b_pins[] = { 2108 /* D0 */ 2109 RCAR_GP_PIN(6, 28), 2110}; 2111 2112static const unsigned int drif3_data0_b_mux[] = { 2113 RIF3_D0_B_MARK, 2114}; 2115 2116static const unsigned int drif3_data1_b_pins[] = { 2117 /* D1 */ 2118 RCAR_GP_PIN(6, 29), 2119}; 2120 2121static const unsigned int drif3_data1_b_mux[] = { 2122 RIF3_D1_B_MARK, 2123}; 2124#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 2125 2126/* - DU --------------------------------------------------------------------- */ 2127static const unsigned int du_rgb666_pins[] = { 2128 /* R[7:2], G[7:2], B[7:2] */ 2129 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2130 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2131 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2132 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2133 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2134 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2135}; 2136 2137static const unsigned int du_rgb666_mux[] = { 2138 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2139 DU_DR3_MARK, DU_DR2_MARK, 2140 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2141 DU_DG3_MARK, DU_DG2_MARK, 2142 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2143 DU_DB3_MARK, DU_DB2_MARK, 2144}; 2145 2146static const unsigned int du_rgb888_pins[] = { 2147 /* R[7:0], G[7:0], B[7:0] */ 2148 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2149 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2150 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2151 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2152 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2153 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2154 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2155 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2156 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2157}; 2158 2159static const unsigned int du_rgb888_mux[] = { 2160 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2161 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2162 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2163 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2164 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2165 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2166}; 2167 2168static const unsigned int du_clk_out_0_pins[] = { 2169 /* CLKOUT */ 2170 RCAR_GP_PIN(1, 27), 2171}; 2172 2173static const unsigned int du_clk_out_0_mux[] = { 2174 DU_DOTCLKOUT0_MARK 2175}; 2176 2177static const unsigned int du_clk_out_1_pins[] = { 2178 /* CLKOUT */ 2179 RCAR_GP_PIN(2, 3), 2180}; 2181 2182static const unsigned int du_clk_out_1_mux[] = { 2183 DU_DOTCLKOUT1_MARK 2184}; 2185 2186static const unsigned int du_sync_pins[] = { 2187 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2188 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2189}; 2190 2191static const unsigned int du_sync_mux[] = { 2192 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2193}; 2194 2195static const unsigned int du_oddf_pins[] = { 2196 /* EXDISP/EXODDF/EXCDE */ 2197 RCAR_GP_PIN(2, 2), 2198}; 2199 2200static const unsigned int du_oddf_mux[] = { 2201 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2202}; 2203 2204static const unsigned int du_cde_pins[] = { 2205 /* CDE */ 2206 RCAR_GP_PIN(2, 0), 2207}; 2208 2209static const unsigned int du_cde_mux[] = { 2210 DU_CDE_MARK, 2211}; 2212 2213static const unsigned int du_disp_pins[] = { 2214 /* DISP */ 2215 RCAR_GP_PIN(2, 1), 2216}; 2217 2218static const unsigned int du_disp_mux[] = { 2219 DU_DISP_MARK, 2220}; 2221 2222/* - HSCIF0 ----------------------------------------------------------------- */ 2223static const unsigned int hscif0_data_pins[] = { 2224 /* RX, TX */ 2225 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2226}; 2227 2228static const unsigned int hscif0_data_mux[] = { 2229 HRX0_MARK, HTX0_MARK, 2230}; 2231 2232static const unsigned int hscif0_clk_pins[] = { 2233 /* SCK */ 2234 RCAR_GP_PIN(5, 12), 2235}; 2236 2237static const unsigned int hscif0_clk_mux[] = { 2238 HSCK0_MARK, 2239}; 2240 2241static const unsigned int hscif0_ctrl_pins[] = { 2242 /* RTS, CTS */ 2243 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2244}; 2245 2246static const unsigned int hscif0_ctrl_mux[] = { 2247 HRTS0_N_MARK, HCTS0_N_MARK, 2248}; 2249 2250/* - HSCIF1 ----------------------------------------------------------------- */ 2251static const unsigned int hscif1_data_a_pins[] = { 2252 /* RX, TX */ 2253 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2254}; 2255 2256static const unsigned int hscif1_data_a_mux[] = { 2257 HRX1_A_MARK, HTX1_A_MARK, 2258}; 2259 2260static const unsigned int hscif1_clk_a_pins[] = { 2261 /* SCK */ 2262 RCAR_GP_PIN(6, 21), 2263}; 2264 2265static const unsigned int hscif1_clk_a_mux[] = { 2266 HSCK1_A_MARK, 2267}; 2268 2269static const unsigned int hscif1_ctrl_a_pins[] = { 2270 /* RTS, CTS */ 2271 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2272}; 2273 2274static const unsigned int hscif1_ctrl_a_mux[] = { 2275 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2276}; 2277 2278static const unsigned int hscif1_data_b_pins[] = { 2279 /* RX, TX */ 2280 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2281}; 2282 2283static const unsigned int hscif1_data_b_mux[] = { 2284 HRX1_B_MARK, HTX1_B_MARK, 2285}; 2286 2287static const unsigned int hscif1_clk_b_pins[] = { 2288 /* SCK */ 2289 RCAR_GP_PIN(5, 0), 2290}; 2291 2292static const unsigned int hscif1_clk_b_mux[] = { 2293 HSCK1_B_MARK, 2294}; 2295 2296static const unsigned int hscif1_ctrl_b_pins[] = { 2297 /* RTS, CTS */ 2298 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2299}; 2300 2301static const unsigned int hscif1_ctrl_b_mux[] = { 2302 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2303}; 2304 2305/* - HSCIF2 ----------------------------------------------------------------- */ 2306static const unsigned int hscif2_data_a_pins[] = { 2307 /* RX, TX */ 2308 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2309}; 2310 2311static const unsigned int hscif2_data_a_mux[] = { 2312 HRX2_A_MARK, HTX2_A_MARK, 2313}; 2314 2315static const unsigned int hscif2_clk_a_pins[] = { 2316 /* SCK */ 2317 RCAR_GP_PIN(6, 10), 2318}; 2319 2320static const unsigned int hscif2_clk_a_mux[] = { 2321 HSCK2_A_MARK, 2322}; 2323 2324static const unsigned int hscif2_ctrl_a_pins[] = { 2325 /* RTS, CTS */ 2326 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2327}; 2328 2329static const unsigned int hscif2_ctrl_a_mux[] = { 2330 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2331}; 2332 2333static const unsigned int hscif2_data_b_pins[] = { 2334 /* RX, TX */ 2335 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2336}; 2337 2338static const unsigned int hscif2_data_b_mux[] = { 2339 HRX2_B_MARK, HTX2_B_MARK, 2340}; 2341 2342static const unsigned int hscif2_clk_b_pins[] = { 2343 /* SCK */ 2344 RCAR_GP_PIN(6, 21), 2345}; 2346 2347static const unsigned int hscif2_clk_b_mux[] = { 2348 HSCK2_B_MARK, 2349}; 2350 2351static const unsigned int hscif2_ctrl_b_pins[] = { 2352 /* RTS, CTS */ 2353 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2354}; 2355 2356static const unsigned int hscif2_ctrl_b_mux[] = { 2357 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2358}; 2359 2360static const unsigned int hscif2_data_c_pins[] = { 2361 /* RX, TX */ 2362 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2363}; 2364 2365static const unsigned int hscif2_data_c_mux[] = { 2366 HRX2_C_MARK, HTX2_C_MARK, 2367}; 2368 2369static const unsigned int hscif2_clk_c_pins[] = { 2370 /* SCK */ 2371 RCAR_GP_PIN(6, 24), 2372}; 2373 2374static const unsigned int hscif2_clk_c_mux[] = { 2375 HSCK2_C_MARK, 2376}; 2377 2378static const unsigned int hscif2_ctrl_c_pins[] = { 2379 /* RTS, CTS */ 2380 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2381}; 2382 2383static const unsigned int hscif2_ctrl_c_mux[] = { 2384 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2385}; 2386 2387/* - HSCIF3 ----------------------------------------------------------------- */ 2388static const unsigned int hscif3_data_a_pins[] = { 2389 /* RX, TX */ 2390 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2391}; 2392 2393static const unsigned int hscif3_data_a_mux[] = { 2394 HRX3_A_MARK, HTX3_A_MARK, 2395}; 2396 2397static const unsigned int hscif3_clk_pins[] = { 2398 /* SCK */ 2399 RCAR_GP_PIN(1, 22), 2400}; 2401 2402static const unsigned int hscif3_clk_mux[] = { 2403 HSCK3_MARK, 2404}; 2405 2406static const unsigned int hscif3_ctrl_pins[] = { 2407 /* RTS, CTS */ 2408 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2409}; 2410 2411static const unsigned int hscif3_ctrl_mux[] = { 2412 HRTS3_N_MARK, HCTS3_N_MARK, 2413}; 2414 2415static const unsigned int hscif3_data_b_pins[] = { 2416 /* RX, TX */ 2417 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2418}; 2419 2420static const unsigned int hscif3_data_b_mux[] = { 2421 HRX3_B_MARK, HTX3_B_MARK, 2422}; 2423 2424static const unsigned int hscif3_data_c_pins[] = { 2425 /* RX, TX */ 2426 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2427}; 2428 2429static const unsigned int hscif3_data_c_mux[] = { 2430 HRX3_C_MARK, HTX3_C_MARK, 2431}; 2432 2433static const unsigned int hscif3_data_d_pins[] = { 2434 /* RX, TX */ 2435 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2436}; 2437 2438static const unsigned int hscif3_data_d_mux[] = { 2439 HRX3_D_MARK, HTX3_D_MARK, 2440}; 2441 2442/* - HSCIF4 ----------------------------------------------------------------- */ 2443static const unsigned int hscif4_data_a_pins[] = { 2444 /* RX, TX */ 2445 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2446}; 2447 2448static const unsigned int hscif4_data_a_mux[] = { 2449 HRX4_A_MARK, HTX4_A_MARK, 2450}; 2451 2452static const unsigned int hscif4_clk_pins[] = { 2453 /* SCK */ 2454 RCAR_GP_PIN(1, 11), 2455}; 2456 2457static const unsigned int hscif4_clk_mux[] = { 2458 HSCK4_MARK, 2459}; 2460 2461static const unsigned int hscif4_ctrl_pins[] = { 2462 /* RTS, CTS */ 2463 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2464}; 2465 2466static const unsigned int hscif4_ctrl_mux[] = { 2467 HRTS4_N_MARK, HCTS4_N_MARK, 2468}; 2469 2470static const unsigned int hscif4_data_b_pins[] = { 2471 /* RX, TX */ 2472 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2473}; 2474 2475static const unsigned int hscif4_data_b_mux[] = { 2476 HRX4_B_MARK, HTX4_B_MARK, 2477}; 2478 2479/* - I2C -------------------------------------------------------------------- */ 2480static const unsigned int i2c0_pins[] = { 2481 /* SCL, SDA */ 2482 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2483}; 2484 2485static const unsigned int i2c0_mux[] = { 2486 SCL0_MARK, SDA0_MARK, 2487}; 2488 2489static const unsigned int i2c1_a_pins[] = { 2490 /* SDA, SCL */ 2491 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2492}; 2493 2494static const unsigned int i2c1_a_mux[] = { 2495 SDA1_A_MARK, SCL1_A_MARK, 2496}; 2497 2498static const unsigned int i2c1_b_pins[] = { 2499 /* SDA, SCL */ 2500 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2501}; 2502 2503static const unsigned int i2c1_b_mux[] = { 2504 SDA1_B_MARK, SCL1_B_MARK, 2505}; 2506 2507static const unsigned int i2c2_a_pins[] = { 2508 /* SDA, SCL */ 2509 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2510}; 2511 2512static const unsigned int i2c2_a_mux[] = { 2513 SDA2_A_MARK, SCL2_A_MARK, 2514}; 2515 2516static const unsigned int i2c2_b_pins[] = { 2517 /* SDA, SCL */ 2518 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2519}; 2520 2521static const unsigned int i2c2_b_mux[] = { 2522 SDA2_B_MARK, SCL2_B_MARK, 2523}; 2524 2525static const unsigned int i2c3_pins[] = { 2526 /* SCL, SDA */ 2527 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2528}; 2529 2530static const unsigned int i2c3_mux[] = { 2531 SCL3_MARK, SDA3_MARK, 2532}; 2533 2534static const unsigned int i2c5_pins[] = { 2535 /* SCL, SDA */ 2536 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2537}; 2538 2539static const unsigned int i2c5_mux[] = { 2540 SCL5_MARK, SDA5_MARK, 2541}; 2542 2543static const unsigned int i2c6_a_pins[] = { 2544 /* SDA, SCL */ 2545 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2546}; 2547 2548static const unsigned int i2c6_a_mux[] = { 2549 SDA6_A_MARK, SCL6_A_MARK, 2550}; 2551 2552static const unsigned int i2c6_b_pins[] = { 2553 /* SDA, SCL */ 2554 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2555}; 2556 2557static const unsigned int i2c6_b_mux[] = { 2558 SDA6_B_MARK, SCL6_B_MARK, 2559}; 2560 2561static const unsigned int i2c6_c_pins[] = { 2562 /* SDA, SCL */ 2563 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2564}; 2565 2566static const unsigned int i2c6_c_mux[] = { 2567 SDA6_C_MARK, SCL6_C_MARK, 2568}; 2569 2570/* - INTC-EX ---------------------------------------------------------------- */ 2571static const unsigned int intc_ex_irq0_pins[] = { 2572 /* IRQ0 */ 2573 RCAR_GP_PIN(2, 0), 2574}; 2575static const unsigned int intc_ex_irq0_mux[] = { 2576 IRQ0_MARK, 2577}; 2578static const unsigned int intc_ex_irq1_pins[] = { 2579 /* IRQ1 */ 2580 RCAR_GP_PIN(2, 1), 2581}; 2582static const unsigned int intc_ex_irq1_mux[] = { 2583 IRQ1_MARK, 2584}; 2585static const unsigned int intc_ex_irq2_pins[] = { 2586 /* IRQ2 */ 2587 RCAR_GP_PIN(2, 2), 2588}; 2589static const unsigned int intc_ex_irq2_mux[] = { 2590 IRQ2_MARK, 2591}; 2592static const unsigned int intc_ex_irq3_pins[] = { 2593 /* IRQ3 */ 2594 RCAR_GP_PIN(2, 3), 2595}; 2596static const unsigned int intc_ex_irq3_mux[] = { 2597 IRQ3_MARK, 2598}; 2599static const unsigned int intc_ex_irq4_pins[] = { 2600 /* IRQ4 */ 2601 RCAR_GP_PIN(2, 4), 2602}; 2603static const unsigned int intc_ex_irq4_mux[] = { 2604 IRQ4_MARK, 2605}; 2606static const unsigned int intc_ex_irq5_pins[] = { 2607 /* IRQ5 */ 2608 RCAR_GP_PIN(2, 5), 2609}; 2610static const unsigned int intc_ex_irq5_mux[] = { 2611 IRQ5_MARK, 2612}; 2613 2614#ifdef CONFIG_PINCTRL_PFC_R8A77965 2615/* - MLB+ ------------------------------------------------------------------- */ 2616static const unsigned int mlb_3pin_pins[] = { 2617 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 2618}; 2619static const unsigned int mlb_3pin_mux[] = { 2620 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2621}; 2622#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 2623 2624/* - MSIOF0 ----------------------------------------------------------------- */ 2625static const unsigned int msiof0_clk_pins[] = { 2626 /* SCK */ 2627 RCAR_GP_PIN(5, 17), 2628}; 2629static const unsigned int msiof0_clk_mux[] = { 2630 MSIOF0_SCK_MARK, 2631}; 2632static const unsigned int msiof0_sync_pins[] = { 2633 /* SYNC */ 2634 RCAR_GP_PIN(5, 18), 2635}; 2636static const unsigned int msiof0_sync_mux[] = { 2637 MSIOF0_SYNC_MARK, 2638}; 2639static const unsigned int msiof0_ss1_pins[] = { 2640 /* SS1 */ 2641 RCAR_GP_PIN(5, 19), 2642}; 2643static const unsigned int msiof0_ss1_mux[] = { 2644 MSIOF0_SS1_MARK, 2645}; 2646static const unsigned int msiof0_ss2_pins[] = { 2647 /* SS2 */ 2648 RCAR_GP_PIN(5, 21), 2649}; 2650static const unsigned int msiof0_ss2_mux[] = { 2651 MSIOF0_SS2_MARK, 2652}; 2653static const unsigned int msiof0_txd_pins[] = { 2654 /* TXD */ 2655 RCAR_GP_PIN(5, 20), 2656}; 2657static const unsigned int msiof0_txd_mux[] = { 2658 MSIOF0_TXD_MARK, 2659}; 2660static const unsigned int msiof0_rxd_pins[] = { 2661 /* RXD */ 2662 RCAR_GP_PIN(5, 22), 2663}; 2664static const unsigned int msiof0_rxd_mux[] = { 2665 MSIOF0_RXD_MARK, 2666}; 2667/* - MSIOF1 ----------------------------------------------------------------- */ 2668static const unsigned int msiof1_clk_a_pins[] = { 2669 /* SCK */ 2670 RCAR_GP_PIN(6, 8), 2671}; 2672static const unsigned int msiof1_clk_a_mux[] = { 2673 MSIOF1_SCK_A_MARK, 2674}; 2675static const unsigned int msiof1_sync_a_pins[] = { 2676 /* SYNC */ 2677 RCAR_GP_PIN(6, 9), 2678}; 2679static const unsigned int msiof1_sync_a_mux[] = { 2680 MSIOF1_SYNC_A_MARK, 2681}; 2682static const unsigned int msiof1_ss1_a_pins[] = { 2683 /* SS1 */ 2684 RCAR_GP_PIN(6, 5), 2685}; 2686static const unsigned int msiof1_ss1_a_mux[] = { 2687 MSIOF1_SS1_A_MARK, 2688}; 2689static const unsigned int msiof1_ss2_a_pins[] = { 2690 /* SS2 */ 2691 RCAR_GP_PIN(6, 6), 2692}; 2693static const unsigned int msiof1_ss2_a_mux[] = { 2694 MSIOF1_SS2_A_MARK, 2695}; 2696static const unsigned int msiof1_txd_a_pins[] = { 2697 /* TXD */ 2698 RCAR_GP_PIN(6, 7), 2699}; 2700static const unsigned int msiof1_txd_a_mux[] = { 2701 MSIOF1_TXD_A_MARK, 2702}; 2703static const unsigned int msiof1_rxd_a_pins[] = { 2704 /* RXD */ 2705 RCAR_GP_PIN(6, 10), 2706}; 2707static const unsigned int msiof1_rxd_a_mux[] = { 2708 MSIOF1_RXD_A_MARK, 2709}; 2710static const unsigned int msiof1_clk_b_pins[] = { 2711 /* SCK */ 2712 RCAR_GP_PIN(5, 9), 2713}; 2714static const unsigned int msiof1_clk_b_mux[] = { 2715 MSIOF1_SCK_B_MARK, 2716}; 2717static const unsigned int msiof1_sync_b_pins[] = { 2718 /* SYNC */ 2719 RCAR_GP_PIN(5, 3), 2720}; 2721static const unsigned int msiof1_sync_b_mux[] = { 2722 MSIOF1_SYNC_B_MARK, 2723}; 2724static const unsigned int msiof1_ss1_b_pins[] = { 2725 /* SS1 */ 2726 RCAR_GP_PIN(5, 4), 2727}; 2728static const unsigned int msiof1_ss1_b_mux[] = { 2729 MSIOF1_SS1_B_MARK, 2730}; 2731static const unsigned int msiof1_ss2_b_pins[] = { 2732 /* SS2 */ 2733 RCAR_GP_PIN(5, 0), 2734}; 2735static const unsigned int msiof1_ss2_b_mux[] = { 2736 MSIOF1_SS2_B_MARK, 2737}; 2738static const unsigned int msiof1_txd_b_pins[] = { 2739 /* TXD */ 2740 RCAR_GP_PIN(5, 8), 2741}; 2742static const unsigned int msiof1_txd_b_mux[] = { 2743 MSIOF1_TXD_B_MARK, 2744}; 2745static const unsigned int msiof1_rxd_b_pins[] = { 2746 /* RXD */ 2747 RCAR_GP_PIN(5, 7), 2748}; 2749static const unsigned int msiof1_rxd_b_mux[] = { 2750 MSIOF1_RXD_B_MARK, 2751}; 2752static const unsigned int msiof1_clk_c_pins[] = { 2753 /* SCK */ 2754 RCAR_GP_PIN(6, 17), 2755}; 2756static const unsigned int msiof1_clk_c_mux[] = { 2757 MSIOF1_SCK_C_MARK, 2758}; 2759static const unsigned int msiof1_sync_c_pins[] = { 2760 /* SYNC */ 2761 RCAR_GP_PIN(6, 18), 2762}; 2763static const unsigned int msiof1_sync_c_mux[] = { 2764 MSIOF1_SYNC_C_MARK, 2765}; 2766static const unsigned int msiof1_ss1_c_pins[] = { 2767 /* SS1 */ 2768 RCAR_GP_PIN(6, 21), 2769}; 2770static const unsigned int msiof1_ss1_c_mux[] = { 2771 MSIOF1_SS1_C_MARK, 2772}; 2773static const unsigned int msiof1_ss2_c_pins[] = { 2774 /* SS2 */ 2775 RCAR_GP_PIN(6, 27), 2776}; 2777static const unsigned int msiof1_ss2_c_mux[] = { 2778 MSIOF1_SS2_C_MARK, 2779}; 2780static const unsigned int msiof1_txd_c_pins[] = { 2781 /* TXD */ 2782 RCAR_GP_PIN(6, 20), 2783}; 2784static const unsigned int msiof1_txd_c_mux[] = { 2785 MSIOF1_TXD_C_MARK, 2786}; 2787static const unsigned int msiof1_rxd_c_pins[] = { 2788 /* RXD */ 2789 RCAR_GP_PIN(6, 19), 2790}; 2791static const unsigned int msiof1_rxd_c_mux[] = { 2792 MSIOF1_RXD_C_MARK, 2793}; 2794static const unsigned int msiof1_clk_d_pins[] = { 2795 /* SCK */ 2796 RCAR_GP_PIN(5, 12), 2797}; 2798static const unsigned int msiof1_clk_d_mux[] = { 2799 MSIOF1_SCK_D_MARK, 2800}; 2801static const unsigned int msiof1_sync_d_pins[] = { 2802 /* SYNC */ 2803 RCAR_GP_PIN(5, 15), 2804}; 2805static const unsigned int msiof1_sync_d_mux[] = { 2806 MSIOF1_SYNC_D_MARK, 2807}; 2808static const unsigned int msiof1_ss1_d_pins[] = { 2809 /* SS1 */ 2810 RCAR_GP_PIN(5, 16), 2811}; 2812static const unsigned int msiof1_ss1_d_mux[] = { 2813 MSIOF1_SS1_D_MARK, 2814}; 2815static const unsigned int msiof1_ss2_d_pins[] = { 2816 /* SS2 */ 2817 RCAR_GP_PIN(5, 21), 2818}; 2819static const unsigned int msiof1_ss2_d_mux[] = { 2820 MSIOF1_SS2_D_MARK, 2821}; 2822static const unsigned int msiof1_txd_d_pins[] = { 2823 /* TXD */ 2824 RCAR_GP_PIN(5, 14), 2825}; 2826static const unsigned int msiof1_txd_d_mux[] = { 2827 MSIOF1_TXD_D_MARK, 2828}; 2829static const unsigned int msiof1_rxd_d_pins[] = { 2830 /* RXD */ 2831 RCAR_GP_PIN(5, 13), 2832}; 2833static const unsigned int msiof1_rxd_d_mux[] = { 2834 MSIOF1_RXD_D_MARK, 2835}; 2836static const unsigned int msiof1_clk_e_pins[] = { 2837 /* SCK */ 2838 RCAR_GP_PIN(3, 0), 2839}; 2840static const unsigned int msiof1_clk_e_mux[] = { 2841 MSIOF1_SCK_E_MARK, 2842}; 2843static const unsigned int msiof1_sync_e_pins[] = { 2844 /* SYNC */ 2845 RCAR_GP_PIN(3, 1), 2846}; 2847static const unsigned int msiof1_sync_e_mux[] = { 2848 MSIOF1_SYNC_E_MARK, 2849}; 2850static const unsigned int msiof1_ss1_e_pins[] = { 2851 /* SS1 */ 2852 RCAR_GP_PIN(3, 4), 2853}; 2854static const unsigned int msiof1_ss1_e_mux[] = { 2855 MSIOF1_SS1_E_MARK, 2856}; 2857static const unsigned int msiof1_ss2_e_pins[] = { 2858 /* SS2 */ 2859 RCAR_GP_PIN(3, 5), 2860}; 2861static const unsigned int msiof1_ss2_e_mux[] = { 2862 MSIOF1_SS2_E_MARK, 2863}; 2864static const unsigned int msiof1_txd_e_pins[] = { 2865 /* TXD */ 2866 RCAR_GP_PIN(3, 3), 2867}; 2868static const unsigned int msiof1_txd_e_mux[] = { 2869 MSIOF1_TXD_E_MARK, 2870}; 2871static const unsigned int msiof1_rxd_e_pins[] = { 2872 /* RXD */ 2873 RCAR_GP_PIN(3, 2), 2874}; 2875static const unsigned int msiof1_rxd_e_mux[] = { 2876 MSIOF1_RXD_E_MARK, 2877}; 2878static const unsigned int msiof1_clk_f_pins[] = { 2879 /* SCK */ 2880 RCAR_GP_PIN(5, 23), 2881}; 2882static const unsigned int msiof1_clk_f_mux[] = { 2883 MSIOF1_SCK_F_MARK, 2884}; 2885static const unsigned int msiof1_sync_f_pins[] = { 2886 /* SYNC */ 2887 RCAR_GP_PIN(5, 24), 2888}; 2889static const unsigned int msiof1_sync_f_mux[] = { 2890 MSIOF1_SYNC_F_MARK, 2891}; 2892static const unsigned int msiof1_ss1_f_pins[] = { 2893 /* SS1 */ 2894 RCAR_GP_PIN(6, 1), 2895}; 2896static const unsigned int msiof1_ss1_f_mux[] = { 2897 MSIOF1_SS1_F_MARK, 2898}; 2899static const unsigned int msiof1_ss2_f_pins[] = { 2900 /* SS2 */ 2901 RCAR_GP_PIN(6, 2), 2902}; 2903static const unsigned int msiof1_ss2_f_mux[] = { 2904 MSIOF1_SS2_F_MARK, 2905}; 2906static const unsigned int msiof1_txd_f_pins[] = { 2907 /* TXD */ 2908 RCAR_GP_PIN(6, 0), 2909}; 2910static const unsigned int msiof1_txd_f_mux[] = { 2911 MSIOF1_TXD_F_MARK, 2912}; 2913static const unsigned int msiof1_rxd_f_pins[] = { 2914 /* RXD */ 2915 RCAR_GP_PIN(5, 25), 2916}; 2917static const unsigned int msiof1_rxd_f_mux[] = { 2918 MSIOF1_RXD_F_MARK, 2919}; 2920static const unsigned int msiof1_clk_g_pins[] = { 2921 /* SCK */ 2922 RCAR_GP_PIN(3, 6), 2923}; 2924static const unsigned int msiof1_clk_g_mux[] = { 2925 MSIOF1_SCK_G_MARK, 2926}; 2927static const unsigned int msiof1_sync_g_pins[] = { 2928 /* SYNC */ 2929 RCAR_GP_PIN(3, 7), 2930}; 2931static const unsigned int msiof1_sync_g_mux[] = { 2932 MSIOF1_SYNC_G_MARK, 2933}; 2934static const unsigned int msiof1_ss1_g_pins[] = { 2935 /* SS1 */ 2936 RCAR_GP_PIN(3, 10), 2937}; 2938static const unsigned int msiof1_ss1_g_mux[] = { 2939 MSIOF1_SS1_G_MARK, 2940}; 2941static const unsigned int msiof1_ss2_g_pins[] = { 2942 /* SS2 */ 2943 RCAR_GP_PIN(3, 11), 2944}; 2945static const unsigned int msiof1_ss2_g_mux[] = { 2946 MSIOF1_SS2_G_MARK, 2947}; 2948static const unsigned int msiof1_txd_g_pins[] = { 2949 /* TXD */ 2950 RCAR_GP_PIN(3, 9), 2951}; 2952static const unsigned int msiof1_txd_g_mux[] = { 2953 MSIOF1_TXD_G_MARK, 2954}; 2955static const unsigned int msiof1_rxd_g_pins[] = { 2956 /* RXD */ 2957 RCAR_GP_PIN(3, 8), 2958}; 2959static const unsigned int msiof1_rxd_g_mux[] = { 2960 MSIOF1_RXD_G_MARK, 2961}; 2962/* - MSIOF2 ----------------------------------------------------------------- */ 2963static const unsigned int msiof2_clk_a_pins[] = { 2964 /* SCK */ 2965 RCAR_GP_PIN(1, 9), 2966}; 2967static const unsigned int msiof2_clk_a_mux[] = { 2968 MSIOF2_SCK_A_MARK, 2969}; 2970static const unsigned int msiof2_sync_a_pins[] = { 2971 /* SYNC */ 2972 RCAR_GP_PIN(1, 8), 2973}; 2974static const unsigned int msiof2_sync_a_mux[] = { 2975 MSIOF2_SYNC_A_MARK, 2976}; 2977static const unsigned int msiof2_ss1_a_pins[] = { 2978 /* SS1 */ 2979 RCAR_GP_PIN(1, 6), 2980}; 2981static const unsigned int msiof2_ss1_a_mux[] = { 2982 MSIOF2_SS1_A_MARK, 2983}; 2984static const unsigned int msiof2_ss2_a_pins[] = { 2985 /* SS2 */ 2986 RCAR_GP_PIN(1, 7), 2987}; 2988static const unsigned int msiof2_ss2_a_mux[] = { 2989 MSIOF2_SS2_A_MARK, 2990}; 2991static const unsigned int msiof2_txd_a_pins[] = { 2992 /* TXD */ 2993 RCAR_GP_PIN(1, 11), 2994}; 2995static const unsigned int msiof2_txd_a_mux[] = { 2996 MSIOF2_TXD_A_MARK, 2997}; 2998static const unsigned int msiof2_rxd_a_pins[] = { 2999 /* RXD */ 3000 RCAR_GP_PIN(1, 10), 3001}; 3002static const unsigned int msiof2_rxd_a_mux[] = { 3003 MSIOF2_RXD_A_MARK, 3004}; 3005static const unsigned int msiof2_clk_b_pins[] = { 3006 /* SCK */ 3007 RCAR_GP_PIN(0, 4), 3008}; 3009static const unsigned int msiof2_clk_b_mux[] = { 3010 MSIOF2_SCK_B_MARK, 3011}; 3012static const unsigned int msiof2_sync_b_pins[] = { 3013 /* SYNC */ 3014 RCAR_GP_PIN(0, 5), 3015}; 3016static const unsigned int msiof2_sync_b_mux[] = { 3017 MSIOF2_SYNC_B_MARK, 3018}; 3019static const unsigned int msiof2_ss1_b_pins[] = { 3020 /* SS1 */ 3021 RCAR_GP_PIN(0, 0), 3022}; 3023static const unsigned int msiof2_ss1_b_mux[] = { 3024 MSIOF2_SS1_B_MARK, 3025}; 3026static const unsigned int msiof2_ss2_b_pins[] = { 3027 /* SS2 */ 3028 RCAR_GP_PIN(0, 1), 3029}; 3030static const unsigned int msiof2_ss2_b_mux[] = { 3031 MSIOF2_SS2_B_MARK, 3032}; 3033static const unsigned int msiof2_txd_b_pins[] = { 3034 /* TXD */ 3035 RCAR_GP_PIN(0, 7), 3036}; 3037static const unsigned int msiof2_txd_b_mux[] = { 3038 MSIOF2_TXD_B_MARK, 3039}; 3040static const unsigned int msiof2_rxd_b_pins[] = { 3041 /* RXD */ 3042 RCAR_GP_PIN(0, 6), 3043}; 3044static const unsigned int msiof2_rxd_b_mux[] = { 3045 MSIOF2_RXD_B_MARK, 3046}; 3047static const unsigned int msiof2_clk_c_pins[] = { 3048 /* SCK */ 3049 RCAR_GP_PIN(2, 12), 3050}; 3051static const unsigned int msiof2_clk_c_mux[] = { 3052 MSIOF2_SCK_C_MARK, 3053}; 3054static const unsigned int msiof2_sync_c_pins[] = { 3055 /* SYNC */ 3056 RCAR_GP_PIN(2, 11), 3057}; 3058static const unsigned int msiof2_sync_c_mux[] = { 3059 MSIOF2_SYNC_C_MARK, 3060}; 3061static const unsigned int msiof2_ss1_c_pins[] = { 3062 /* SS1 */ 3063 RCAR_GP_PIN(2, 10), 3064}; 3065static const unsigned int msiof2_ss1_c_mux[] = { 3066 MSIOF2_SS1_C_MARK, 3067}; 3068static const unsigned int msiof2_ss2_c_pins[] = { 3069 /* SS2 */ 3070 RCAR_GP_PIN(2, 9), 3071}; 3072static const unsigned int msiof2_ss2_c_mux[] = { 3073 MSIOF2_SS2_C_MARK, 3074}; 3075static const unsigned int msiof2_txd_c_pins[] = { 3076 /* TXD */ 3077 RCAR_GP_PIN(2, 14), 3078}; 3079static const unsigned int msiof2_txd_c_mux[] = { 3080 MSIOF2_TXD_C_MARK, 3081}; 3082static const unsigned int msiof2_rxd_c_pins[] = { 3083 /* RXD */ 3084 RCAR_GP_PIN(2, 13), 3085}; 3086static const unsigned int msiof2_rxd_c_mux[] = { 3087 MSIOF2_RXD_C_MARK, 3088}; 3089static const unsigned int msiof2_clk_d_pins[] = { 3090 /* SCK */ 3091 RCAR_GP_PIN(0, 8), 3092}; 3093static const unsigned int msiof2_clk_d_mux[] = { 3094 MSIOF2_SCK_D_MARK, 3095}; 3096static const unsigned int msiof2_sync_d_pins[] = { 3097 /* SYNC */ 3098 RCAR_GP_PIN(0, 9), 3099}; 3100static const unsigned int msiof2_sync_d_mux[] = { 3101 MSIOF2_SYNC_D_MARK, 3102}; 3103static const unsigned int msiof2_ss1_d_pins[] = { 3104 /* SS1 */ 3105 RCAR_GP_PIN(0, 12), 3106}; 3107static const unsigned int msiof2_ss1_d_mux[] = { 3108 MSIOF2_SS1_D_MARK, 3109}; 3110static const unsigned int msiof2_ss2_d_pins[] = { 3111 /* SS2 */ 3112 RCAR_GP_PIN(0, 13), 3113}; 3114static const unsigned int msiof2_ss2_d_mux[] = { 3115 MSIOF2_SS2_D_MARK, 3116}; 3117static const unsigned int msiof2_txd_d_pins[] = { 3118 /* TXD */ 3119 RCAR_GP_PIN(0, 11), 3120}; 3121static const unsigned int msiof2_txd_d_mux[] = { 3122 MSIOF2_TXD_D_MARK, 3123}; 3124static const unsigned int msiof2_rxd_d_pins[] = { 3125 /* RXD */ 3126 RCAR_GP_PIN(0, 10), 3127}; 3128static const unsigned int msiof2_rxd_d_mux[] = { 3129 MSIOF2_RXD_D_MARK, 3130}; 3131/* - MSIOF3 ----------------------------------------------------------------- */ 3132static const unsigned int msiof3_clk_a_pins[] = { 3133 /* SCK */ 3134 RCAR_GP_PIN(0, 0), 3135}; 3136static const unsigned int msiof3_clk_a_mux[] = { 3137 MSIOF3_SCK_A_MARK, 3138}; 3139static const unsigned int msiof3_sync_a_pins[] = { 3140 /* SYNC */ 3141 RCAR_GP_PIN(0, 1), 3142}; 3143static const unsigned int msiof3_sync_a_mux[] = { 3144 MSIOF3_SYNC_A_MARK, 3145}; 3146static const unsigned int msiof3_ss1_a_pins[] = { 3147 /* SS1 */ 3148 RCAR_GP_PIN(0, 14), 3149}; 3150static const unsigned int msiof3_ss1_a_mux[] = { 3151 MSIOF3_SS1_A_MARK, 3152}; 3153static const unsigned int msiof3_ss2_a_pins[] = { 3154 /* SS2 */ 3155 RCAR_GP_PIN(0, 15), 3156}; 3157static const unsigned int msiof3_ss2_a_mux[] = { 3158 MSIOF3_SS2_A_MARK, 3159}; 3160static const unsigned int msiof3_txd_a_pins[] = { 3161 /* TXD */ 3162 RCAR_GP_PIN(0, 3), 3163}; 3164static const unsigned int msiof3_txd_a_mux[] = { 3165 MSIOF3_TXD_A_MARK, 3166}; 3167static const unsigned int msiof3_rxd_a_pins[] = { 3168 /* RXD */ 3169 RCAR_GP_PIN(0, 2), 3170}; 3171static const unsigned int msiof3_rxd_a_mux[] = { 3172 MSIOF3_RXD_A_MARK, 3173}; 3174static const unsigned int msiof3_clk_b_pins[] = { 3175 /* SCK */ 3176 RCAR_GP_PIN(1, 2), 3177}; 3178static const unsigned int msiof3_clk_b_mux[] = { 3179 MSIOF3_SCK_B_MARK, 3180}; 3181static const unsigned int msiof3_sync_b_pins[] = { 3182 /* SYNC */ 3183 RCAR_GP_PIN(1, 0), 3184}; 3185static const unsigned int msiof3_sync_b_mux[] = { 3186 MSIOF3_SYNC_B_MARK, 3187}; 3188static const unsigned int msiof3_ss1_b_pins[] = { 3189 /* SS1 */ 3190 RCAR_GP_PIN(1, 4), 3191}; 3192static const unsigned int msiof3_ss1_b_mux[] = { 3193 MSIOF3_SS1_B_MARK, 3194}; 3195static const unsigned int msiof3_ss2_b_pins[] = { 3196 /* SS2 */ 3197 RCAR_GP_PIN(1, 5), 3198}; 3199static const unsigned int msiof3_ss2_b_mux[] = { 3200 MSIOF3_SS2_B_MARK, 3201}; 3202static const unsigned int msiof3_txd_b_pins[] = { 3203 /* TXD */ 3204 RCAR_GP_PIN(1, 1), 3205}; 3206static const unsigned int msiof3_txd_b_mux[] = { 3207 MSIOF3_TXD_B_MARK, 3208}; 3209static const unsigned int msiof3_rxd_b_pins[] = { 3210 /* RXD */ 3211 RCAR_GP_PIN(1, 3), 3212}; 3213static const unsigned int msiof3_rxd_b_mux[] = { 3214 MSIOF3_RXD_B_MARK, 3215}; 3216static const unsigned int msiof3_clk_c_pins[] = { 3217 /* SCK */ 3218 RCAR_GP_PIN(1, 12), 3219}; 3220static const unsigned int msiof3_clk_c_mux[] = { 3221 MSIOF3_SCK_C_MARK, 3222}; 3223static const unsigned int msiof3_sync_c_pins[] = { 3224 /* SYNC */ 3225 RCAR_GP_PIN(1, 13), 3226}; 3227static const unsigned int msiof3_sync_c_mux[] = { 3228 MSIOF3_SYNC_C_MARK, 3229}; 3230static const unsigned int msiof3_txd_c_pins[] = { 3231 /* TXD */ 3232 RCAR_GP_PIN(1, 15), 3233}; 3234static const unsigned int msiof3_txd_c_mux[] = { 3235 MSIOF3_TXD_C_MARK, 3236}; 3237static const unsigned int msiof3_rxd_c_pins[] = { 3238 /* RXD */ 3239 RCAR_GP_PIN(1, 14), 3240}; 3241static const unsigned int msiof3_rxd_c_mux[] = { 3242 MSIOF3_RXD_C_MARK, 3243}; 3244static const unsigned int msiof3_clk_d_pins[] = { 3245 /* SCK */ 3246 RCAR_GP_PIN(1, 22), 3247}; 3248static const unsigned int msiof3_clk_d_mux[] = { 3249 MSIOF3_SCK_D_MARK, 3250}; 3251static const unsigned int msiof3_sync_d_pins[] = { 3252 /* SYNC */ 3253 RCAR_GP_PIN(1, 23), 3254}; 3255static const unsigned int msiof3_sync_d_mux[] = { 3256 MSIOF3_SYNC_D_MARK, 3257}; 3258static const unsigned int msiof3_ss1_d_pins[] = { 3259 /* SS1 */ 3260 RCAR_GP_PIN(1, 26), 3261}; 3262static const unsigned int msiof3_ss1_d_mux[] = { 3263 MSIOF3_SS1_D_MARK, 3264}; 3265static const unsigned int msiof3_txd_d_pins[] = { 3266 /* TXD */ 3267 RCAR_GP_PIN(1, 25), 3268}; 3269static const unsigned int msiof3_txd_d_mux[] = { 3270 MSIOF3_TXD_D_MARK, 3271}; 3272static const unsigned int msiof3_rxd_d_pins[] = { 3273 /* RXD */ 3274 RCAR_GP_PIN(1, 24), 3275}; 3276static const unsigned int msiof3_rxd_d_mux[] = { 3277 MSIOF3_RXD_D_MARK, 3278}; 3279static const unsigned int msiof3_clk_e_pins[] = { 3280 /* SCK */ 3281 RCAR_GP_PIN(2, 3), 3282}; 3283static const unsigned int msiof3_clk_e_mux[] = { 3284 MSIOF3_SCK_E_MARK, 3285}; 3286static const unsigned int msiof3_sync_e_pins[] = { 3287 /* SYNC */ 3288 RCAR_GP_PIN(2, 2), 3289}; 3290static const unsigned int msiof3_sync_e_mux[] = { 3291 MSIOF3_SYNC_E_MARK, 3292}; 3293static const unsigned int msiof3_ss1_e_pins[] = { 3294 /* SS1 */ 3295 RCAR_GP_PIN(2, 1), 3296}; 3297static const unsigned int msiof3_ss1_e_mux[] = { 3298 MSIOF3_SS1_E_MARK, 3299}; 3300static const unsigned int msiof3_ss2_e_pins[] = { 3301 /* SS2 */ 3302 RCAR_GP_PIN(2, 0), 3303}; 3304static const unsigned int msiof3_ss2_e_mux[] = { 3305 MSIOF3_SS2_E_MARK, 3306}; 3307static const unsigned int msiof3_txd_e_pins[] = { 3308 /* TXD */ 3309 RCAR_GP_PIN(2, 5), 3310}; 3311static const unsigned int msiof3_txd_e_mux[] = { 3312 MSIOF3_TXD_E_MARK, 3313}; 3314static const unsigned int msiof3_rxd_e_pins[] = { 3315 /* RXD */ 3316 RCAR_GP_PIN(2, 4), 3317}; 3318static const unsigned int msiof3_rxd_e_mux[] = { 3319 MSIOF3_RXD_E_MARK, 3320}; 3321 3322/* - PWM0 --------------------------------------------------------------------*/ 3323static const unsigned int pwm0_pins[] = { 3324 /* PWM */ 3325 RCAR_GP_PIN(2, 6), 3326}; 3327static const unsigned int pwm0_mux[] = { 3328 PWM0_MARK, 3329}; 3330/* - PWM1 --------------------------------------------------------------------*/ 3331static const unsigned int pwm1_a_pins[] = { 3332 /* PWM */ 3333 RCAR_GP_PIN(2, 7), 3334}; 3335static const unsigned int pwm1_a_mux[] = { 3336 PWM1_A_MARK, 3337}; 3338static const unsigned int pwm1_b_pins[] = { 3339 /* PWM */ 3340 RCAR_GP_PIN(1, 8), 3341}; 3342static const unsigned int pwm1_b_mux[] = { 3343 PWM1_B_MARK, 3344}; 3345/* - PWM2 --------------------------------------------------------------------*/ 3346static const unsigned int pwm2_a_pins[] = { 3347 /* PWM */ 3348 RCAR_GP_PIN(2, 8), 3349}; 3350static const unsigned int pwm2_a_mux[] = { 3351 PWM2_A_MARK, 3352}; 3353static const unsigned int pwm2_b_pins[] = { 3354 /* PWM */ 3355 RCAR_GP_PIN(1, 11), 3356}; 3357static const unsigned int pwm2_b_mux[] = { 3358 PWM2_B_MARK, 3359}; 3360/* - PWM3 --------------------------------------------------------------------*/ 3361static const unsigned int pwm3_a_pins[] = { 3362 /* PWM */ 3363 RCAR_GP_PIN(1, 0), 3364}; 3365static const unsigned int pwm3_a_mux[] = { 3366 PWM3_A_MARK, 3367}; 3368static const unsigned int pwm3_b_pins[] = { 3369 /* PWM */ 3370 RCAR_GP_PIN(2, 2), 3371}; 3372static const unsigned int pwm3_b_mux[] = { 3373 PWM3_B_MARK, 3374}; 3375/* - PWM4 --------------------------------------------------------------------*/ 3376static const unsigned int pwm4_a_pins[] = { 3377 /* PWM */ 3378 RCAR_GP_PIN(1, 1), 3379}; 3380static const unsigned int pwm4_a_mux[] = { 3381 PWM4_A_MARK, 3382}; 3383static const unsigned int pwm4_b_pins[] = { 3384 /* PWM */ 3385 RCAR_GP_PIN(2, 3), 3386}; 3387static const unsigned int pwm4_b_mux[] = { 3388 PWM4_B_MARK, 3389}; 3390/* - PWM5 --------------------------------------------------------------------*/ 3391static const unsigned int pwm5_a_pins[] = { 3392 /* PWM */ 3393 RCAR_GP_PIN(1, 2), 3394}; 3395static const unsigned int pwm5_a_mux[] = { 3396 PWM5_A_MARK, 3397}; 3398static const unsigned int pwm5_b_pins[] = { 3399 /* PWM */ 3400 RCAR_GP_PIN(2, 4), 3401}; 3402static const unsigned int pwm5_b_mux[] = { 3403 PWM5_B_MARK, 3404}; 3405/* - PWM6 --------------------------------------------------------------------*/ 3406static const unsigned int pwm6_a_pins[] = { 3407 /* PWM */ 3408 RCAR_GP_PIN(1, 3), 3409}; 3410static const unsigned int pwm6_a_mux[] = { 3411 PWM6_A_MARK, 3412}; 3413static const unsigned int pwm6_b_pins[] = { 3414 /* PWM */ 3415 RCAR_GP_PIN(2, 5), 3416}; 3417static const unsigned int pwm6_b_mux[] = { 3418 PWM6_B_MARK, 3419}; 3420 3421/* - QSPI0 ------------------------------------------------------------------ */ 3422static const unsigned int qspi0_ctrl_pins[] = { 3423 /* QSPI0_SPCLK, QSPI0_SSL */ 3424 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, 3425}; 3426static const unsigned int qspi0_ctrl_mux[] = { 3427 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 3428}; 3429static const unsigned int qspi0_data_pins[] = { 3430 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3431 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3432 /* QSPI0_IO2, QSPI0_IO3 */ 3433 PIN_QSPI0_IO2, PIN_QSPI0_IO3, 3434}; 3435static const unsigned int qspi0_data_mux[] = { 3436 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3437 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 3438}; 3439/* - QSPI1 ------------------------------------------------------------------ */ 3440static const unsigned int qspi1_ctrl_pins[] = { 3441 /* QSPI1_SPCLK, QSPI1_SSL */ 3442 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, 3443}; 3444static const unsigned int qspi1_ctrl_mux[] = { 3445 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 3446}; 3447static const unsigned int qspi1_data_pins[] = { 3448 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3449 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3450 /* QSPI1_IO2, QSPI1_IO3 */ 3451 PIN_QSPI1_IO2, PIN_QSPI1_IO3, 3452}; 3453static const unsigned int qspi1_data_mux[] = { 3454 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3455 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 3456}; 3457 3458/* - SATA --------------------------------------------------------------------*/ 3459static const unsigned int sata0_devslp_a_pins[] = { 3460 /* DEVSLP */ 3461 RCAR_GP_PIN(6, 16), 3462}; 3463 3464static const unsigned int sata0_devslp_a_mux[] = { 3465 SATA_DEVSLP_A_MARK, 3466}; 3467 3468static const unsigned int sata0_devslp_b_pins[] = { 3469 /* DEVSLP */ 3470 RCAR_GP_PIN(4, 6), 3471}; 3472 3473static const unsigned int sata0_devslp_b_mux[] = { 3474 SATA_DEVSLP_B_MARK, 3475}; 3476 3477/* - SCIF0 ------------------------------------------------------------------ */ 3478static const unsigned int scif0_data_pins[] = { 3479 /* RX, TX */ 3480 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3481}; 3482static const unsigned int scif0_data_mux[] = { 3483 RX0_MARK, TX0_MARK, 3484}; 3485static const unsigned int scif0_clk_pins[] = { 3486 /* SCK */ 3487 RCAR_GP_PIN(5, 0), 3488}; 3489static const unsigned int scif0_clk_mux[] = { 3490 SCK0_MARK, 3491}; 3492static const unsigned int scif0_ctrl_pins[] = { 3493 /* RTS, CTS */ 3494 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3495}; 3496static const unsigned int scif0_ctrl_mux[] = { 3497 RTS0_N_MARK, CTS0_N_MARK, 3498}; 3499/* - SCIF1 ------------------------------------------------------------------ */ 3500static const unsigned int scif1_data_a_pins[] = { 3501 /* RX, TX */ 3502 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3503}; 3504static const unsigned int scif1_data_a_mux[] = { 3505 RX1_A_MARK, TX1_A_MARK, 3506}; 3507static const unsigned int scif1_clk_pins[] = { 3508 /* SCK */ 3509 RCAR_GP_PIN(6, 21), 3510}; 3511static const unsigned int scif1_clk_mux[] = { 3512 SCK1_MARK, 3513}; 3514static const unsigned int scif1_ctrl_pins[] = { 3515 /* RTS, CTS */ 3516 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3517}; 3518static const unsigned int scif1_ctrl_mux[] = { 3519 RTS1_N_MARK, CTS1_N_MARK, 3520}; 3521static const unsigned int scif1_data_b_pins[] = { 3522 /* RX, TX */ 3523 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3524}; 3525static const unsigned int scif1_data_b_mux[] = { 3526 RX1_B_MARK, TX1_B_MARK, 3527}; 3528/* - SCIF2 ------------------------------------------------------------------ */ 3529static const unsigned int scif2_data_a_pins[] = { 3530 /* RX, TX */ 3531 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3532}; 3533static const unsigned int scif2_data_a_mux[] = { 3534 RX2_A_MARK, TX2_A_MARK, 3535}; 3536static const unsigned int scif2_clk_pins[] = { 3537 /* SCK */ 3538 RCAR_GP_PIN(5, 9), 3539}; 3540static const unsigned int scif2_clk_mux[] = { 3541 SCK2_MARK, 3542}; 3543static const unsigned int scif2_data_b_pins[] = { 3544 /* RX, TX */ 3545 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3546}; 3547static const unsigned int scif2_data_b_mux[] = { 3548 RX2_B_MARK, TX2_B_MARK, 3549}; 3550/* - SCIF3 ------------------------------------------------------------------ */ 3551static const unsigned int scif3_data_a_pins[] = { 3552 /* RX, TX */ 3553 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3554}; 3555static const unsigned int scif3_data_a_mux[] = { 3556 RX3_A_MARK, TX3_A_MARK, 3557}; 3558static const unsigned int scif3_clk_pins[] = { 3559 /* SCK */ 3560 RCAR_GP_PIN(1, 22), 3561}; 3562static const unsigned int scif3_clk_mux[] = { 3563 SCK3_MARK, 3564}; 3565static const unsigned int scif3_ctrl_pins[] = { 3566 /* RTS, CTS */ 3567 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3568}; 3569static const unsigned int scif3_ctrl_mux[] = { 3570 RTS3_N_MARK, CTS3_N_MARK, 3571}; 3572static const unsigned int scif3_data_b_pins[] = { 3573 /* RX, TX */ 3574 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3575}; 3576static const unsigned int scif3_data_b_mux[] = { 3577 RX3_B_MARK, TX3_B_MARK, 3578}; 3579/* - SCIF4 ------------------------------------------------------------------ */ 3580static const unsigned int scif4_data_a_pins[] = { 3581 /* RX, TX */ 3582 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3583}; 3584static const unsigned int scif4_data_a_mux[] = { 3585 RX4_A_MARK, TX4_A_MARK, 3586}; 3587static const unsigned int scif4_clk_a_pins[] = { 3588 /* SCK */ 3589 RCAR_GP_PIN(2, 10), 3590}; 3591static const unsigned int scif4_clk_a_mux[] = { 3592 SCK4_A_MARK, 3593}; 3594static const unsigned int scif4_ctrl_a_pins[] = { 3595 /* RTS, CTS */ 3596 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3597}; 3598static const unsigned int scif4_ctrl_a_mux[] = { 3599 RTS4_N_A_MARK, CTS4_N_A_MARK, 3600}; 3601static const unsigned int scif4_data_b_pins[] = { 3602 /* RX, TX */ 3603 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3604}; 3605static const unsigned int scif4_data_b_mux[] = { 3606 RX4_B_MARK, TX4_B_MARK, 3607}; 3608static const unsigned int scif4_clk_b_pins[] = { 3609 /* SCK */ 3610 RCAR_GP_PIN(1, 5), 3611}; 3612static const unsigned int scif4_clk_b_mux[] = { 3613 SCK4_B_MARK, 3614}; 3615static const unsigned int scif4_ctrl_b_pins[] = { 3616 /* RTS, CTS */ 3617 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3618}; 3619static const unsigned int scif4_ctrl_b_mux[] = { 3620 RTS4_N_B_MARK, CTS4_N_B_MARK, 3621}; 3622static const unsigned int scif4_data_c_pins[] = { 3623 /* RX, TX */ 3624 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3625}; 3626static const unsigned int scif4_data_c_mux[] = { 3627 RX4_C_MARK, TX4_C_MARK, 3628}; 3629static const unsigned int scif4_clk_c_pins[] = { 3630 /* SCK */ 3631 RCAR_GP_PIN(0, 8), 3632}; 3633static const unsigned int scif4_clk_c_mux[] = { 3634 SCK4_C_MARK, 3635}; 3636static const unsigned int scif4_ctrl_c_pins[] = { 3637 /* RTS, CTS */ 3638 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3639}; 3640static const unsigned int scif4_ctrl_c_mux[] = { 3641 RTS4_N_C_MARK, CTS4_N_C_MARK, 3642}; 3643/* - SCIF5 ------------------------------------------------------------------ */ 3644static const unsigned int scif5_data_a_pins[] = { 3645 /* RX, TX */ 3646 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3647}; 3648static const unsigned int scif5_data_a_mux[] = { 3649 RX5_A_MARK, TX5_A_MARK, 3650}; 3651static const unsigned int scif5_clk_a_pins[] = { 3652 /* SCK */ 3653 RCAR_GP_PIN(6, 21), 3654}; 3655static const unsigned int scif5_clk_a_mux[] = { 3656 SCK5_A_MARK, 3657}; 3658static const unsigned int scif5_data_b_pins[] = { 3659 /* RX, TX */ 3660 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3661}; 3662static const unsigned int scif5_data_b_mux[] = { 3663 RX5_B_MARK, TX5_B_MARK, 3664}; 3665static const unsigned int scif5_clk_b_pins[] = { 3666 /* SCK */ 3667 RCAR_GP_PIN(5, 0), 3668}; 3669static const unsigned int scif5_clk_b_mux[] = { 3670 SCK5_B_MARK, 3671}; 3672/* - SCIF Clock ------------------------------------------------------------- */ 3673static const unsigned int scif_clk_a_pins[] = { 3674 /* SCIF_CLK */ 3675 RCAR_GP_PIN(6, 23), 3676}; 3677static const unsigned int scif_clk_a_mux[] = { 3678 SCIF_CLK_A_MARK, 3679}; 3680static const unsigned int scif_clk_b_pins[] = { 3681 /* SCIF_CLK */ 3682 RCAR_GP_PIN(5, 9), 3683}; 3684static const unsigned int scif_clk_b_mux[] = { 3685 SCIF_CLK_B_MARK, 3686}; 3687 3688/* - SDHI0 ------------------------------------------------------------------ */ 3689static const unsigned int sdhi0_data_pins[] = { 3690 /* D[0:3] */ 3691 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3692 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3693}; 3694 3695static const unsigned int sdhi0_data_mux[] = { 3696 SD0_DAT0_MARK, SD0_DAT1_MARK, 3697 SD0_DAT2_MARK, SD0_DAT3_MARK, 3698}; 3699 3700static const unsigned int sdhi0_ctrl_pins[] = { 3701 /* CLK, CMD */ 3702 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3703}; 3704 3705static const unsigned int sdhi0_ctrl_mux[] = { 3706 SD0_CLK_MARK, SD0_CMD_MARK, 3707}; 3708 3709static const unsigned int sdhi0_cd_pins[] = { 3710 /* CD */ 3711 RCAR_GP_PIN(3, 12), 3712}; 3713 3714static const unsigned int sdhi0_cd_mux[] = { 3715 SD0_CD_MARK, 3716}; 3717 3718static const unsigned int sdhi0_wp_pins[] = { 3719 /* WP */ 3720 RCAR_GP_PIN(3, 13), 3721}; 3722 3723static const unsigned int sdhi0_wp_mux[] = { 3724 SD0_WP_MARK, 3725}; 3726 3727/* - SDHI1 ------------------------------------------------------------------ */ 3728static const unsigned int sdhi1_data_pins[] = { 3729 /* D[0:3] */ 3730 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3731 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3732}; 3733 3734static const unsigned int sdhi1_data_mux[] = { 3735 SD1_DAT0_MARK, SD1_DAT1_MARK, 3736 SD1_DAT2_MARK, SD1_DAT3_MARK, 3737}; 3738 3739static const unsigned int sdhi1_ctrl_pins[] = { 3740 /* CLK, CMD */ 3741 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3742}; 3743 3744static const unsigned int sdhi1_ctrl_mux[] = { 3745 SD1_CLK_MARK, SD1_CMD_MARK, 3746}; 3747 3748static const unsigned int sdhi1_cd_pins[] = { 3749 /* CD */ 3750 RCAR_GP_PIN(3, 14), 3751}; 3752 3753static const unsigned int sdhi1_cd_mux[] = { 3754 SD1_CD_MARK, 3755}; 3756 3757static const unsigned int sdhi1_wp_pins[] = { 3758 /* WP */ 3759 RCAR_GP_PIN(3, 15), 3760}; 3761 3762static const unsigned int sdhi1_wp_mux[] = { 3763 SD1_WP_MARK, 3764}; 3765 3766/* - SDHI2 ------------------------------------------------------------------ */ 3767static const unsigned int sdhi2_data_pins[] = { 3768 /* D[0:7] */ 3769 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3770 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3771 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3772 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3773}; 3774 3775static const unsigned int sdhi2_data_mux[] = { 3776 SD2_DAT0_MARK, SD2_DAT1_MARK, 3777 SD2_DAT2_MARK, SD2_DAT3_MARK, 3778 SD2_DAT4_MARK, SD2_DAT5_MARK, 3779 SD2_DAT6_MARK, SD2_DAT7_MARK, 3780}; 3781 3782static const unsigned int sdhi2_ctrl_pins[] = { 3783 /* CLK, CMD */ 3784 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3785}; 3786 3787static const unsigned int sdhi2_ctrl_mux[] = { 3788 SD2_CLK_MARK, SD2_CMD_MARK, 3789}; 3790 3791static const unsigned int sdhi2_cd_a_pins[] = { 3792 /* CD */ 3793 RCAR_GP_PIN(4, 13), 3794}; 3795 3796static const unsigned int sdhi2_cd_a_mux[] = { 3797 SD2_CD_A_MARK, 3798}; 3799 3800static const unsigned int sdhi2_cd_b_pins[] = { 3801 /* CD */ 3802 RCAR_GP_PIN(5, 10), 3803}; 3804 3805static const unsigned int sdhi2_cd_b_mux[] = { 3806 SD2_CD_B_MARK, 3807}; 3808 3809static const unsigned int sdhi2_wp_a_pins[] = { 3810 /* WP */ 3811 RCAR_GP_PIN(4, 14), 3812}; 3813 3814static const unsigned int sdhi2_wp_a_mux[] = { 3815 SD2_WP_A_MARK, 3816}; 3817 3818static const unsigned int sdhi2_wp_b_pins[] = { 3819 /* WP */ 3820 RCAR_GP_PIN(5, 11), 3821}; 3822 3823static const unsigned int sdhi2_wp_b_mux[] = { 3824 SD2_WP_B_MARK, 3825}; 3826 3827static const unsigned int sdhi2_ds_pins[] = { 3828 /* DS */ 3829 RCAR_GP_PIN(4, 6), 3830}; 3831 3832static const unsigned int sdhi2_ds_mux[] = { 3833 SD2_DS_MARK, 3834}; 3835 3836/* - SDHI3 ------------------------------------------------------------------ */ 3837static const unsigned int sdhi3_data_pins[] = { 3838 /* D[0:7] */ 3839 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3840 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3841 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3842 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3843}; 3844 3845static const unsigned int sdhi3_data_mux[] = { 3846 SD3_DAT0_MARK, SD3_DAT1_MARK, 3847 SD3_DAT2_MARK, SD3_DAT3_MARK, 3848 SD3_DAT4_MARK, SD3_DAT5_MARK, 3849 SD3_DAT6_MARK, SD3_DAT7_MARK, 3850}; 3851 3852static const unsigned int sdhi3_ctrl_pins[] = { 3853 /* CLK, CMD */ 3854 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3855}; 3856 3857static const unsigned int sdhi3_ctrl_mux[] = { 3858 SD3_CLK_MARK, SD3_CMD_MARK, 3859}; 3860 3861static const unsigned int sdhi3_cd_pins[] = { 3862 /* CD */ 3863 RCAR_GP_PIN(4, 15), 3864}; 3865 3866static const unsigned int sdhi3_cd_mux[] = { 3867 SD3_CD_MARK, 3868}; 3869 3870static const unsigned int sdhi3_wp_pins[] = { 3871 /* WP */ 3872 RCAR_GP_PIN(4, 16), 3873}; 3874 3875static const unsigned int sdhi3_wp_mux[] = { 3876 SD3_WP_MARK, 3877}; 3878 3879static const unsigned int sdhi3_ds_pins[] = { 3880 /* DS */ 3881 RCAR_GP_PIN(4, 17), 3882}; 3883 3884static const unsigned int sdhi3_ds_mux[] = { 3885 SD3_DS_MARK, 3886}; 3887 3888/* - SSI -------------------------------------------------------------------- */ 3889static const unsigned int ssi0_data_pins[] = { 3890 /* SDATA */ 3891 RCAR_GP_PIN(6, 2), 3892}; 3893static const unsigned int ssi0_data_mux[] = { 3894 SSI_SDATA0_MARK, 3895}; 3896static const unsigned int ssi01239_ctrl_pins[] = { 3897 /* SCK, WS */ 3898 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3899}; 3900static const unsigned int ssi01239_ctrl_mux[] = { 3901 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3902}; 3903static const unsigned int ssi1_data_a_pins[] = { 3904 /* SDATA */ 3905 RCAR_GP_PIN(6, 3), 3906}; 3907static const unsigned int ssi1_data_a_mux[] = { 3908 SSI_SDATA1_A_MARK, 3909}; 3910static const unsigned int ssi1_data_b_pins[] = { 3911 /* SDATA */ 3912 RCAR_GP_PIN(5, 12), 3913}; 3914static const unsigned int ssi1_data_b_mux[] = { 3915 SSI_SDATA1_B_MARK, 3916}; 3917static const unsigned int ssi1_ctrl_a_pins[] = { 3918 /* SCK, WS */ 3919 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3920}; 3921static const unsigned int ssi1_ctrl_a_mux[] = { 3922 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3923}; 3924static const unsigned int ssi1_ctrl_b_pins[] = { 3925 /* SCK, WS */ 3926 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3927}; 3928static const unsigned int ssi1_ctrl_b_mux[] = { 3929 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3930}; 3931static const unsigned int ssi2_data_a_pins[] = { 3932 /* SDATA */ 3933 RCAR_GP_PIN(6, 4), 3934}; 3935static const unsigned int ssi2_data_a_mux[] = { 3936 SSI_SDATA2_A_MARK, 3937}; 3938static const unsigned int ssi2_data_b_pins[] = { 3939 /* SDATA */ 3940 RCAR_GP_PIN(5, 13), 3941}; 3942static const unsigned int ssi2_data_b_mux[] = { 3943 SSI_SDATA2_B_MARK, 3944}; 3945static const unsigned int ssi2_ctrl_a_pins[] = { 3946 /* SCK, WS */ 3947 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3948}; 3949static const unsigned int ssi2_ctrl_a_mux[] = { 3950 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3951}; 3952static const unsigned int ssi2_ctrl_b_pins[] = { 3953 /* SCK, WS */ 3954 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 3955}; 3956static const unsigned int ssi2_ctrl_b_mux[] = { 3957 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3958}; 3959static const unsigned int ssi3_data_pins[] = { 3960 /* SDATA */ 3961 RCAR_GP_PIN(6, 7), 3962}; 3963static const unsigned int ssi3_data_mux[] = { 3964 SSI_SDATA3_MARK, 3965}; 3966static const unsigned int ssi349_ctrl_pins[] = { 3967 /* SCK, WS */ 3968 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3969}; 3970static const unsigned int ssi349_ctrl_mux[] = { 3971 SSI_SCK349_MARK, SSI_WS349_MARK, 3972}; 3973static const unsigned int ssi4_data_pins[] = { 3974 /* SDATA */ 3975 RCAR_GP_PIN(6, 10), 3976}; 3977static const unsigned int ssi4_data_mux[] = { 3978 SSI_SDATA4_MARK, 3979}; 3980static const unsigned int ssi4_ctrl_pins[] = { 3981 /* SCK, WS */ 3982 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 3983}; 3984static const unsigned int ssi4_ctrl_mux[] = { 3985 SSI_SCK4_MARK, SSI_WS4_MARK, 3986}; 3987static const unsigned int ssi5_data_pins[] = { 3988 /* SDATA */ 3989 RCAR_GP_PIN(6, 13), 3990}; 3991static const unsigned int ssi5_data_mux[] = { 3992 SSI_SDATA5_MARK, 3993}; 3994static const unsigned int ssi5_ctrl_pins[] = { 3995 /* SCK, WS */ 3996 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3997}; 3998static const unsigned int ssi5_ctrl_mux[] = { 3999 SSI_SCK5_MARK, SSI_WS5_MARK, 4000}; 4001static const unsigned int ssi6_data_pins[] = { 4002 /* SDATA */ 4003 RCAR_GP_PIN(6, 16), 4004}; 4005static const unsigned int ssi6_data_mux[] = { 4006 SSI_SDATA6_MARK, 4007}; 4008static const unsigned int ssi6_ctrl_pins[] = { 4009 /* SCK, WS */ 4010 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 4011}; 4012static const unsigned int ssi6_ctrl_mux[] = { 4013 SSI_SCK6_MARK, SSI_WS6_MARK, 4014}; 4015static const unsigned int ssi7_data_pins[] = { 4016 /* SDATA */ 4017 RCAR_GP_PIN(6, 19), 4018}; 4019static const unsigned int ssi7_data_mux[] = { 4020 SSI_SDATA7_MARK, 4021}; 4022static const unsigned int ssi78_ctrl_pins[] = { 4023 /* SCK, WS */ 4024 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 4025}; 4026static const unsigned int ssi78_ctrl_mux[] = { 4027 SSI_SCK78_MARK, SSI_WS78_MARK, 4028}; 4029static const unsigned int ssi8_data_pins[] = { 4030 /* SDATA */ 4031 RCAR_GP_PIN(6, 20), 4032}; 4033static const unsigned int ssi8_data_mux[] = { 4034 SSI_SDATA8_MARK, 4035}; 4036static const unsigned int ssi9_data_a_pins[] = { 4037 /* SDATA */ 4038 RCAR_GP_PIN(6, 21), 4039}; 4040static const unsigned int ssi9_data_a_mux[] = { 4041 SSI_SDATA9_A_MARK, 4042}; 4043static const unsigned int ssi9_data_b_pins[] = { 4044 /* SDATA */ 4045 RCAR_GP_PIN(5, 14), 4046}; 4047static const unsigned int ssi9_data_b_mux[] = { 4048 SSI_SDATA9_B_MARK, 4049}; 4050static const unsigned int ssi9_ctrl_a_pins[] = { 4051 /* SCK, WS */ 4052 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 4053}; 4054static const unsigned int ssi9_ctrl_a_mux[] = { 4055 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 4056}; 4057static const unsigned int ssi9_ctrl_b_pins[] = { 4058 /* SCK, WS */ 4059 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 4060}; 4061static const unsigned int ssi9_ctrl_b_mux[] = { 4062 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4063}; 4064 4065/* - TMU -------------------------------------------------------------------- */ 4066static const unsigned int tmu_tclk1_a_pins[] = { 4067 /* TCLK */ 4068 RCAR_GP_PIN(6, 23), 4069}; 4070 4071static const unsigned int tmu_tclk1_a_mux[] = { 4072 TCLK1_A_MARK, 4073}; 4074 4075static const unsigned int tmu_tclk1_b_pins[] = { 4076 /* TCLK */ 4077 RCAR_GP_PIN(5, 19), 4078}; 4079 4080static const unsigned int tmu_tclk1_b_mux[] = { 4081 TCLK1_B_MARK, 4082}; 4083 4084static const unsigned int tmu_tclk2_a_pins[] = { 4085 /* TCLK */ 4086 RCAR_GP_PIN(6, 19), 4087}; 4088 4089static const unsigned int tmu_tclk2_a_mux[] = { 4090 TCLK2_A_MARK, 4091}; 4092 4093static const unsigned int tmu_tclk2_b_pins[] = { 4094 /* TCLK */ 4095 RCAR_GP_PIN(6, 28), 4096}; 4097 4098static const unsigned int tmu_tclk2_b_mux[] = { 4099 TCLK2_B_MARK, 4100}; 4101 4102/* - TPU ------------------------------------------------------------------- */ 4103static const unsigned int tpu_to0_pins[] = { 4104 /* TPU0TO0 */ 4105 RCAR_GP_PIN(6, 28), 4106}; 4107static const unsigned int tpu_to0_mux[] = { 4108 TPU0TO0_MARK, 4109}; 4110static const unsigned int tpu_to1_pins[] = { 4111 /* TPU0TO1 */ 4112 RCAR_GP_PIN(6, 29), 4113}; 4114static const unsigned int tpu_to1_mux[] = { 4115 TPU0TO1_MARK, 4116}; 4117static const unsigned int tpu_to2_pins[] = { 4118 /* TPU0TO2 */ 4119 RCAR_GP_PIN(6, 30), 4120}; 4121static const unsigned int tpu_to2_mux[] = { 4122 TPU0TO2_MARK, 4123}; 4124static const unsigned int tpu_to3_pins[] = { 4125 /* TPU0TO3 */ 4126 RCAR_GP_PIN(6, 31), 4127}; 4128static const unsigned int tpu_to3_mux[] = { 4129 TPU0TO3_MARK, 4130}; 4131 4132/* - USB0 ------------------------------------------------------------------- */ 4133static const unsigned int usb0_pins[] = { 4134 /* PWEN, OVC */ 4135 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4136}; 4137 4138static const unsigned int usb0_mux[] = { 4139 USB0_PWEN_MARK, USB0_OVC_MARK, 4140}; 4141 4142/* - USB1 ------------------------------------------------------------------- */ 4143static const unsigned int usb1_pins[] = { 4144 /* PWEN, OVC */ 4145 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4146}; 4147 4148static const unsigned int usb1_mux[] = { 4149 USB1_PWEN_MARK, USB1_OVC_MARK, 4150}; 4151 4152/* - USB30 ------------------------------------------------------------------ */ 4153static const unsigned int usb30_pins[] = { 4154 /* PWEN, OVC */ 4155 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4156}; 4157 4158static const unsigned int usb30_mux[] = { 4159 USB30_PWEN_MARK, USB30_OVC_MARK, 4160}; 4161 4162/* - VIN4 ------------------------------------------------------------------- */ 4163static const unsigned int vin4_data18_a_pins[] = { 4164 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4165 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4166 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4167 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4168 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4169 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4170 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4171 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4172 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4173}; 4174 4175static const unsigned int vin4_data18_a_mux[] = { 4176 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4177 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4178 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4179 VI4_DATA10_MARK, VI4_DATA11_MARK, 4180 VI4_DATA12_MARK, VI4_DATA13_MARK, 4181 VI4_DATA14_MARK, VI4_DATA15_MARK, 4182 VI4_DATA18_MARK, VI4_DATA19_MARK, 4183 VI4_DATA20_MARK, VI4_DATA21_MARK, 4184 VI4_DATA22_MARK, VI4_DATA23_MARK, 4185}; 4186 4187static const unsigned int vin4_data_a_pins[] = { 4188 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4189 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4190 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4191 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4192 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4193 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4194 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4195 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4196 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4197 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4198 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4199 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4200}; 4201 4202static const unsigned int vin4_data_a_mux[] = { 4203 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4204 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4205 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4206 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4207 VI4_DATA8_MARK, VI4_DATA9_MARK, 4208 VI4_DATA10_MARK, VI4_DATA11_MARK, 4209 VI4_DATA12_MARK, VI4_DATA13_MARK, 4210 VI4_DATA14_MARK, VI4_DATA15_MARK, 4211 VI4_DATA16_MARK, VI4_DATA17_MARK, 4212 VI4_DATA18_MARK, VI4_DATA19_MARK, 4213 VI4_DATA20_MARK, VI4_DATA21_MARK, 4214 VI4_DATA22_MARK, VI4_DATA23_MARK, 4215}; 4216 4217static const unsigned int vin4_data18_b_pins[] = { 4218 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4219 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4220 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4221 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4222 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4223 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4224 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4225 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4226 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4227}; 4228 4229static const unsigned int vin4_data18_b_mux[] = { 4230 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4231 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4232 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4233 VI4_DATA10_MARK, VI4_DATA11_MARK, 4234 VI4_DATA12_MARK, VI4_DATA13_MARK, 4235 VI4_DATA14_MARK, VI4_DATA15_MARK, 4236 VI4_DATA18_MARK, VI4_DATA19_MARK, 4237 VI4_DATA20_MARK, VI4_DATA21_MARK, 4238 VI4_DATA22_MARK, VI4_DATA23_MARK, 4239}; 4240 4241static const unsigned int vin4_data_b_pins[] = { 4242 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4243 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4244 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4245 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4246 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4247 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4248 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4249 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4250 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4251 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4252 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4253 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4254}; 4255 4256static const unsigned int vin4_data_b_mux[] = { 4257 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4258 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4259 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4260 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4261 VI4_DATA8_MARK, VI4_DATA9_MARK, 4262 VI4_DATA10_MARK, VI4_DATA11_MARK, 4263 VI4_DATA12_MARK, VI4_DATA13_MARK, 4264 VI4_DATA14_MARK, VI4_DATA15_MARK, 4265 VI4_DATA16_MARK, VI4_DATA17_MARK, 4266 VI4_DATA18_MARK, VI4_DATA19_MARK, 4267 VI4_DATA20_MARK, VI4_DATA21_MARK, 4268 VI4_DATA22_MARK, VI4_DATA23_MARK, 4269}; 4270 4271static const unsigned int vin4_sync_pins[] = { 4272 /* VSYNC_N, HSYNC_N */ 4273 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 4274}; 4275 4276static const unsigned int vin4_sync_mux[] = { 4277 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4278}; 4279 4280static const unsigned int vin4_field_pins[] = { 4281 RCAR_GP_PIN(1, 16), 4282}; 4283 4284static const unsigned int vin4_field_mux[] = { 4285 VI4_FIELD_MARK, 4286}; 4287 4288static const unsigned int vin4_clkenb_pins[] = { 4289 RCAR_GP_PIN(1, 19), 4290}; 4291 4292static const unsigned int vin4_clkenb_mux[] = { 4293 VI4_CLKENB_MARK, 4294}; 4295 4296static const unsigned int vin4_clk_pins[] = { 4297 RCAR_GP_PIN(1, 27), 4298}; 4299 4300static const unsigned int vin4_clk_mux[] = { 4301 VI4_CLK_MARK, 4302}; 4303 4304/* - VIN5 ------------------------------------------------------------------- */ 4305static const unsigned int vin5_data_pins[] = { 4306 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4307 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4308 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4309 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4310 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4311 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4312 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4313 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4314}; 4315 4316static const unsigned int vin5_data_mux[] = { 4317 VI5_DATA0_MARK, VI5_DATA1_MARK, 4318 VI5_DATA2_MARK, VI5_DATA3_MARK, 4319 VI5_DATA4_MARK, VI5_DATA5_MARK, 4320 VI5_DATA6_MARK, VI5_DATA7_MARK, 4321 VI5_DATA8_MARK, VI5_DATA9_MARK, 4322 VI5_DATA10_MARK, VI5_DATA11_MARK, 4323 VI5_DATA12_MARK, VI5_DATA13_MARK, 4324 VI5_DATA14_MARK, VI5_DATA15_MARK, 4325}; 4326 4327static const unsigned int vin5_sync_pins[] = { 4328 /* VSYNC_N, HSYNC_N */ 4329 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 4330}; 4331 4332static const unsigned int vin5_sync_mux[] = { 4333 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4334}; 4335 4336static const unsigned int vin5_field_pins[] = { 4337 RCAR_GP_PIN(1, 11), 4338}; 4339 4340static const unsigned int vin5_field_mux[] = { 4341 VI5_FIELD_MARK, 4342}; 4343 4344static const unsigned int vin5_clkenb_pins[] = { 4345 RCAR_GP_PIN(1, 20), 4346}; 4347 4348static const unsigned int vin5_clkenb_mux[] = { 4349 VI5_CLKENB_MARK, 4350}; 4351 4352static const unsigned int vin5_clk_pins[] = { 4353 RCAR_GP_PIN(1, 21), 4354}; 4355 4356static const unsigned int vin5_clk_mux[] = { 4357 VI5_CLK_MARK, 4358}; 4359 4360static const struct { 4361 struct sh_pfc_pin_group common[326]; 4362#ifdef CONFIG_PINCTRL_PFC_R8A77965 4363 struct sh_pfc_pin_group automotive[31]; 4364#endif 4365} pinmux_groups = { 4366 .common = { 4367 SH_PFC_PIN_GROUP(audio_clk_a_a), 4368 SH_PFC_PIN_GROUP(audio_clk_a_b), 4369 SH_PFC_PIN_GROUP(audio_clk_a_c), 4370 SH_PFC_PIN_GROUP(audio_clk_b_a), 4371 SH_PFC_PIN_GROUP(audio_clk_b_b), 4372 SH_PFC_PIN_GROUP(audio_clk_c_a), 4373 SH_PFC_PIN_GROUP(audio_clk_c_b), 4374 SH_PFC_PIN_GROUP(audio_clkout_a), 4375 SH_PFC_PIN_GROUP(audio_clkout_b), 4376 SH_PFC_PIN_GROUP(audio_clkout_c), 4377 SH_PFC_PIN_GROUP(audio_clkout_d), 4378 SH_PFC_PIN_GROUP(audio_clkout1_a), 4379 SH_PFC_PIN_GROUP(audio_clkout1_b), 4380 SH_PFC_PIN_GROUP(audio_clkout2_a), 4381 SH_PFC_PIN_GROUP(audio_clkout2_b), 4382 SH_PFC_PIN_GROUP(audio_clkout3_a), 4383 SH_PFC_PIN_GROUP(audio_clkout3_b), 4384 SH_PFC_PIN_GROUP(avb_link), 4385 SH_PFC_PIN_GROUP(avb_magic), 4386 SH_PFC_PIN_GROUP(avb_phy_int), 4387 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4388 SH_PFC_PIN_GROUP(avb_mdio), 4389 SH_PFC_PIN_GROUP(avb_mii), 4390 SH_PFC_PIN_GROUP(avb_avtp_pps), 4391 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4392 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4393 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4394 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4395 SH_PFC_PIN_GROUP(can0_data_a), 4396 SH_PFC_PIN_GROUP(can0_data_b), 4397 SH_PFC_PIN_GROUP(can1_data), 4398 SH_PFC_PIN_GROUP(can_clk), 4399 SH_PFC_PIN_GROUP(canfd0_data_a), 4400 SH_PFC_PIN_GROUP(canfd0_data_b), 4401 SH_PFC_PIN_GROUP(canfd1_data), 4402 SH_PFC_PIN_GROUP(du_rgb666), 4403 SH_PFC_PIN_GROUP(du_rgb888), 4404 SH_PFC_PIN_GROUP(du_clk_out_0), 4405 SH_PFC_PIN_GROUP(du_clk_out_1), 4406 SH_PFC_PIN_GROUP(du_sync), 4407 SH_PFC_PIN_GROUP(du_oddf), 4408 SH_PFC_PIN_GROUP(du_cde), 4409 SH_PFC_PIN_GROUP(du_disp), 4410 SH_PFC_PIN_GROUP(hscif0_data), 4411 SH_PFC_PIN_GROUP(hscif0_clk), 4412 SH_PFC_PIN_GROUP(hscif0_ctrl), 4413 SH_PFC_PIN_GROUP(hscif1_data_a), 4414 SH_PFC_PIN_GROUP(hscif1_clk_a), 4415 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4416 SH_PFC_PIN_GROUP(hscif1_data_b), 4417 SH_PFC_PIN_GROUP(hscif1_clk_b), 4418 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4419 SH_PFC_PIN_GROUP(hscif2_data_a), 4420 SH_PFC_PIN_GROUP(hscif2_clk_a), 4421 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4422 SH_PFC_PIN_GROUP(hscif2_data_b), 4423 SH_PFC_PIN_GROUP(hscif2_clk_b), 4424 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4425 SH_PFC_PIN_GROUP(hscif2_data_c), 4426 SH_PFC_PIN_GROUP(hscif2_clk_c), 4427 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4428 SH_PFC_PIN_GROUP(hscif3_data_a), 4429 SH_PFC_PIN_GROUP(hscif3_clk), 4430 SH_PFC_PIN_GROUP(hscif3_ctrl), 4431 SH_PFC_PIN_GROUP(hscif3_data_b), 4432 SH_PFC_PIN_GROUP(hscif3_data_c), 4433 SH_PFC_PIN_GROUP(hscif3_data_d), 4434 SH_PFC_PIN_GROUP(hscif4_data_a), 4435 SH_PFC_PIN_GROUP(hscif4_clk), 4436 SH_PFC_PIN_GROUP(hscif4_ctrl), 4437 SH_PFC_PIN_GROUP(hscif4_data_b), 4438 SH_PFC_PIN_GROUP(i2c0), 4439 SH_PFC_PIN_GROUP(i2c1_a), 4440 SH_PFC_PIN_GROUP(i2c1_b), 4441 SH_PFC_PIN_GROUP(i2c2_a), 4442 SH_PFC_PIN_GROUP(i2c2_b), 4443 SH_PFC_PIN_GROUP(i2c3), 4444 SH_PFC_PIN_GROUP(i2c5), 4445 SH_PFC_PIN_GROUP(i2c6_a), 4446 SH_PFC_PIN_GROUP(i2c6_b), 4447 SH_PFC_PIN_GROUP(i2c6_c), 4448 SH_PFC_PIN_GROUP(intc_ex_irq0), 4449 SH_PFC_PIN_GROUP(intc_ex_irq1), 4450 SH_PFC_PIN_GROUP(intc_ex_irq2), 4451 SH_PFC_PIN_GROUP(intc_ex_irq3), 4452 SH_PFC_PIN_GROUP(intc_ex_irq4), 4453 SH_PFC_PIN_GROUP(intc_ex_irq5), 4454 SH_PFC_PIN_GROUP(msiof0_clk), 4455 SH_PFC_PIN_GROUP(msiof0_sync), 4456 SH_PFC_PIN_GROUP(msiof0_ss1), 4457 SH_PFC_PIN_GROUP(msiof0_ss2), 4458 SH_PFC_PIN_GROUP(msiof0_txd), 4459 SH_PFC_PIN_GROUP(msiof0_rxd), 4460 SH_PFC_PIN_GROUP(msiof1_clk_a), 4461 SH_PFC_PIN_GROUP(msiof1_sync_a), 4462 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4463 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4464 SH_PFC_PIN_GROUP(msiof1_txd_a), 4465 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4466 SH_PFC_PIN_GROUP(msiof1_clk_b), 4467 SH_PFC_PIN_GROUP(msiof1_sync_b), 4468 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4469 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4470 SH_PFC_PIN_GROUP(msiof1_txd_b), 4471 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4472 SH_PFC_PIN_GROUP(msiof1_clk_c), 4473 SH_PFC_PIN_GROUP(msiof1_sync_c), 4474 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4475 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4476 SH_PFC_PIN_GROUP(msiof1_txd_c), 4477 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4478 SH_PFC_PIN_GROUP(msiof1_clk_d), 4479 SH_PFC_PIN_GROUP(msiof1_sync_d), 4480 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4481 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4482 SH_PFC_PIN_GROUP(msiof1_txd_d), 4483 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4484 SH_PFC_PIN_GROUP(msiof1_clk_e), 4485 SH_PFC_PIN_GROUP(msiof1_sync_e), 4486 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4487 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4488 SH_PFC_PIN_GROUP(msiof1_txd_e), 4489 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4490 SH_PFC_PIN_GROUP(msiof1_clk_f), 4491 SH_PFC_PIN_GROUP(msiof1_sync_f), 4492 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4493 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4494 SH_PFC_PIN_GROUP(msiof1_txd_f), 4495 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4496 SH_PFC_PIN_GROUP(msiof1_clk_g), 4497 SH_PFC_PIN_GROUP(msiof1_sync_g), 4498 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4499 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4500 SH_PFC_PIN_GROUP(msiof1_txd_g), 4501 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4502 SH_PFC_PIN_GROUP(msiof2_clk_a), 4503 SH_PFC_PIN_GROUP(msiof2_sync_a), 4504 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4505 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4506 SH_PFC_PIN_GROUP(msiof2_txd_a), 4507 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4508 SH_PFC_PIN_GROUP(msiof2_clk_b), 4509 SH_PFC_PIN_GROUP(msiof2_sync_b), 4510 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4511 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4512 SH_PFC_PIN_GROUP(msiof2_txd_b), 4513 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4514 SH_PFC_PIN_GROUP(msiof2_clk_c), 4515 SH_PFC_PIN_GROUP(msiof2_sync_c), 4516 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4517 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4518 SH_PFC_PIN_GROUP(msiof2_txd_c), 4519 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4520 SH_PFC_PIN_GROUP(msiof2_clk_d), 4521 SH_PFC_PIN_GROUP(msiof2_sync_d), 4522 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4523 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4524 SH_PFC_PIN_GROUP(msiof2_txd_d), 4525 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4526 SH_PFC_PIN_GROUP(msiof3_clk_a), 4527 SH_PFC_PIN_GROUP(msiof3_sync_a), 4528 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4529 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4530 SH_PFC_PIN_GROUP(msiof3_txd_a), 4531 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4532 SH_PFC_PIN_GROUP(msiof3_clk_b), 4533 SH_PFC_PIN_GROUP(msiof3_sync_b), 4534 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4535 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4536 SH_PFC_PIN_GROUP(msiof3_txd_b), 4537 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4538 SH_PFC_PIN_GROUP(msiof3_clk_c), 4539 SH_PFC_PIN_GROUP(msiof3_sync_c), 4540 SH_PFC_PIN_GROUP(msiof3_txd_c), 4541 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4542 SH_PFC_PIN_GROUP(msiof3_clk_d), 4543 SH_PFC_PIN_GROUP(msiof3_sync_d), 4544 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4545 SH_PFC_PIN_GROUP(msiof3_txd_d), 4546 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4547 SH_PFC_PIN_GROUP(msiof3_clk_e), 4548 SH_PFC_PIN_GROUP(msiof3_sync_e), 4549 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4550 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4551 SH_PFC_PIN_GROUP(msiof3_txd_e), 4552 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4553 SH_PFC_PIN_GROUP(pwm0), 4554 SH_PFC_PIN_GROUP(pwm1_a), 4555 SH_PFC_PIN_GROUP(pwm1_b), 4556 SH_PFC_PIN_GROUP(pwm2_a), 4557 SH_PFC_PIN_GROUP(pwm2_b), 4558 SH_PFC_PIN_GROUP(pwm3_a), 4559 SH_PFC_PIN_GROUP(pwm3_b), 4560 SH_PFC_PIN_GROUP(pwm4_a), 4561 SH_PFC_PIN_GROUP(pwm4_b), 4562 SH_PFC_PIN_GROUP(pwm5_a), 4563 SH_PFC_PIN_GROUP(pwm5_b), 4564 SH_PFC_PIN_GROUP(pwm6_a), 4565 SH_PFC_PIN_GROUP(pwm6_b), 4566 SH_PFC_PIN_GROUP(qspi0_ctrl), 4567 BUS_DATA_PIN_GROUP(qspi0_data, 2), 4568 BUS_DATA_PIN_GROUP(qspi0_data, 4), 4569 SH_PFC_PIN_GROUP(qspi1_ctrl), 4570 BUS_DATA_PIN_GROUP(qspi1_data, 2), 4571 BUS_DATA_PIN_GROUP(qspi1_data, 4), 4572 SH_PFC_PIN_GROUP(sata0_devslp_a), 4573 SH_PFC_PIN_GROUP(sata0_devslp_b), 4574 SH_PFC_PIN_GROUP(scif0_data), 4575 SH_PFC_PIN_GROUP(scif0_clk), 4576 SH_PFC_PIN_GROUP(scif0_ctrl), 4577 SH_PFC_PIN_GROUP(scif1_data_a), 4578 SH_PFC_PIN_GROUP(scif1_clk), 4579 SH_PFC_PIN_GROUP(scif1_ctrl), 4580 SH_PFC_PIN_GROUP(scif1_data_b), 4581 SH_PFC_PIN_GROUP(scif2_data_a), 4582 SH_PFC_PIN_GROUP(scif2_clk), 4583 SH_PFC_PIN_GROUP(scif2_data_b), 4584 SH_PFC_PIN_GROUP(scif3_data_a), 4585 SH_PFC_PIN_GROUP(scif3_clk), 4586 SH_PFC_PIN_GROUP(scif3_ctrl), 4587 SH_PFC_PIN_GROUP(scif3_data_b), 4588 SH_PFC_PIN_GROUP(scif4_data_a), 4589 SH_PFC_PIN_GROUP(scif4_clk_a), 4590 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4591 SH_PFC_PIN_GROUP(scif4_data_b), 4592 SH_PFC_PIN_GROUP(scif4_clk_b), 4593 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4594 SH_PFC_PIN_GROUP(scif4_data_c), 4595 SH_PFC_PIN_GROUP(scif4_clk_c), 4596 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4597 SH_PFC_PIN_GROUP(scif5_data_a), 4598 SH_PFC_PIN_GROUP(scif5_clk_a), 4599 SH_PFC_PIN_GROUP(scif5_data_b), 4600 SH_PFC_PIN_GROUP(scif5_clk_b), 4601 SH_PFC_PIN_GROUP(scif_clk_a), 4602 SH_PFC_PIN_GROUP(scif_clk_b), 4603 BUS_DATA_PIN_GROUP(sdhi0_data, 1), 4604 BUS_DATA_PIN_GROUP(sdhi0_data, 4), 4605 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4606 SH_PFC_PIN_GROUP(sdhi0_cd), 4607 SH_PFC_PIN_GROUP(sdhi0_wp), 4608 BUS_DATA_PIN_GROUP(sdhi1_data, 1), 4609 BUS_DATA_PIN_GROUP(sdhi1_data, 4), 4610 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4611 SH_PFC_PIN_GROUP(sdhi1_cd), 4612 SH_PFC_PIN_GROUP(sdhi1_wp), 4613 BUS_DATA_PIN_GROUP(sdhi2_data, 1), 4614 BUS_DATA_PIN_GROUP(sdhi2_data, 4), 4615 BUS_DATA_PIN_GROUP(sdhi2_data, 8), 4616 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4617 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4618 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4619 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4620 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4621 SH_PFC_PIN_GROUP(sdhi2_ds), 4622 BUS_DATA_PIN_GROUP(sdhi3_data, 1), 4623 BUS_DATA_PIN_GROUP(sdhi3_data, 4), 4624 BUS_DATA_PIN_GROUP(sdhi3_data, 8), 4625 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4626 SH_PFC_PIN_GROUP(sdhi3_cd), 4627 SH_PFC_PIN_GROUP(sdhi3_wp), 4628 SH_PFC_PIN_GROUP(sdhi3_ds), 4629 SH_PFC_PIN_GROUP(ssi0_data), 4630 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4631 SH_PFC_PIN_GROUP(ssi1_data_a), 4632 SH_PFC_PIN_GROUP(ssi1_data_b), 4633 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4634 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4635 SH_PFC_PIN_GROUP(ssi2_data_a), 4636 SH_PFC_PIN_GROUP(ssi2_data_b), 4637 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4638 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4639 SH_PFC_PIN_GROUP(ssi3_data), 4640 SH_PFC_PIN_GROUP(ssi349_ctrl), 4641 SH_PFC_PIN_GROUP(ssi4_data), 4642 SH_PFC_PIN_GROUP(ssi4_ctrl), 4643 SH_PFC_PIN_GROUP(ssi5_data), 4644 SH_PFC_PIN_GROUP(ssi5_ctrl), 4645 SH_PFC_PIN_GROUP(ssi6_data), 4646 SH_PFC_PIN_GROUP(ssi6_ctrl), 4647 SH_PFC_PIN_GROUP(ssi7_data), 4648 SH_PFC_PIN_GROUP(ssi78_ctrl), 4649 SH_PFC_PIN_GROUP(ssi8_data), 4650 SH_PFC_PIN_GROUP(ssi9_data_a), 4651 SH_PFC_PIN_GROUP(ssi9_data_b), 4652 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4653 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4654 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4655 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4656 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4657 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4658 SH_PFC_PIN_GROUP(tpu_to0), 4659 SH_PFC_PIN_GROUP(tpu_to1), 4660 SH_PFC_PIN_GROUP(tpu_to2), 4661 SH_PFC_PIN_GROUP(tpu_to3), 4662 SH_PFC_PIN_GROUP(usb0), 4663 SH_PFC_PIN_GROUP(usb1), 4664 SH_PFC_PIN_GROUP(usb30), 4665 BUS_DATA_PIN_GROUP(vin4_data, 8, _a), 4666 BUS_DATA_PIN_GROUP(vin4_data, 10, _a), 4667 BUS_DATA_PIN_GROUP(vin4_data, 12, _a), 4668 BUS_DATA_PIN_GROUP(vin4_data, 16, _a), 4669 SH_PFC_PIN_GROUP(vin4_data18_a), 4670 BUS_DATA_PIN_GROUP(vin4_data, 20, _a), 4671 BUS_DATA_PIN_GROUP(vin4_data, 24, _a), 4672 BUS_DATA_PIN_GROUP(vin4_data, 8, _b), 4673 BUS_DATA_PIN_GROUP(vin4_data, 10, _b), 4674 BUS_DATA_PIN_GROUP(vin4_data, 12, _b), 4675 BUS_DATA_PIN_GROUP(vin4_data, 16, _b), 4676 SH_PFC_PIN_GROUP(vin4_data18_b), 4677 BUS_DATA_PIN_GROUP(vin4_data, 20, _b), 4678 BUS_DATA_PIN_GROUP(vin4_data, 24, _b), 4679 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), 4680 SH_PFC_PIN_GROUP(vin4_sync), 4681 SH_PFC_PIN_GROUP(vin4_field), 4682 SH_PFC_PIN_GROUP(vin4_clkenb), 4683 SH_PFC_PIN_GROUP(vin4_clk), 4684 BUS_DATA_PIN_GROUP(vin5_data, 8), 4685 BUS_DATA_PIN_GROUP(vin5_data, 10), 4686 BUS_DATA_PIN_GROUP(vin5_data, 12), 4687 BUS_DATA_PIN_GROUP(vin5_data, 16), 4688 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), 4689 SH_PFC_PIN_GROUP(vin5_sync), 4690 SH_PFC_PIN_GROUP(vin5_field), 4691 SH_PFC_PIN_GROUP(vin5_clkenb), 4692 SH_PFC_PIN_GROUP(vin5_clk), 4693 }, 4694#ifdef CONFIG_PINCTRL_PFC_R8A77965 4695 .automotive = { 4696 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4697 SH_PFC_PIN_GROUP(drif0_data0_a), 4698 SH_PFC_PIN_GROUP(drif0_data1_a), 4699 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4700 SH_PFC_PIN_GROUP(drif0_data0_b), 4701 SH_PFC_PIN_GROUP(drif0_data1_b), 4702 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4703 SH_PFC_PIN_GROUP(drif0_data0_c), 4704 SH_PFC_PIN_GROUP(drif0_data1_c), 4705 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4706 SH_PFC_PIN_GROUP(drif1_data0_a), 4707 SH_PFC_PIN_GROUP(drif1_data1_a), 4708 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4709 SH_PFC_PIN_GROUP(drif1_data0_b), 4710 SH_PFC_PIN_GROUP(drif1_data1_b), 4711 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4712 SH_PFC_PIN_GROUP(drif1_data0_c), 4713 SH_PFC_PIN_GROUP(drif1_data1_c), 4714 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4715 SH_PFC_PIN_GROUP(drif2_data0_a), 4716 SH_PFC_PIN_GROUP(drif2_data1_a), 4717 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4718 SH_PFC_PIN_GROUP(drif2_data0_b), 4719 SH_PFC_PIN_GROUP(drif2_data1_b), 4720 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4721 SH_PFC_PIN_GROUP(drif3_data0_a), 4722 SH_PFC_PIN_GROUP(drif3_data1_a), 4723 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4724 SH_PFC_PIN_GROUP(drif3_data0_b), 4725 SH_PFC_PIN_GROUP(drif3_data1_b), 4726 SH_PFC_PIN_GROUP(mlb_3pin), 4727 } 4728#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4729}; 4730 4731static const char * const audio_clk_groups[] = { 4732 "audio_clk_a_a", 4733 "audio_clk_a_b", 4734 "audio_clk_a_c", 4735 "audio_clk_b_a", 4736 "audio_clk_b_b", 4737 "audio_clk_c_a", 4738 "audio_clk_c_b", 4739 "audio_clkout_a", 4740 "audio_clkout_b", 4741 "audio_clkout_c", 4742 "audio_clkout_d", 4743 "audio_clkout1_a", 4744 "audio_clkout1_b", 4745 "audio_clkout2_a", 4746 "audio_clkout2_b", 4747 "audio_clkout3_a", 4748 "audio_clkout3_b", 4749}; 4750 4751static const char * const avb_groups[] = { 4752 "avb_link", 4753 "avb_magic", 4754 "avb_phy_int", 4755 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4756 "avb_mdio", 4757 "avb_mii", 4758 "avb_avtp_pps", 4759 "avb_avtp_match_a", 4760 "avb_avtp_capture_a", 4761 "avb_avtp_match_b", 4762 "avb_avtp_capture_b", 4763}; 4764 4765static const char * const can0_groups[] = { 4766 "can0_data_a", 4767 "can0_data_b", 4768}; 4769 4770static const char * const can1_groups[] = { 4771 "can1_data", 4772}; 4773 4774static const char * const can_clk_groups[] = { 4775 "can_clk", 4776}; 4777 4778static const char * const canfd0_groups[] = { 4779 "canfd0_data_a", 4780 "canfd0_data_b", 4781}; 4782 4783static const char * const canfd1_groups[] = { 4784 "canfd1_data", 4785}; 4786 4787#ifdef CONFIG_PINCTRL_PFC_R8A77965 4788static const char * const drif0_groups[] = { 4789 "drif0_ctrl_a", 4790 "drif0_data0_a", 4791 "drif0_data1_a", 4792 "drif0_ctrl_b", 4793 "drif0_data0_b", 4794 "drif0_data1_b", 4795 "drif0_ctrl_c", 4796 "drif0_data0_c", 4797 "drif0_data1_c", 4798}; 4799 4800static const char * const drif1_groups[] = { 4801 "drif1_ctrl_a", 4802 "drif1_data0_a", 4803 "drif1_data1_a", 4804 "drif1_ctrl_b", 4805 "drif1_data0_b", 4806 "drif1_data1_b", 4807 "drif1_ctrl_c", 4808 "drif1_data0_c", 4809 "drif1_data1_c", 4810}; 4811 4812static const char * const drif2_groups[] = { 4813 "drif2_ctrl_a", 4814 "drif2_data0_a", 4815 "drif2_data1_a", 4816 "drif2_ctrl_b", 4817 "drif2_data0_b", 4818 "drif2_data1_b", 4819}; 4820 4821static const char * const drif3_groups[] = { 4822 "drif3_ctrl_a", 4823 "drif3_data0_a", 4824 "drif3_data1_a", 4825 "drif3_ctrl_b", 4826 "drif3_data0_b", 4827 "drif3_data1_b", 4828}; 4829#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4830 4831static const char * const du_groups[] = { 4832 "du_rgb666", 4833 "du_rgb888", 4834 "du_clk_out_0", 4835 "du_clk_out_1", 4836 "du_sync", 4837 "du_oddf", 4838 "du_cde", 4839 "du_disp", 4840}; 4841 4842static const char * const hscif0_groups[] = { 4843 "hscif0_data", 4844 "hscif0_clk", 4845 "hscif0_ctrl", 4846}; 4847 4848static const char * const hscif1_groups[] = { 4849 "hscif1_data_a", 4850 "hscif1_clk_a", 4851 "hscif1_ctrl_a", 4852 "hscif1_data_b", 4853 "hscif1_clk_b", 4854 "hscif1_ctrl_b", 4855}; 4856 4857static const char * const hscif2_groups[] = { 4858 "hscif2_data_a", 4859 "hscif2_clk_a", 4860 "hscif2_ctrl_a", 4861 "hscif2_data_b", 4862 "hscif2_clk_b", 4863 "hscif2_ctrl_b", 4864 "hscif2_data_c", 4865 "hscif2_clk_c", 4866 "hscif2_ctrl_c", 4867}; 4868 4869static const char * const hscif3_groups[] = { 4870 "hscif3_data_a", 4871 "hscif3_clk", 4872 "hscif3_ctrl", 4873 "hscif3_data_b", 4874 "hscif3_data_c", 4875 "hscif3_data_d", 4876}; 4877 4878static const char * const hscif4_groups[] = { 4879 "hscif4_data_a", 4880 "hscif4_clk", 4881 "hscif4_ctrl", 4882 "hscif4_data_b", 4883}; 4884 4885static const char * const i2c0_groups[] = { 4886 "i2c0", 4887}; 4888 4889static const char * const i2c1_groups[] = { 4890 "i2c1_a", 4891 "i2c1_b", 4892}; 4893 4894static const char * const i2c2_groups[] = { 4895 "i2c2_a", 4896 "i2c2_b", 4897}; 4898 4899static const char * const i2c3_groups[] = { 4900 "i2c3", 4901}; 4902 4903static const char * const i2c5_groups[] = { 4904 "i2c5", 4905}; 4906 4907static const char * const i2c6_groups[] = { 4908 "i2c6_a", 4909 "i2c6_b", 4910 "i2c6_c", 4911}; 4912 4913static const char * const intc_ex_groups[] = { 4914 "intc_ex_irq0", 4915 "intc_ex_irq1", 4916 "intc_ex_irq2", 4917 "intc_ex_irq3", 4918 "intc_ex_irq4", 4919 "intc_ex_irq5", 4920}; 4921 4922#ifdef CONFIG_PINCTRL_PFC_R8A77965 4923static const char * const mlb_3pin_groups[] = { 4924 "mlb_3pin", 4925}; 4926#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4927 4928static const char * const msiof0_groups[] = { 4929 "msiof0_clk", 4930 "msiof0_sync", 4931 "msiof0_ss1", 4932 "msiof0_ss2", 4933 "msiof0_txd", 4934 "msiof0_rxd", 4935}; 4936 4937static const char * const msiof1_groups[] = { 4938 "msiof1_clk_a", 4939 "msiof1_sync_a", 4940 "msiof1_ss1_a", 4941 "msiof1_ss2_a", 4942 "msiof1_txd_a", 4943 "msiof1_rxd_a", 4944 "msiof1_clk_b", 4945 "msiof1_sync_b", 4946 "msiof1_ss1_b", 4947 "msiof1_ss2_b", 4948 "msiof1_txd_b", 4949 "msiof1_rxd_b", 4950 "msiof1_clk_c", 4951 "msiof1_sync_c", 4952 "msiof1_ss1_c", 4953 "msiof1_ss2_c", 4954 "msiof1_txd_c", 4955 "msiof1_rxd_c", 4956 "msiof1_clk_d", 4957 "msiof1_sync_d", 4958 "msiof1_ss1_d", 4959 "msiof1_ss2_d", 4960 "msiof1_txd_d", 4961 "msiof1_rxd_d", 4962 "msiof1_clk_e", 4963 "msiof1_sync_e", 4964 "msiof1_ss1_e", 4965 "msiof1_ss2_e", 4966 "msiof1_txd_e", 4967 "msiof1_rxd_e", 4968 "msiof1_clk_f", 4969 "msiof1_sync_f", 4970 "msiof1_ss1_f", 4971 "msiof1_ss2_f", 4972 "msiof1_txd_f", 4973 "msiof1_rxd_f", 4974 "msiof1_clk_g", 4975 "msiof1_sync_g", 4976 "msiof1_ss1_g", 4977 "msiof1_ss2_g", 4978 "msiof1_txd_g", 4979 "msiof1_rxd_g", 4980}; 4981 4982static const char * const msiof2_groups[] = { 4983 "msiof2_clk_a", 4984 "msiof2_sync_a", 4985 "msiof2_ss1_a", 4986 "msiof2_ss2_a", 4987 "msiof2_txd_a", 4988 "msiof2_rxd_a", 4989 "msiof2_clk_b", 4990 "msiof2_sync_b", 4991 "msiof2_ss1_b", 4992 "msiof2_ss2_b", 4993 "msiof2_txd_b", 4994 "msiof2_rxd_b", 4995 "msiof2_clk_c", 4996 "msiof2_sync_c", 4997 "msiof2_ss1_c", 4998 "msiof2_ss2_c", 4999 "msiof2_txd_c", 5000 "msiof2_rxd_c", 5001 "msiof2_clk_d", 5002 "msiof2_sync_d", 5003 "msiof2_ss1_d", 5004 "msiof2_ss2_d", 5005 "msiof2_txd_d", 5006 "msiof2_rxd_d", 5007}; 5008 5009static const char * const msiof3_groups[] = { 5010 "msiof3_clk_a", 5011 "msiof3_sync_a", 5012 "msiof3_ss1_a", 5013 "msiof3_ss2_a", 5014 "msiof3_txd_a", 5015 "msiof3_rxd_a", 5016 "msiof3_clk_b", 5017 "msiof3_sync_b", 5018 "msiof3_ss1_b", 5019 "msiof3_ss2_b", 5020 "msiof3_txd_b", 5021 "msiof3_rxd_b", 5022 "msiof3_clk_c", 5023 "msiof3_sync_c", 5024 "msiof3_txd_c", 5025 "msiof3_rxd_c", 5026 "msiof3_clk_d", 5027 "msiof3_sync_d", 5028 "msiof3_ss1_d", 5029 "msiof3_txd_d", 5030 "msiof3_rxd_d", 5031 "msiof3_clk_e", 5032 "msiof3_sync_e", 5033 "msiof3_ss1_e", 5034 "msiof3_ss2_e", 5035 "msiof3_txd_e", 5036 "msiof3_rxd_e", 5037}; 5038 5039static const char * const pwm0_groups[] = { 5040 "pwm0", 5041}; 5042 5043static const char * const pwm1_groups[] = { 5044 "pwm1_a", 5045 "pwm1_b", 5046}; 5047 5048static const char * const pwm2_groups[] = { 5049 "pwm2_a", 5050 "pwm2_b", 5051}; 5052 5053static const char * const pwm3_groups[] = { 5054 "pwm3_a", 5055 "pwm3_b", 5056}; 5057 5058static const char * const pwm4_groups[] = { 5059 "pwm4_a", 5060 "pwm4_b", 5061}; 5062 5063static const char * const pwm5_groups[] = { 5064 "pwm5_a", 5065 "pwm5_b", 5066}; 5067 5068static const char * const pwm6_groups[] = { 5069 "pwm6_a", 5070 "pwm6_b", 5071}; 5072 5073static const char * const qspi0_groups[] = { 5074 "qspi0_ctrl", 5075 "qspi0_data2", 5076 "qspi0_data4", 5077}; 5078 5079static const char * const qspi1_groups[] = { 5080 "qspi1_ctrl", 5081 "qspi1_data2", 5082 "qspi1_data4", 5083}; 5084 5085static const char * const sata0_groups[] = { 5086 "sata0_devslp_a", 5087 "sata0_devslp_b", 5088}; 5089 5090static const char * const scif0_groups[] = { 5091 "scif0_data", 5092 "scif0_clk", 5093 "scif0_ctrl", 5094}; 5095 5096static const char * const scif1_groups[] = { 5097 "scif1_data_a", 5098 "scif1_clk", 5099 "scif1_ctrl", 5100 "scif1_data_b", 5101}; 5102static const char * const scif2_groups[] = { 5103 "scif2_data_a", 5104 "scif2_clk", 5105 "scif2_data_b", 5106}; 5107 5108static const char * const scif3_groups[] = { 5109 "scif3_data_a", 5110 "scif3_clk", 5111 "scif3_ctrl", 5112 "scif3_data_b", 5113}; 5114 5115static const char * const scif4_groups[] = { 5116 "scif4_data_a", 5117 "scif4_clk_a", 5118 "scif4_ctrl_a", 5119 "scif4_data_b", 5120 "scif4_clk_b", 5121 "scif4_ctrl_b", 5122 "scif4_data_c", 5123 "scif4_clk_c", 5124 "scif4_ctrl_c", 5125}; 5126 5127static const char * const scif5_groups[] = { 5128 "scif5_data_a", 5129 "scif5_clk_a", 5130 "scif5_data_b", 5131 "scif5_clk_b", 5132}; 5133 5134static const char * const scif_clk_groups[] = { 5135 "scif_clk_a", 5136 "scif_clk_b", 5137}; 5138 5139static const char * const sdhi0_groups[] = { 5140 "sdhi0_data1", 5141 "sdhi0_data4", 5142 "sdhi0_ctrl", 5143 "sdhi0_cd", 5144 "sdhi0_wp", 5145}; 5146 5147static const char * const sdhi1_groups[] = { 5148 "sdhi1_data1", 5149 "sdhi1_data4", 5150 "sdhi1_ctrl", 5151 "sdhi1_cd", 5152 "sdhi1_wp", 5153}; 5154 5155static const char * const sdhi2_groups[] = { 5156 "sdhi2_data1", 5157 "sdhi2_data4", 5158 "sdhi2_data8", 5159 "sdhi2_ctrl", 5160 "sdhi2_cd_a", 5161 "sdhi2_wp_a", 5162 "sdhi2_cd_b", 5163 "sdhi2_wp_b", 5164 "sdhi2_ds", 5165}; 5166 5167static const char * const sdhi3_groups[] = { 5168 "sdhi3_data1", 5169 "sdhi3_data4", 5170 "sdhi3_data8", 5171 "sdhi3_ctrl", 5172 "sdhi3_cd", 5173 "sdhi3_wp", 5174 "sdhi3_ds", 5175}; 5176 5177static const char * const ssi_groups[] = { 5178 "ssi0_data", 5179 "ssi01239_ctrl", 5180 "ssi1_data_a", 5181 "ssi1_data_b", 5182 "ssi1_ctrl_a", 5183 "ssi1_ctrl_b", 5184 "ssi2_data_a", 5185 "ssi2_data_b", 5186 "ssi2_ctrl_a", 5187 "ssi2_ctrl_b", 5188 "ssi3_data", 5189 "ssi349_ctrl", 5190 "ssi4_data", 5191 "ssi4_ctrl", 5192 "ssi5_data", 5193 "ssi5_ctrl", 5194 "ssi6_data", 5195 "ssi6_ctrl", 5196 "ssi7_data", 5197 "ssi78_ctrl", 5198 "ssi8_data", 5199 "ssi9_data_a", 5200 "ssi9_data_b", 5201 "ssi9_ctrl_a", 5202 "ssi9_ctrl_b", 5203}; 5204 5205static const char * const tmu_groups[] = { 5206 "tmu_tclk1_a", 5207 "tmu_tclk1_b", 5208 "tmu_tclk2_a", 5209 "tmu_tclk2_b", 5210}; 5211 5212static const char * const tpu_groups[] = { 5213 "tpu_to0", 5214 "tpu_to1", 5215 "tpu_to2", 5216 "tpu_to3", 5217}; 5218 5219static const char * const usb0_groups[] = { 5220 "usb0", 5221}; 5222 5223static const char * const usb1_groups[] = { 5224 "usb1", 5225}; 5226 5227static const char * const usb30_groups[] = { 5228 "usb30", 5229}; 5230 5231static const char * const vin4_groups[] = { 5232 "vin4_data8_a", 5233 "vin4_data10_a", 5234 "vin4_data12_a", 5235 "vin4_data16_a", 5236 "vin4_data18_a", 5237 "vin4_data20_a", 5238 "vin4_data24_a", 5239 "vin4_data8_b", 5240 "vin4_data10_b", 5241 "vin4_data12_b", 5242 "vin4_data16_b", 5243 "vin4_data18_b", 5244 "vin4_data20_b", 5245 "vin4_data24_b", 5246 "vin4_g8", 5247 "vin4_sync", 5248 "vin4_field", 5249 "vin4_clkenb", 5250 "vin4_clk", 5251}; 5252 5253static const char * const vin5_groups[] = { 5254 "vin5_data8", 5255 "vin5_data10", 5256 "vin5_data12", 5257 "vin5_data16", 5258 "vin5_high8", 5259 "vin5_sync", 5260 "vin5_field", 5261 "vin5_clkenb", 5262 "vin5_clk", 5263}; 5264 5265static const struct { 5266 struct sh_pfc_function common[53]; 5267#ifdef CONFIG_PINCTRL_PFC_R8A77965 5268 struct sh_pfc_function automotive[5]; 5269#endif 5270} pinmux_functions = { 5271 .common = { 5272 SH_PFC_FUNCTION(audio_clk), 5273 SH_PFC_FUNCTION(avb), 5274 SH_PFC_FUNCTION(can0), 5275 SH_PFC_FUNCTION(can1), 5276 SH_PFC_FUNCTION(can_clk), 5277 SH_PFC_FUNCTION(canfd0), 5278 SH_PFC_FUNCTION(canfd1), 5279 SH_PFC_FUNCTION(du), 5280 SH_PFC_FUNCTION(hscif0), 5281 SH_PFC_FUNCTION(hscif1), 5282 SH_PFC_FUNCTION(hscif2), 5283 SH_PFC_FUNCTION(hscif3), 5284 SH_PFC_FUNCTION(hscif4), 5285 SH_PFC_FUNCTION(i2c0), 5286 SH_PFC_FUNCTION(i2c1), 5287 SH_PFC_FUNCTION(i2c2), 5288 SH_PFC_FUNCTION(i2c3), 5289 SH_PFC_FUNCTION(i2c5), 5290 SH_PFC_FUNCTION(i2c6), 5291 SH_PFC_FUNCTION(intc_ex), 5292 SH_PFC_FUNCTION(msiof0), 5293 SH_PFC_FUNCTION(msiof1), 5294 SH_PFC_FUNCTION(msiof2), 5295 SH_PFC_FUNCTION(msiof3), 5296 SH_PFC_FUNCTION(pwm0), 5297 SH_PFC_FUNCTION(pwm1), 5298 SH_PFC_FUNCTION(pwm2), 5299 SH_PFC_FUNCTION(pwm3), 5300 SH_PFC_FUNCTION(pwm4), 5301 SH_PFC_FUNCTION(pwm5), 5302 SH_PFC_FUNCTION(pwm6), 5303 SH_PFC_FUNCTION(qspi0), 5304 SH_PFC_FUNCTION(qspi1), 5305 SH_PFC_FUNCTION(sata0), 5306 SH_PFC_FUNCTION(scif0), 5307 SH_PFC_FUNCTION(scif1), 5308 SH_PFC_FUNCTION(scif2), 5309 SH_PFC_FUNCTION(scif3), 5310 SH_PFC_FUNCTION(scif4), 5311 SH_PFC_FUNCTION(scif5), 5312 SH_PFC_FUNCTION(scif_clk), 5313 SH_PFC_FUNCTION(sdhi0), 5314 SH_PFC_FUNCTION(sdhi1), 5315 SH_PFC_FUNCTION(sdhi2), 5316 SH_PFC_FUNCTION(sdhi3), 5317 SH_PFC_FUNCTION(ssi), 5318 SH_PFC_FUNCTION(tmu), 5319 SH_PFC_FUNCTION(tpu), 5320 SH_PFC_FUNCTION(usb0), 5321 SH_PFC_FUNCTION(usb1), 5322 SH_PFC_FUNCTION(usb30), 5323 SH_PFC_FUNCTION(vin4), 5324 SH_PFC_FUNCTION(vin5), 5325 }, 5326#ifdef CONFIG_PINCTRL_PFC_R8A77965 5327 .automotive = { 5328 SH_PFC_FUNCTION(drif0), 5329 SH_PFC_FUNCTION(drif1), 5330 SH_PFC_FUNCTION(drif2), 5331 SH_PFC_FUNCTION(drif3), 5332 SH_PFC_FUNCTION(mlb_3pin), 5333 } 5334#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 5335}; 5336 5337static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5338#define F_(x, y) FN_##y 5339#define FM(x) FN_##x 5340 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, 5341 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5342 1, 1, 1, 1, 1), 5343 GROUP( 5344 /* GP0_31_16 RESERVED */ 5345 GP_0_15_FN, GPSR0_15, 5346 GP_0_14_FN, GPSR0_14, 5347 GP_0_13_FN, GPSR0_13, 5348 GP_0_12_FN, GPSR0_12, 5349 GP_0_11_FN, GPSR0_11, 5350 GP_0_10_FN, GPSR0_10, 5351 GP_0_9_FN, GPSR0_9, 5352 GP_0_8_FN, GPSR0_8, 5353 GP_0_7_FN, GPSR0_7, 5354 GP_0_6_FN, GPSR0_6, 5355 GP_0_5_FN, GPSR0_5, 5356 GP_0_4_FN, GPSR0_4, 5357 GP_0_3_FN, GPSR0_3, 5358 GP_0_2_FN, GPSR0_2, 5359 GP_0_1_FN, GPSR0_1, 5360 GP_0_0_FN, GPSR0_0, )) 5361 }, 5362 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5363 0, 0, 5364 0, 0, 5365 0, 0, 5366 GP_1_28_FN, GPSR1_28, 5367 GP_1_27_FN, GPSR1_27, 5368 GP_1_26_FN, GPSR1_26, 5369 GP_1_25_FN, GPSR1_25, 5370 GP_1_24_FN, GPSR1_24, 5371 GP_1_23_FN, GPSR1_23, 5372 GP_1_22_FN, GPSR1_22, 5373 GP_1_21_FN, GPSR1_21, 5374 GP_1_20_FN, GPSR1_20, 5375 GP_1_19_FN, GPSR1_19, 5376 GP_1_18_FN, GPSR1_18, 5377 GP_1_17_FN, GPSR1_17, 5378 GP_1_16_FN, GPSR1_16, 5379 GP_1_15_FN, GPSR1_15, 5380 GP_1_14_FN, GPSR1_14, 5381 GP_1_13_FN, GPSR1_13, 5382 GP_1_12_FN, GPSR1_12, 5383 GP_1_11_FN, GPSR1_11, 5384 GP_1_10_FN, GPSR1_10, 5385 GP_1_9_FN, GPSR1_9, 5386 GP_1_8_FN, GPSR1_8, 5387 GP_1_7_FN, GPSR1_7, 5388 GP_1_6_FN, GPSR1_6, 5389 GP_1_5_FN, GPSR1_5, 5390 GP_1_4_FN, GPSR1_4, 5391 GP_1_3_FN, GPSR1_3, 5392 GP_1_2_FN, GPSR1_2, 5393 GP_1_1_FN, GPSR1_1, 5394 GP_1_0_FN, GPSR1_0, )) 5395 }, 5396 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, 5397 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5398 1, 1, 1, 1), 5399 GROUP( 5400 /* GP2_31_15 RESERVED */ 5401 GP_2_14_FN, GPSR2_14, 5402 GP_2_13_FN, GPSR2_13, 5403 GP_2_12_FN, GPSR2_12, 5404 GP_2_11_FN, GPSR2_11, 5405 GP_2_10_FN, GPSR2_10, 5406 GP_2_9_FN, GPSR2_9, 5407 GP_2_8_FN, GPSR2_8, 5408 GP_2_7_FN, GPSR2_7, 5409 GP_2_6_FN, GPSR2_6, 5410 GP_2_5_FN, GPSR2_5, 5411 GP_2_4_FN, GPSR2_4, 5412 GP_2_3_FN, GPSR2_3, 5413 GP_2_2_FN, GPSR2_2, 5414 GP_2_1_FN, GPSR2_1, 5415 GP_2_0_FN, GPSR2_0, )) 5416 }, 5417 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, 5418 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5419 1, 1, 1, 1, 1), 5420 GROUP( 5421 /* GP3_31_16 RESERVED */ 5422 GP_3_15_FN, GPSR3_15, 5423 GP_3_14_FN, GPSR3_14, 5424 GP_3_13_FN, GPSR3_13, 5425 GP_3_12_FN, GPSR3_12, 5426 GP_3_11_FN, GPSR3_11, 5427 GP_3_10_FN, GPSR3_10, 5428 GP_3_9_FN, GPSR3_9, 5429 GP_3_8_FN, GPSR3_8, 5430 GP_3_7_FN, GPSR3_7, 5431 GP_3_6_FN, GPSR3_6, 5432 GP_3_5_FN, GPSR3_5, 5433 GP_3_4_FN, GPSR3_4, 5434 GP_3_3_FN, GPSR3_3, 5435 GP_3_2_FN, GPSR3_2, 5436 GP_3_1_FN, GPSR3_1, 5437 GP_3_0_FN, GPSR3_0, )) 5438 }, 5439 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, 5440 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5441 1, 1, 1, 1, 1, 1, 1), 5442 GROUP( 5443 /* GP4_31_18 RESERVED */ 5444 GP_4_17_FN, GPSR4_17, 5445 GP_4_16_FN, GPSR4_16, 5446 GP_4_15_FN, GPSR4_15, 5447 GP_4_14_FN, GPSR4_14, 5448 GP_4_13_FN, GPSR4_13, 5449 GP_4_12_FN, GPSR4_12, 5450 GP_4_11_FN, GPSR4_11, 5451 GP_4_10_FN, GPSR4_10, 5452 GP_4_9_FN, GPSR4_9, 5453 GP_4_8_FN, GPSR4_8, 5454 GP_4_7_FN, GPSR4_7, 5455 GP_4_6_FN, GPSR4_6, 5456 GP_4_5_FN, GPSR4_5, 5457 GP_4_4_FN, GPSR4_4, 5458 GP_4_3_FN, GPSR4_3, 5459 GP_4_2_FN, GPSR4_2, 5460 GP_4_1_FN, GPSR4_1, 5461 GP_4_0_FN, GPSR4_0, )) 5462 }, 5463 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5464 0, 0, 5465 0, 0, 5466 0, 0, 5467 0, 0, 5468 0, 0, 5469 0, 0, 5470 GP_5_25_FN, GPSR5_25, 5471 GP_5_24_FN, GPSR5_24, 5472 GP_5_23_FN, GPSR5_23, 5473 GP_5_22_FN, GPSR5_22, 5474 GP_5_21_FN, GPSR5_21, 5475 GP_5_20_FN, GPSR5_20, 5476 GP_5_19_FN, GPSR5_19, 5477 GP_5_18_FN, GPSR5_18, 5478 GP_5_17_FN, GPSR5_17, 5479 GP_5_16_FN, GPSR5_16, 5480 GP_5_15_FN, GPSR5_15, 5481 GP_5_14_FN, GPSR5_14, 5482 GP_5_13_FN, GPSR5_13, 5483 GP_5_12_FN, GPSR5_12, 5484 GP_5_11_FN, GPSR5_11, 5485 GP_5_10_FN, GPSR5_10, 5486 GP_5_9_FN, GPSR5_9, 5487 GP_5_8_FN, GPSR5_8, 5488 GP_5_7_FN, GPSR5_7, 5489 GP_5_6_FN, GPSR5_6, 5490 GP_5_5_FN, GPSR5_5, 5491 GP_5_4_FN, GPSR5_4, 5492 GP_5_3_FN, GPSR5_3, 5493 GP_5_2_FN, GPSR5_2, 5494 GP_5_1_FN, GPSR5_1, 5495 GP_5_0_FN, GPSR5_0, )) 5496 }, 5497 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5498 GP_6_31_FN, GPSR6_31, 5499 GP_6_30_FN, GPSR6_30, 5500 GP_6_29_FN, GPSR6_29, 5501 GP_6_28_FN, GPSR6_28, 5502 GP_6_27_FN, GPSR6_27, 5503 GP_6_26_FN, GPSR6_26, 5504 GP_6_25_FN, GPSR6_25, 5505 GP_6_24_FN, GPSR6_24, 5506 GP_6_23_FN, GPSR6_23, 5507 GP_6_22_FN, GPSR6_22, 5508 GP_6_21_FN, GPSR6_21, 5509 GP_6_20_FN, GPSR6_20, 5510 GP_6_19_FN, GPSR6_19, 5511 GP_6_18_FN, GPSR6_18, 5512 GP_6_17_FN, GPSR6_17, 5513 GP_6_16_FN, GPSR6_16, 5514 GP_6_15_FN, GPSR6_15, 5515 GP_6_14_FN, GPSR6_14, 5516 GP_6_13_FN, GPSR6_13, 5517 GP_6_12_FN, GPSR6_12, 5518 GP_6_11_FN, GPSR6_11, 5519 GP_6_10_FN, GPSR6_10, 5520 GP_6_9_FN, GPSR6_9, 5521 GP_6_8_FN, GPSR6_8, 5522 GP_6_7_FN, GPSR6_7, 5523 GP_6_6_FN, GPSR6_6, 5524 GP_6_5_FN, GPSR6_5, 5525 GP_6_4_FN, GPSR6_4, 5526 GP_6_3_FN, GPSR6_3, 5527 GP_6_2_FN, GPSR6_2, 5528 GP_6_1_FN, GPSR6_1, 5529 GP_6_0_FN, GPSR6_0, )) 5530 }, 5531 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32, 5532 GROUP(-28, 1, 1, 1, 1), 5533 GROUP( 5534 /* GP7_31_4 RESERVED */ 5535 GP_7_3_FN, GPSR7_3, 5536 GP_7_2_FN, GPSR7_2, 5537 GP_7_1_FN, GPSR7_1, 5538 GP_7_0_FN, GPSR7_0, )) 5539 }, 5540#undef F_ 5541#undef FM 5542 5543#define F_(x, y) x, 5544#define FM(x) FN_##x, 5545 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5546 IP0_31_28 5547 IP0_27_24 5548 IP0_23_20 5549 IP0_19_16 5550 IP0_15_12 5551 IP0_11_8 5552 IP0_7_4 5553 IP0_3_0 )) 5554 }, 5555 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5556 IP1_31_28 5557 IP1_27_24 5558 IP1_23_20 5559 IP1_19_16 5560 IP1_15_12 5561 IP1_11_8 5562 IP1_7_4 5563 IP1_3_0 )) 5564 }, 5565 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5566 IP2_31_28 5567 IP2_27_24 5568 IP2_23_20 5569 IP2_19_16 5570 IP2_15_12 5571 IP2_11_8 5572 IP2_7_4 5573 IP2_3_0 )) 5574 }, 5575 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5576 IP3_31_28 5577 IP3_27_24 5578 IP3_23_20 5579 IP3_19_16 5580 IP3_15_12 5581 IP3_11_8 5582 IP3_7_4 5583 IP3_3_0 )) 5584 }, 5585 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5586 IP4_31_28 5587 IP4_27_24 5588 IP4_23_20 5589 IP4_19_16 5590 IP4_15_12 5591 IP4_11_8 5592 IP4_7_4 5593 IP4_3_0 )) 5594 }, 5595 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5596 IP5_31_28 5597 IP5_27_24 5598 IP5_23_20 5599 IP5_19_16 5600 IP5_15_12 5601 IP5_11_8 5602 IP5_7_4 5603 IP5_3_0 )) 5604 }, 5605 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5606 IP6_31_28 5607 IP6_27_24 5608 IP6_23_20 5609 IP6_19_16 5610 IP6_15_12 5611 IP6_11_8 5612 IP6_7_4 5613 IP6_3_0 )) 5614 }, 5615 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32, 5616 GROUP(4, 4, 4, 4, -4, 4, 4, 4), 5617 GROUP( 5618 IP7_31_28 5619 IP7_27_24 5620 IP7_23_20 5621 IP7_19_16 5622 /* IP7_15_12 RESERVED */ 5623 IP7_11_8 5624 IP7_7_4 5625 IP7_3_0 )) 5626 }, 5627 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5628 IP8_31_28 5629 IP8_27_24 5630 IP8_23_20 5631 IP8_19_16 5632 IP8_15_12 5633 IP8_11_8 5634 IP8_7_4 5635 IP8_3_0 )) 5636 }, 5637 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5638 IP9_31_28 5639 IP9_27_24 5640 IP9_23_20 5641 IP9_19_16 5642 IP9_15_12 5643 IP9_11_8 5644 IP9_7_4 5645 IP9_3_0 )) 5646 }, 5647 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5648 IP10_31_28 5649 IP10_27_24 5650 IP10_23_20 5651 IP10_19_16 5652 IP10_15_12 5653 IP10_11_8 5654 IP10_7_4 5655 IP10_3_0 )) 5656 }, 5657 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5658 IP11_31_28 5659 IP11_27_24 5660 IP11_23_20 5661 IP11_19_16 5662 IP11_15_12 5663 IP11_11_8 5664 IP11_7_4 5665 IP11_3_0 )) 5666 }, 5667 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5668 IP12_31_28 5669 IP12_27_24 5670 IP12_23_20 5671 IP12_19_16 5672 IP12_15_12 5673 IP12_11_8 5674 IP12_7_4 5675 IP12_3_0 )) 5676 }, 5677 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5678 IP13_31_28 5679 IP13_27_24 5680 IP13_23_20 5681 IP13_19_16 5682 IP13_15_12 5683 IP13_11_8 5684 IP13_7_4 5685 IP13_3_0 )) 5686 }, 5687 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5688 IP14_31_28 5689 IP14_27_24 5690 IP14_23_20 5691 IP14_19_16 5692 IP14_15_12 5693 IP14_11_8 5694 IP14_7_4 5695 IP14_3_0 )) 5696 }, 5697 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5698 IP15_31_28 5699 IP15_27_24 5700 IP15_23_20 5701 IP15_19_16 5702 IP15_15_12 5703 IP15_11_8 5704 IP15_7_4 5705 IP15_3_0 )) 5706 }, 5707 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5708 IP16_31_28 5709 IP16_27_24 5710 IP16_23_20 5711 IP16_19_16 5712 IP16_15_12 5713 IP16_11_8 5714 IP16_7_4 5715 IP16_3_0 )) 5716 }, 5717 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5718 IP17_31_28 5719 IP17_27_24 5720 IP17_23_20 5721 IP17_19_16 5722 IP17_15_12 5723 IP17_11_8 5724 IP17_7_4 5725 IP17_3_0 )) 5726 }, 5727 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32, 5728 GROUP(-24, 4, 4), 5729 GROUP( 5730 /* IP18_31_8 RESERVED */ 5731 IP18_7_4 5732 IP18_3_0 )) 5733 }, 5734#undef F_ 5735#undef FM 5736 5737#define F_(x, y) x, 5738#define FM(x) FN_##x, 5739 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5740 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2, 5741 1, 1, 1, 2, 2, 1, 2, -3), 5742 GROUP( 5743 MOD_SEL0_31_30_29 5744 MOD_SEL0_28_27 5745 MOD_SEL0_26_25_24 5746 MOD_SEL0_23 5747 MOD_SEL0_22 5748 MOD_SEL0_21 5749 MOD_SEL0_20 5750 MOD_SEL0_19 5751 MOD_SEL0_18_17 5752 MOD_SEL0_16 5753 /* RESERVED 15 */ 5754 MOD_SEL0_14_13 5755 MOD_SEL0_12 5756 MOD_SEL0_11 5757 MOD_SEL0_10 5758 MOD_SEL0_9_8 5759 MOD_SEL0_7_6 5760 MOD_SEL0_5 5761 MOD_SEL0_4_3 5762 /* RESERVED 2, 1, 0 */ )) 5763 }, 5764 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5765 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5766 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1), 5767 GROUP( 5768 MOD_SEL1_31_30 5769 MOD_SEL1_29_28_27 5770 MOD_SEL1_26 5771 MOD_SEL1_25_24 5772 MOD_SEL1_23_22_21 5773 MOD_SEL1_20 5774 MOD_SEL1_19 5775 MOD_SEL1_18_17 5776 MOD_SEL1_16 5777 MOD_SEL1_15_14 5778 MOD_SEL1_13 5779 MOD_SEL1_12 5780 MOD_SEL1_11 5781 MOD_SEL1_10 5782 MOD_SEL1_9 5783 /* RESERVED 8, 7 */ 5784 MOD_SEL1_6 5785 MOD_SEL1_5 5786 MOD_SEL1_4 5787 MOD_SEL1_3 5788 MOD_SEL1_2 5789 MOD_SEL1_1 5790 MOD_SEL1_0 )) 5791 }, 5792 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5793 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5794 -16, 1), 5795 GROUP( 5796 MOD_SEL2_31 5797 MOD_SEL2_30 5798 MOD_SEL2_29 5799 MOD_SEL2_28_27 5800 MOD_SEL2_26 5801 MOD_SEL2_25_24_23 5802 MOD_SEL2_22 5803 MOD_SEL2_21 5804 MOD_SEL2_20 5805 MOD_SEL2_19 5806 MOD_SEL2_18 5807 MOD_SEL2_17 5808 /* RESERVED 16-1 */ 5809 MOD_SEL2_0 )) 5810 }, 5811 { /* sentinel */ } 5812}; 5813 5814static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5815 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5816 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5817 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5818 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5819 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5820 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5821 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5822 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5823 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5824 } }, 5825 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5826 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5827 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5828 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5829 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5830 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5831 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5832 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5833 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5834 } }, 5835 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5836 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5837 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5838 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5839 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5840 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5841 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5842 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5843 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5844 } }, 5845 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5846 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5847 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5848 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5849 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5850 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5851 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5852 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 5853 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 5854 } }, 5855 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 5856 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 5857 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 5858 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 5859 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 5860 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 5861 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 5862 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 5863 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 5864 } }, 5865 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 5866 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 5867 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 5868 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 5869 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 5870 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 5871 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 5872 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 5873 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 5874 } }, 5875 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 5876 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 5877 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 5878 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 5879 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 5880 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 5881 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 5882 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 5883 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 5884 } }, 5885 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 5886 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 5887 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 5888 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 5889 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 5890 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 5891 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 5892 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 5893 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 5894 } }, 5895 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 5896 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 5897 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 5898 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 5899 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 5900 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 5901 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 5902 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 5903 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 5904 } }, 5905 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 5906 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 5907 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 5908 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 5909 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 5910 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 5911 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 5912 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 5913 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 5914 } }, 5915 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 5916 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 5917 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 5918 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 5919 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 5920 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 5921 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 5922 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 5923 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 5924 } }, 5925 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 5926 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 5927 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5928 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5929 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5930 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 5931 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5932 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 5933 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 5934 } }, 5935 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 5936 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 5937 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 5938 { PIN_TMS, 4, 2 }, /* TMS */ 5939 } }, 5940 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 5941 { PIN_TDO, 28, 2 }, /* TDO */ 5942 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 5943 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 5944 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 5945 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 5946 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 5947 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 5948 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 5949 } }, 5950 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 5951 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 5952 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 5953 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 5954 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 5955 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 5956 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 5957 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 5958 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 5959 } }, 5960 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 5961 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 5962 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 5963 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 5964 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 5965 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 5966 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 5967 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 5968 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 5969 } }, 5970 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 5971 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 5972 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 5973 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 5974 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 5975 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 5976 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 5977 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 5978 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 5979 } }, 5980 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 5981 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 5982 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 5983 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 5984 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 5985 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 5986 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 5987 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 5988 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5989 } }, 5990 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5991 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 5992 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5993 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5994 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5995 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 5996 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5997 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5998 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5999 } }, 6000 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 6001 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 6002 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 6003 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 6004 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 6005 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 6006 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 6007 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 6008 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 6009 } }, 6010 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 6011 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 6012 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 6013 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 6014 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 6015 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 6016 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 6017 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 6018 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 6019 } }, 6020 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 6021 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 6022 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 6023 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 6024 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 6025 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 6026 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 6027 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 6028 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 6029 } }, 6030 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 6031 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 6032 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 6033 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 6034 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 6035 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 6036 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 6037 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 6038 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 6039 } }, 6040 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 6041 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 6042 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 6043 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 6044 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 6045 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 6046 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 6047 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 6048 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 6049 } }, 6050 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 6051 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 6052 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 6053 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 6054 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 6055 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 6056 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 6057 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 6058 } }, 6059 { /* sentinel */ } 6060}; 6061 6062enum ioctrl_regs { 6063 POCCTRL, 6064 TDSELCTRL, 6065}; 6066 6067static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 6068 [POCCTRL] = { 0xe6060380, }, 6069 [TDSELCTRL] = { 0xe60603c0, }, 6070 { /* sentinel */ } 6071}; 6072 6073static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 6074{ 6075 int bit = -EINVAL; 6076 6077 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 6078 6079 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 6080 bit = pin & 0x1f; 6081 6082 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 6083 bit = (pin & 0x1f) + 12; 6084 6085 return bit; 6086} 6087 6088static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6089 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 6090 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 6091 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 6092 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 6093 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 6094 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 6095 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 6096 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 6097 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 6098 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 6099 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 6100 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 6101 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 6102 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 6103 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 6104 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 6105 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 6106 [16] = PIN_AVB_RXC, /* AVB_RXC */ 6107 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 6108 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 6109 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 6110 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 6111 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 6112 [22] = PIN_AVB_TXC, /* AVB_TXC */ 6113 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 6114 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 6115 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 6116 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 6117 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 6118 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 6119 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 6120 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 6121 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 6122 } }, 6123 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 6124 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 6125 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 6126 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 6127 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 6128 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 6129 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 6130 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 6131 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 6132 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 6133 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 6134 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 6135 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6136 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6137 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6138 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6139 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6140 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6141 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6142 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6143 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6144 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6145 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6146 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6147 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6148 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6149 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6150 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6151 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6152 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6153 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6154 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6155 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6156 } }, 6157 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6158 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6159 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6160 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6161 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6162 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6163 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6164 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6165 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6166 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6167 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6168 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6169 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6170 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6171 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6172 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6173 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6174 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6175 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6176 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6177 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6178 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6179 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6180 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6181 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6182 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6183 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6184 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6185 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6186 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6187 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6188 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6189 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6190 } }, 6191 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6192 [ 0] = SH_PFC_PIN_NONE, 6193 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6194 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6195 [ 3] = PIN_EXTALR, /* EXTALR*/ 6196 [ 4] = PIN_TRST_N, /* TRST# */ 6197 [ 5] = PIN_TCK, /* TCK */ 6198 [ 6] = PIN_TMS, /* TMS */ 6199 [ 7] = PIN_TDI, /* TDI */ 6200 [ 8] = SH_PFC_PIN_NONE, 6201 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6202 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6203 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6204 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6205 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6206 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6207 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6208 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6209 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6210 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6211 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6212 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6213 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6214 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6215 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6216 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6217 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6218 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6219 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6220 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6221 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6222 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6223 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6224 } }, 6225 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6226 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6227 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6228 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6229 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6230 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6231 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6232 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6233 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6234 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6235 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6236 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6237 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6238 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6239 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6240 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6241 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6242 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6243 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6244 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6245 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6246 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6247 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6248 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6249 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6250 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6251 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6252 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6253 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6254 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6255 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6256 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6257 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6258 } }, 6259 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6260 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6261 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6262 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6263 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6264 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6265 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6266 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6267 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6268 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6269 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6270 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6271 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6272 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6273 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6274 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6275 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6276 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6277 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6278 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6279 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6280 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6281 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6282 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6283 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6284 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6285 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6286 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6287 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6288 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6289 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6290 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6291 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6292 } }, 6293 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6294 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6295 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6296 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6297 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6298 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6299 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6300 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6301 [ 7] = SH_PFC_PIN_NONE, 6302 [ 8] = SH_PFC_PIN_NONE, 6303 [ 9] = SH_PFC_PIN_NONE, 6304 [10] = SH_PFC_PIN_NONE, 6305 [11] = SH_PFC_PIN_NONE, 6306 [12] = SH_PFC_PIN_NONE, 6307 [13] = SH_PFC_PIN_NONE, 6308 [14] = SH_PFC_PIN_NONE, 6309 [15] = SH_PFC_PIN_NONE, 6310 [16] = SH_PFC_PIN_NONE, 6311 [17] = SH_PFC_PIN_NONE, 6312 [18] = SH_PFC_PIN_NONE, 6313 [19] = SH_PFC_PIN_NONE, 6314 [20] = SH_PFC_PIN_NONE, 6315 [21] = SH_PFC_PIN_NONE, 6316 [22] = SH_PFC_PIN_NONE, 6317 [23] = SH_PFC_PIN_NONE, 6318 [24] = SH_PFC_PIN_NONE, 6319 [25] = SH_PFC_PIN_NONE, 6320 [26] = SH_PFC_PIN_NONE, 6321 [27] = SH_PFC_PIN_NONE, 6322 [28] = SH_PFC_PIN_NONE, 6323 [29] = SH_PFC_PIN_NONE, 6324 [30] = SH_PFC_PIN_NONE, 6325 [31] = SH_PFC_PIN_NONE, 6326 } }, 6327 { /* sentinel */ } 6328}; 6329 6330static const struct sh_pfc_soc_operations r8a77965_pfc_ops = { 6331 .pin_to_pocctrl = r8a77965_pin_to_pocctrl, 6332 .get_bias = rcar_pinmux_get_bias, 6333 .set_bias = rcar_pinmux_set_bias, 6334}; 6335 6336#ifdef CONFIG_PINCTRL_PFC_R8A774B1 6337const struct sh_pfc_soc_info r8a774b1_pinmux_info = { 6338 .name = "r8a774b1_pfc", 6339 .ops = &r8a77965_pfc_ops, 6340 .unlock_reg = 0xe6060000, /* PMMR */ 6341 6342 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6343 6344 .pins = pinmux_pins, 6345 .nr_pins = ARRAY_SIZE(pinmux_pins), 6346 .groups = pinmux_groups.common, 6347 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6348 .functions = pinmux_functions.common, 6349 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6350 6351 .cfg_regs = pinmux_config_regs, 6352 .drive_regs = pinmux_drive_regs, 6353 .bias_regs = pinmux_bias_regs, 6354 .ioctrl_regs = pinmux_ioctrl_regs, 6355 6356 .pinmux_data = pinmux_data, 6357 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6358}; 6359#endif 6360 6361#ifdef CONFIG_PINCTRL_PFC_R8A77965 6362const struct sh_pfc_soc_info r8a77965_pinmux_info = { 6363 .name = "r8a77965_pfc", 6364 .ops = &r8a77965_pfc_ops, 6365 .unlock_reg = 0xe6060000, /* PMMR */ 6366 6367 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6368 6369 .pins = pinmux_pins, 6370 .nr_pins = ARRAY_SIZE(pinmux_pins), 6371 .groups = pinmux_groups.common, 6372 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6373 ARRAY_SIZE(pinmux_groups.automotive), 6374 .functions = pinmux_functions.common, 6375 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6376 ARRAY_SIZE(pinmux_functions.automotive), 6377 6378 .cfg_regs = pinmux_config_regs, 6379 .drive_regs = pinmux_drive_regs, 6380 .bias_regs = pinmux_bias_regs, 6381 .ioctrl_regs = pinmux_ioctrl_regs, 6382 6383 .pinmux_data = pinmux_data, 6384 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6385}; 6386#endif 6387