1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de> 4 */ 5 6#include <command.h> 7#include <console.h> 8#include <dm.h> 9#include <i2c.h> 10#include <init.h> 11#include <net.h> 12#include <pci.h> 13#if !defined(CONFIG_SPL_BUILD) 14#include <bootcount.h> 15#endif 16#include <asm/global_data.h> 17#include <asm/gpio.h> 18#include <asm/io.h> 19#include <asm/arch/cpu.h> 20#include <asm/arch/soc.h> 21#include <linux/delay.h> 22#include <linux/mbus.h> 23#ifdef CONFIG_NET 24#include <netdev.h> 25#endif 26#include <u-boot/crc.h> 27#include "theadorable.h" 28 29#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" 30#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" 31 32DECLARE_GLOBAL_DATA_PTR; 33 34#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) 35#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \ 36 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8) 37 38#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780 39#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0 40#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0)) 41 42#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f 43#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c 44#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000 45 46#define GPIO_USB0_PWR_ON 18 47#define GPIO_USB1_PWR_ON 19 48 49#define PEX_SWITCH_NOT_FOUNT_LIMIT 3 50 51#define STM_I2C_BUS 1 52#define STM_I2C_ADDR 0x27 53#define REBOOT_DELAY 1000 /* reboot-delay in ms */ 54#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */ 55 56/* DDR3 static configuration */ 57static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { 58 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */ 59 {0x00001404, 0x30000800}, /* Dunit Control Low Register */ 60 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */ 61 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */ 62 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */ 63 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */ 64 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */ 65 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */ 66 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */ 67 68 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ 69 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ 70 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */ 71 {0x000014A8, 0x00000101}, /* AXI Control Register */ 72 73 /* 74 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the 75 * training sequence 76 */ 77 {0x000200e8, 0x3fff0e01}, 78 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */ 79 80 {0x0001504, 0x7fffffe1}, /* CS0 Size */ 81 {0x000150C, 0x00000000}, /* CS1 Size */ 82 {0x0001514, 0x00000000}, /* CS2 Size */ 83 {0x000151C, 0x00000000}, /* CS3 Size */ 84 85 {0x00020220, 0x00000007}, /* Reserved */ 86 87 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */ 88 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */ 89 90 {0x000015D0, 0x00000650}, /* MR0 */ 91 {0x000015D4, 0x00000044}, /* MR1 */ 92 {0x000015D8, 0x00000010}, /* MR2 */ 93 {0x000015DC, 0x00000000}, /* MR3 */ 94 {0x000015E0, 0x00000001}, 95 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ 96 {0x000015EC, 0xf800a225}, /* DDR PHY */ 97 98 /* Recommended Settings from Marvell for 4 x 16 bit devices: */ 99 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/ 100 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */ 101 102 {0x0, 0x0} 103}; 104 105static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = { 106 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL}, 107}; 108 109extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; 110 111/* 112 * Lane0 - PCIE0.0 X1 (to WIFI Module) 113 * Lane5 - SATA0 114 * Lane6 - SATA1 115 * Lane7 - SGMII0 (to Ethernet Phy) 116 * Lane8-11 - PCIE2.0 X4 (to PEX Switch) 117 * all other lanes are disabled 118 */ 119MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { 120 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111, 121 { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, 122 PEX_BUS_DISABLED }, 123 0x0060, serdes_change_m_phy 124 }, 125}; 126 127/* 128 * Define a board-specific detection pulse-width array for the SerDes PCIe 129 * interfaces. If not defined in the board code, the default of currently 2 130 * is used. Values from 0...3 are possible (2 bits). 131 */ 132u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 }; 133 134MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) 135{ 136 /* Only one mode supported for this board */ 137 return &board_ddr_modes[0]; 138} 139 140MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) 141{ 142 return &theadorable_serdes_cfg[0]; 143} 144 145u8 board_sat_r_get(u8 dev_num, u8 reg) 146{ 147 /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */ 148 return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */ 149} 150 151#define PCIE_LNK_CTRL_STAT_2_OFF 0x0090 152#define PCIE_LNK_CTRL_STAT_2_DEEM_BIT BIT(6) 153 154static void pcie_set_deemphasis(u32 base) 155{ 156 u32 reg; 157 158 reg = readl((void *)base + PCIE_LNK_CTRL_STAT_2_OFF); 159 reg |= PCIE_LNK_CTRL_STAT_2_DEEM_BIT; 160 writel(reg, (void *)base + PCIE_LNK_CTRL_STAT_2_OFF); 161} 162 163int board_early_init_f(void) 164{ 165 /* Configure MPP */ 166 writel(0x00000000, MVEBU_MPP_BASE + 0x00); 167 writel(0x03300000, MVEBU_MPP_BASE + 0x04); 168 writel(0x00000033, MVEBU_MPP_BASE + 0x08); 169 writel(0x00000000, MVEBU_MPP_BASE + 0x0c); 170 writel(0x11110000, MVEBU_MPP_BASE + 0x10); 171 writel(0x00221100, MVEBU_MPP_BASE + 0x14); 172 writel(0x00000000, MVEBU_MPP_BASE + 0x18); 173 writel(0x00000000, MVEBU_MPP_BASE + 0x1c); 174 writel(0x00000000, MVEBU_MPP_BASE + 0x20); 175 176 /* Configure GPIO */ 177 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 178 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 179 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 180 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 181 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); 182 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); 183 184 /* 185 * Set deephasis bit in the PCIe configuration of both PCIe ports 186 * used on this board. 187 * 188 * This needs to be done very early, even before the SERDES setup 189 * code is run. This way, the first link will already be established 190 * with this setup. Testing has shown, that this results in a more 191 * stable PCIe link with better signal quality. 192 */ 193 pcie_set_deemphasis(MVEBU_REG_PCIE_BASE); /* Port 0 */ 194 pcie_set_deemphasis(MVEBU_REG_PCIE_BASE + 0x2000); /* Port 2 */ 195 196 return 0; 197} 198 199int board_init(void) 200{ 201 int ret; 202 203 /* adress of boot parameters */ 204 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 205 206 /* 207 * Map SPI devices via MBUS so that they can be accessed via 208 * the SPI direct access mode 209 */ 210 mbus_dt_setup_win(SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE, 211 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1); 212 mbus_dt_setup_win(SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE, 213 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2); 214 215 /* 216 * Set RX Channel Control 0 Register: 217 * Tests have shown, that setting the LPF_COEF from 0 (1/8) 218 * to 3 (1/1) results in a more stable USB connection. 219 */ 220 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc); 221 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc); 222 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc); 223 224 /* Toggle USB power */ 225 ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON"); 226 if (ret < 0) 227 return ret; 228 gpio_direction_output(GPIO_USB0_PWR_ON, 0); 229 ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON"); 230 if (ret < 0) 231 return ret; 232 gpio_direction_output(GPIO_USB1_PWR_ON, 0); 233 mdelay(1); 234 gpio_set_value(GPIO_USB0_PWR_ON, 1); 235 gpio_set_value(GPIO_USB1_PWR_ON, 1); 236 237 return 0; 238} 239 240int checkboard(void) 241{ 242 board_fpga_add(); 243 244 return 0; 245} 246 247#ifdef CONFIG_NET 248int board_eth_init(struct bd_info *bis) 249{ 250 cpu_eth_init(bis); /* Built in controller(s) come first */ 251 return pci_eth_init(bis); 252} 253#endif 254 255#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT) 256int board_late_init(void) 257{ 258 pci_dev_t bdf; 259 ulong bootcount; 260 261 /* 262 * Check if the PEX switch is detected (somtimes its not available 263 * on the PCIe bus). In this case, try to recover by issuing a 264 * soft-reset or even a power-cycle, depending on the bootcounter 265 * value. 266 */ 267 bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0); 268 if (bdf == -1) { 269 unsigned long start_time = get_timer(0); 270 u8 i2c_buf[8]; 271 int ret; 272 273 /* PEX switch not found! */ 274 bootcount = bootcount_load(); 275 printf("Failed to find PLX PEX-switch (bootcount=%ld)\n", 276 bootcount); 277 278 /* 279 * The user can exit this boot-loop in the error case by 280 * hitting Ctrl-C. So wait some time for this key here. 281 */ 282 printf("Continue booting with Ctrl-C, otherwise rebooting\n"); 283 do { 284 /* Handle control-c and timeouts */ 285 if (ctrlc()) { 286 printf("PEX error boot-loop aborted!\n"); 287 return 0; 288 } 289 } while (get_timer(start_time) < ABORT_TIMEOUT); 290 291 292 /* 293 * At this stage the bootcounter has not been incremented 294 * yet. We need to do this manually here to get an actually 295 * working bootcounter in this error case. 296 */ 297 bootcount_inc(); 298 299 if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) { 300 struct udevice *dev; 301 302 printf("Issuing power-switch via uC!\n"); 303 ret = i2c_get_chip_for_busnum(STM_I2C_BUS, STM_I2C_ADDR, 304 1, &dev); 305 if (ret) { 306 printf("Error selecting STM on I2C bus (ret=%d)\n", 307 ret); 308 printf("Issuing soft-reset...\n"); 309 /* default handling: SOFT reset */ 310 do_reset(NULL, 0, 0, NULL); 311 } 312 313 i2c_buf[0] = STM_I2C_ADDR << 1; 314 i2c_buf[1] = 0xc5; /* cmd */ 315 i2c_buf[2] = 0x01; /* enable */ 316 /* Delay before reboot */ 317 i2c_buf[3] = REBOOT_DELAY & 0x00ff; 318 i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8; 319 /* Delay before shutdown */ 320 i2c_buf[5] = 0x00; 321 i2c_buf[6] = 0x00; 322 i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7); 323 324 ret = dm_i2c_write(dev, 0, &i2c_buf[1], 7); 325 if (ret) { 326 printf("I2C write error (ret=%d)\n", ret); 327 printf("Issuing soft-reset...\n"); 328 /* default handling: SOFT reset */ 329 do_reset(NULL, 0, 0, NULL); 330 } 331 332 /* Wait for power-cycle to occur... */ 333 printf("Waiting for power-cycle via uC...\n"); 334 while (1) 335 ; 336 } else { 337 printf("Issuing soft-reset...\n"); 338 /* default handling: SOFT reset */ 339 do_reset(NULL, 0, 0, NULL); 340 } 341 } 342 343 return 0; 344} 345#endif 346 347#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI) 348static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width) 349{ 350 struct udevice *dev; 351 u16 ven_id, dev_id; 352 u16 lnksta; 353 int ret; 354 int pos; 355 356 /* 357 * Check if the PCIe device is detected (sometimes its not available 358 * on the PCIe bus) 359 */ 360 ret = dm_pci_bus_find_bdf(bdf, &dev); 361 if (ret) 362 return -ENODEV; 363 364 /* PCIe device found */ 365 dm_pci_read_config16(dev, PCI_VENDOR_ID, &ven_id); 366 dm_pci_read_config16(dev, PCI_DEVICE_ID, &dev_id); 367 printf("Detected PCIe device: VendorID 0x%04x DeviceId 0x%04x @ BDF %d.%d.%d\n", 368 ven_id, dev_id, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 369 370 /* Now read EXP_LNKSTA register */ 371 pos = dm_pci_find_capability(dev, PCI_CAP_ID_EXP); 372 dm_pci_read_config16(dev, pos + PCI_EXP_LNKSTA, &lnksta); 373 *speed = lnksta & PCI_EXP_LNKSTA_CLS; 374 *width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 375 376 return 0; 377} 378 379/* 380 * U-Boot cmd to test for the presence of the directly connected PCIe devices 381 * the theadorable board. This cmd can be used by U-Boot scripts for automated 382 * testing, if the PCIe setup is correct. Meaning, that all PCIe devices are 383 * correctly detected and the link speed and width is corrent. 384 * 385 * Here a short script that may be used for an automated test. It results in 386 * an endless reboot loop, if the PCIe devices are detected correctly. If at 387 * any time a problem is detected (PCIe device not available or link is 388 * incorrect), then booting will halt. So just use this "bootcmd" and let the 389 * board run over a longer time (e.g. one night) and if the board still reboots 390 * after this time, then everything is okay. 391 * 392 * bootcmd=echo bootcount=$bootcount; pcie ;if test $? -eq 0; 393 * then echo PCIe status okay, resetting...; reset; else; 394 * echo PCIe status NOT okay, hanging (bootcount=$bootcount); fi; 395 */ 396int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) 397{ 398 pci_dev_t bdf; 399 int speed; 400 int width; 401 int ret; 402 403 if (argc != 1) 404 return cmd_usage(cmdtp); 405 406 /* 407 * Check if the PCIe device is detected (sometimes its not available 408 * on the PCIe bus) 409 */ 410 411 /* Check for PCIe device on PCIe port/bus 0 */ 412 bdf = PCI_BDF(0, 1, 0); 413 ret = pcie_get_link_speed_width(bdf, &speed, &width); 414 if (ret) { 415 /* PCIe device not found! */ 416 printf("Failed to find PCIe device @ BDF %d.%d.%d\n", 417 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 418 return CMD_RET_FAILURE; 419 } 420 421 printf("Established speed=%d width=%d\n", speed, width); 422 if ((speed != 1 || width != 1)) { 423 printf("Detected incorrect speed/width!!!\n"); 424 return CMD_RET_FAILURE; 425 } 426 427 /* Check for PCIe device on PCIe port/bus 1 */ 428 bdf = PCI_BDF(1, 1, 0); 429 ret = pcie_get_link_speed_width(bdf, &speed, &width); 430 if (ret) { 431 /* PCIe device not found! */ 432 printf("Failed to find PCIe device @ BDF %d.%d.%d\n", 433 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 434 return CMD_RET_FAILURE; 435 } 436 437 printf("Established speed=%d width=%d\n", speed, width); 438 if ((speed != 2 || width != 4)) { 439 printf("Detected incorrect speed/width!!!\n"); 440 return CMD_RET_FAILURE; 441 } 442 443 return CMD_RET_SUCCESS; 444} 445 446U_BOOT_CMD( 447 pcie, 1, 0, do_pcie_test, 448 "Test for presence of a PCIe devices with correct link", 449 "" 450); 451#endif 452