1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A7790 processor support
4 *
5 * Copyright (C) 2013  Renesas Electronics Corporation
6 * Copyright (C) 2013  Magnus Damm
7 * Copyright (C) 2012  Renesas Solutions Corp.
8 * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 */
10
11#include <dm.h>
12#include <errno.h>
13#include <dm/pinctrl.h>
14#include <linux/kernel.h>
15
16#include "sh_pfc.h"
17
18/*
19 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
20 * which case they support both 3.3V and 1.8V signalling.
21 */
22#define CPU_ALL_GP(fn, sfx)						\
23	PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
24	PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
25	PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
26	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),	\
27	PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),		\
28	PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
29
30#define CPU_ALL_NOGP(fn)		\
31	PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
32	PIN_NOGP(IIC0_SDA, "AF15", fn),	\
33	PIN_NOGP(IIC0_SCL, "AG15", fn),	\
34	PIN_NOGP(IIC3_SDA, "AH15", fn),	\
35	PIN_NOGP(IIC3_SCL, "AJ15", fn), \
36	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),	\
37	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),	\
38	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),	\
39	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
40
41enum {
42	PINMUX_RESERVED = 0,
43
44	PINMUX_DATA_BEGIN,
45	GP_ALL(DATA),
46	PINMUX_DATA_END,
47
48	PINMUX_FUNCTION_BEGIN,
49	GP_ALL(FN),
50
51	/* GPSR0 */
52	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
53	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
54	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
55	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
56	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
57	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
58	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
59	FN_IP3_14_12, FN_IP3_17_15,
60
61	/* GPSR1 */
62	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
63	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
64	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
65	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
66	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
67	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
68	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
69
70	/* GPSR2 */
71	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
72	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
73	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
74	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
75	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
76	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
77	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
78
79	/* GPSR3 */
80	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
81	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
82	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
83	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
84	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
85	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
86	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
87
88	/* GPSR4 */
89	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
90	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
91	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
92	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
93	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
94	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
95	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
96	FN_IP14_15_12, FN_IP14_18_16,
97
98	/* GPSR5 */
99	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
100	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
101	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
102	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
103	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
104	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
105	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
106
107	/* IPSR0 */
108	FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
109	FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
110	FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
111	FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
112	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
113	FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
114	FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
115	FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
116	FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
117	FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
118	FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
119	FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
120	FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
121	FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
122
123	/* IPSR1 */
124	FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
125	FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
126	FN_SCIFA1_TXD_C, FN_AVB_TXD2,
127	FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
128	FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
129	FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
130	FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
131	FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
132	FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
133	FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
134	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
135	FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
136	FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
137	FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
138	FN_A0, FN_PWM3, FN_A1, FN_PWM4,
139
140	/* IPSR2 */
141	FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
142	FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
143	FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
144	FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
145	FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
146	FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
147	FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
148	FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
149	FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
150	FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
151	FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
152
153	/* IPSR3 */
154	FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
155	FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
156	FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
157	FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
158	FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
159	FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
160	FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
161	FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
162	FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
163	FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
164	FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
165	FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
166	FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
167
168	/* IPSR4 */
169	FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
170	FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
171	FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
172	FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
173	FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
174	FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
175	FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
176	FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
177	FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
178	FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
179	FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
180	FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
181	FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
182	FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
183	FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
184
185	/* IPSR5 */
186	FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
187	FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
188	FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
189	FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
190	FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
191	FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
192	FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
193	FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
194	FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
195	FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
196	FN_WE0_N, FN_IECLK, FN_CAN_CLK,
197	FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
198	FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
199	FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
200	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
201	FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
202	FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
203	FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
204	FN_SSI_WS78_B,
205
206	/* IPSR6 */
207	FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
208	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
209	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
210	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
211	FN_SSI_WS6_B, FN_SSI_SDATA8_C,
212	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
213	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
214	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
215	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
216	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
217	FN_I2C2_SCL_E, FN_ETH_RX_ER,
218	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
219	FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
220	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
221	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
222	FN_HRX0_E, FN_STP_ISSYNC_0_B,
223	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
224	FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
225	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
226	FN_ETH_REF_CLK, FN_HCTS0_N_E,
227	FN_STP_IVCXO27_1_B, FN_HRX0_F,
228
229	/* IPSR7 */
230	FN_ETH_MDIO, FN_HRTS0_N_E,
231	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
232	FN_HTX0_F, FN_BPFCLK_G,
233	FN_ETH_TX_EN, FN_SIM0_CLK_C,
234	FN_HRTS0_N_F, FN_ETH_MAGIC,
235	FN_SIM0_RST_C, FN_ETH_TXD0,
236	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
237	FN_ETH_MDC, FN_STP_ISD_1_B,
238	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
239	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
240	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
241	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
242	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
243	FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
244	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
245	FN_ATACS00_N, FN_AVB_RXD1,
246	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
247
248	/* IPSR8 */
249	FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
250	FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
251	FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
252	FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
253	FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
254	FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
255	FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
256	FN_VI1_CLK, FN_AVB_RX_DV,
257	FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
258	FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
259	FN_SCIFA1_RXD_D, FN_AVB_MDC,
260	FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
261	FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
262	FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
263	FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
264	FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
265	FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
266	FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
267
268	/* IPSR9 */
269	FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
270	FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
271	FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
272	FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
273	FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
274	FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
275	FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
276	FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
277	FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
278	FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
279	FN_AVB_TX_EN, FN_SD1_CMD,
280	FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
281	FN_SD1_DAT0, FN_AVB_TX_CLK,
282	FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
283	FN_SCIFB0_TXD_B, FN_SD1_DAT2,
284	FN_AVB_COL, FN_SCIFB0_CTS_N_B,
285	FN_SD1_DAT3, FN_AVB_RXD0,
286	FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
287	FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
288	FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
289	FN_VI3_CLK_B,
290
291	/* IPSR10 */
292	FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
293	FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
294	FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
295	FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
296	FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
297	FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
298	FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
299	FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
300	FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
301	FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
302	FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
303	FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
304	FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
305	FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
306	FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
307	FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
308	FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
309	FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
310	FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
311	FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
312	FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
313	FN_GLO_I0_B, FN_VI3_DATA6_B,
314
315	/* IPSR11 */
316	FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
317	FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
318	FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
319	FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
320	FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
321	FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
322	FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
323	FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
324	FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
325	FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
326	FN_FMIN_E, FN_FMIN_F,
327	FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
328	FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
329	FN_I2C2_SDA_B, FN_MLB_DAT,
330	FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
331	FN_SSI_SCK0129, FN_CAN_CLK_B,
332	FN_MOUT0,
333
334	/* IPSR12 */
335	FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
336	FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
337	FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
338	FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
339	FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
340	FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
341	FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
342	FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
343	FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
344	FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
345	FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
346	FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
347	FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
348	FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
349	FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
350	FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
351	FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
352	FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
353	FN_CAN_DEBUGOUT4,
354
355	/* IPSR13 */
356	FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
357	FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
358	FN_SCIFB1_CTS_N, FN_BPFCLK_D,
359	FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
360	FN_BPFCLK_F, FN_SSI_WS6,
361	FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
362	FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
363	FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
364	FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
365	FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
366	FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
367	FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
368	FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
369	FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
370	FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
371	FN_BPFCLK_E, FN_SSI_SDATA7_B,
372	FN_FMIN_G, FN_SSI_SDATA8,
373	FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
374	FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
375	FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
376	FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
377	FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
378
379	/* IPSR14 */
380	FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
381	FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
382	FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
383	FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
384	FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
385	FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
386	FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
387	FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
388	FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
389	FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
390	FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
391	FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
392	FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
393	FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
394	FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
395	FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
396	FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
397	FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
398	FN_HRTS0_N_C,
399
400	/* IPSR15 */
401	FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
402	FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
403	FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
404	FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
405	FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
406	FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
407	FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
408	FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
409	FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
410	FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
411	FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
412	FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
413	FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
414	FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
415	FN_DU2_DG6, FN_LCDOUT14,
416
417	/* IPSR16 */
418	FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
419	FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
420	FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
421	FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
422	FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
423	FN_TCLK1_B,
424
425	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
426	FN_SEL_SCIF1_4,
427	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
428	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
429	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
430	FN_SEL_SCIFB1_4,
431	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
432	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
433	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
434	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
435	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
436	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
437	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
438	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
439	FN_SEL_VI3_0, FN_SEL_VI3_1,
440	FN_SEL_VI2_0, FN_SEL_VI2_1,
441	FN_SEL_VI1_0, FN_SEL_VI1_1,
442	FN_SEL_VI0_0, FN_SEL_VI0_1,
443	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
444	FN_SEL_LBS_0, FN_SEL_LBS_1,
445	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
446	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
447	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
448
449	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
450	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
451	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
452	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
453	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
454	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
455	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
456	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
457	FN_SEL_ADI_0, FN_SEL_ADI_1,
458	FN_SEL_SSP_0, FN_SEL_SSP_1,
459	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
460	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
461	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
462	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
463	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
464	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
465	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
466
467	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
468	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
469	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
470	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
471	FN_SEL_IIC2_4,
472	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
473	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
474	FN_SEL_I2C2_4,
475	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
476	PINMUX_FUNCTION_END,
477
478	PINMUX_MARK_BEGIN,
479
480	VI1_DATA7_VI1_B7_MARK,
481
482	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
483	USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
484	DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
485
486	D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
487	D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
488	VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
489	VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
490	VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
491	SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
492	VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
493	SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
494	VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
495	IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
496	I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
497	VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
498	D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
499	VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
500
501	D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
502	VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
503	SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
504	VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
505	SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
506	VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
507	D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
508	VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
509	D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
510	VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
511	SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
512	VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
513	D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
514	VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
515	A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
516
517	A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
518	PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
519	TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
520	A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
521	SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
522	A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
523	VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
524	A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
525	VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
526	A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
527	VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
528
529	A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
530	VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
531	A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
532	VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
533	A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
534	MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
535	VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
536	ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
537	ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
538	A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
539	AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
540	ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
541	VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
542
543	A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
544	A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
545	VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
546	VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
547	VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
548	VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
549	VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
550	VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
551	CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
552	VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
553	VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
554	MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
555	HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
556	VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
557	VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
558
559	EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
560	VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
561	EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
562	VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
563	INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
564	MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
565	VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
566	I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
567	CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
568	CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
569	VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
570	WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
571	VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
572	WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
573	VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
574	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
575	VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
576	MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
577	VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
578	SSI_WS78_B_MARK,
579
580	DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
581	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
582	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
583	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
584	SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
585	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
586	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
587	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
588	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
589	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
590	I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
591	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
592	IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
593	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
594	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
595	HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
596	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
597	RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
598	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
599	ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
600	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
601
602	ETH_MDIO_MARK, HRTS0_N_E_MARK,
603	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
604	HTX0_F_MARK, BPFCLK_G_MARK,
605	ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
606	HRTS0_N_F_MARK, ETH_MAGIC_MARK,
607	SIM0_RST_C_MARK, ETH_TXD0_MARK,
608	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
609	ETH_MDC_MARK, STP_ISD_1_B_MARK,
610	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
611	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
612	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
613	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
614	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
615	PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
616	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
617	ATACS00_N_MARK, AVB_RXD1_MARK,
618	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
619
620	VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
621	VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
622	AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
623	AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
624	AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
625	AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
626	VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
627	VI1_CLK_MARK, AVB_RX_DV_MARK,
628	VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
629	AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
630	SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
631	VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
632	VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
633	AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
634	AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
635	AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
636	SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
637	SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
638
639	SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
640	SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
641	SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
642	SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
643	SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
644	GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
645	I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
646	MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
647	GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
648	I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
649	AVB_TX_EN_MARK, SD1_CMD_MARK,
650	AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
651	SD1_DAT0_MARK, AVB_TX_CLK_MARK,
652	SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
653	SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
654	AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
655	SD1_DAT3_MARK, AVB_RXD0_MARK,
656	SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
657	TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
658	IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
659	VI3_CLK_B_MARK,
660
661	SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
662	GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
663	SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
664	VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
665	VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
666	VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
667	TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
668	SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
669	VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
670	TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
671	SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
672	VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
673	TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
674	SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
675	VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
676	GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
677	MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
678	HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
679	VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
680	TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
681	VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
682	GLO_I0_B_MARK, VI3_DATA6_B_MARK,
683
684	SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
685	GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
686	TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
687	SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
688	MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
689	SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
690	MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
691	SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
692	VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
693	MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
694	FMIN_E_MARK, FMIN_F_MARK,
695	MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
696	MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
697	I2C2_SDA_B_MARK, MLB_DAT_MARK,
698	SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
699	SSI_SCK0129_MARK, CAN_CLK_B_MARK,
700	MOUT0_MARK,
701
702	SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
703	SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
704	SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
705	SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
706	SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
707	MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
708	STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
709	CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
710	SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
711	SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
712	MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
713	SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
714	MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
715	SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
716	CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
717	IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
718	CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
719	IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
720	CAN_DEBUGOUT4_MARK,
721
722	SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
723	LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
724	SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
725	DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
726	BPFCLK_F_MARK, SSI_WS6_MARK,
727	SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
728	LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
729	FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
730	CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
731	SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
732	CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
733	SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
734	LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
735	STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
736	TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
737	BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
738	FMIN_G_MARK, SSI_SDATA8_MARK,
739	STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
740	CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
741	STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
742	SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
743	SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
744
745	AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
746	DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
747	REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
748	MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
749	I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
750	DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
751	TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
752	HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
753	LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
754	SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
755	MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
756	SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
757	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
758	SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
759	LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
760	CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
761	SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
762	MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
763	HRTS0_N_C_MARK,
764
765	SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
766	LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
767	TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
768	SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
769	IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
770	DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
771	DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
772	LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
773	LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
774	LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
775	DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
776	SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
777	HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
778	DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
779	DU2_DG6_MARK, LCDOUT14_MARK,
780
781	MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
782	DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
783	MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
784	ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
785	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
786	TCLK1_B_MARK,
787
788	IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
789	IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
790	PINMUX_MARK_END,
791};
792
793static const u16 pinmux_data[] = {
794	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
795
796	PINMUX_SINGLE(VI1_DATA7_VI1_B7),
797	PINMUX_SINGLE(USB0_PWEN),
798	PINMUX_SINGLE(USB0_OVC_VBUS),
799	PINMUX_SINGLE(USB2_PWEN),
800	PINMUX_SINGLE(USB2_OVC),
801	PINMUX_SINGLE(AVS1),
802	PINMUX_SINGLE(AVS2),
803	PINMUX_SINGLE(DU_DOTCLKIN0),
804	PINMUX_SINGLE(DU_DOTCLKIN2),
805
806	PINMUX_IPSR_GPSR(IP0_2_0, D0),
807	PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
808	PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
809	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
810	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
811	PINMUX_IPSR_GPSR(IP0_5_3, D1),
812	PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
813	PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
814	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
815	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
816	PINMUX_IPSR_GPSR(IP0_8_6, D2),
817	PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
818	PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
819	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
820	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
821	PINMUX_IPSR_GPSR(IP0_11_9, D3),
822	PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
823	PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
824	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
825	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
826	PINMUX_IPSR_GPSR(IP0_15_12, D4),
827	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
828	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
829	PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
830	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
831	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
832	PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
833	PINMUX_IPSR_GPSR(IP0_19_16, D5),
834	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
835	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
836	PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
837	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
838	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
839	PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
840	PINMUX_IPSR_GPSR(IP0_22_20, D6),
841	PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
842	PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
843	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
844	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
845	PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
846	PINMUX_IPSR_GPSR(IP0_26_23, D7),
847	PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
848	PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
849	PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
850	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
851	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
852	PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
853	PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
854	PINMUX_IPSR_GPSR(IP0_30_27, D8),
855	PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
856	PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
857	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
858	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
859	PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
860
861	PINMUX_IPSR_GPSR(IP1_3_0, D9),
862	PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
863	PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
864	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
865	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
866	PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
867	PINMUX_IPSR_GPSR(IP1_7_4, D10),
868	PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
869	PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
870	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
871	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
872	PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
873	PINMUX_IPSR_GPSR(IP1_11_8, D11),
874	PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
875	PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
876	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
877	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
878	PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
879	PINMUX_IPSR_GPSR(IP1_14_12, D12),
880	PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
881	PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
882	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
883	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
884	PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
885	PINMUX_IPSR_GPSR(IP1_17_15, D13),
886	PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
887	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
888	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
889	PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
890	PINMUX_IPSR_GPSR(IP1_21_18, D14),
891	PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
892	PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
893	PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
894	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
895	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
896	PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
897	PINMUX_IPSR_GPSR(IP1_25_22, D15),
898	PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
899	PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
900	PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
901	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
902	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
903	PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
904	PINMUX_IPSR_GPSR(IP1_27_26, A0),
905	PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
906	PINMUX_IPSR_GPSR(IP1_29_28, A1),
907	PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
908
909	PINMUX_IPSR_GPSR(IP2_2_0, A2),
910	PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
911	PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
912	PINMUX_IPSR_GPSR(IP2_5_3, A3),
913	PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
914	PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
915	PINMUX_IPSR_GPSR(IP2_8_6, A4),
916	PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
917	PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
918	PINMUX_IPSR_GPSR(IP2_11_9, A5),
919	PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
920	PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
921	PINMUX_IPSR_GPSR(IP2_14_12, A6),
922	PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
923	PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
924	PINMUX_IPSR_GPSR(IP2_17_15, A7),
925	PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
926	PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
927	PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
928	PINMUX_IPSR_GPSR(IP2_21_18, A8),
929	PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
930	PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
931	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
932	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
933	PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
934	PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
935	PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
936	PINMUX_IPSR_GPSR(IP2_25_22, A9),
937	PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
938	PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
939	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
940	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
941	PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
942	PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
943	PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
944	PINMUX_IPSR_GPSR(IP2_28_26, A10),
945	PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
946	PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
947	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
948	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
949	PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
950
951	PINMUX_IPSR_GPSR(IP3_3_0, A11),
952	PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
953	PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
954	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
955	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
956	PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
957	PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
958	PINMUX_IPSR_GPSR(IP3_7_4, A12),
959	PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
960	PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
961	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
962	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
963	PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
964	PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
965	PINMUX_IPSR_GPSR(IP3_11_8, A13),
966	PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
967	PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
968	PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
969	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
970	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
971	PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
972	PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
973	PINMUX_IPSR_GPSR(IP3_14_12, A14),
974	PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
975	PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
976	PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
977	PINMUX_IPSR_GPSR(IP3_17_15, A15),
978	PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
979	PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
980	PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
981	PINMUX_IPSR_GPSR(IP3_19_18, A16),
982	PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
983	PINMUX_IPSR_GPSR(IP3_22_20, A17),
984	PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
985	PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
986	PINMUX_IPSR_GPSR(IP3_25_23, A18),
987	PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
988	PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
989	PINMUX_IPSR_GPSR(IP3_28_26, A19),
990	PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
991	PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
992	PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
993	PINMUX_IPSR_GPSR(IP3_31_29, A20),
994	PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
995	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
996	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
997	PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
998
999	PINMUX_IPSR_GPSR(IP4_2_0, A21),
1000	PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
1001	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
1002	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1003	PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
1004	PINMUX_IPSR_GPSR(IP4_5_3, A22),
1005	PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
1006	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1007	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1008	PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
1009	PINMUX_IPSR_GPSR(IP4_8_6, A23),
1010	PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1011	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1012	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1013	PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1014	PINMUX_IPSR_GPSR(IP4_11_9, A24),
1015	PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1016	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1017	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1018	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1019	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1020	PINMUX_IPSR_GPSR(IP4_14_12, A25),
1021	PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1022	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1023	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1024	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1025	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1026	PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1027	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1028	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1029	PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1030	PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1031	PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1032	PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1033	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1034	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1035	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1036	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1037	PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1038	PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1039	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1040	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1041	PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1042	PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1043	PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1044	PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1045	PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1046	PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1047	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1048	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1049	PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1050	PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1051	PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1052	PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1053	PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1054	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1055	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1056	PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1057
1058	PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1059	PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1060	PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1061	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1062	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1063	PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1064	PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1065	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1066	PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1067	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1068	PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1069	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1070	PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1071	PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1072	PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1073	PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1074	PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1075	PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1076	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1077	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1078	PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1079	PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1080	PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1081	PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1082	PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1083	PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1084	PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1085	PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1086	PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1087	PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1088	PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1089	PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1090	PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1091	PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1092	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1093	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1094	PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1095	PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1096	PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1097	PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1098	PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1099	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1100	PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1101	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1102	PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1103	PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1104	PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1105	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1106	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1107	PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1108	PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1109	PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1110	PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1111	PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1112	PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1113	PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1114	PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1115	PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1116	PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1117	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1118	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1119	PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1120	PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1121	PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1122
1123	PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1124	PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1125	PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1126	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1127	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1128	PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1129	PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1130	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1131	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1132	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1133	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1134	PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1135	PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1136	PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1137	PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1138	PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1139	PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1140	PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1141	PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1142	PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1143	PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1144	PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1145	PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1146	PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1147	PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1148	PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1149	PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1150	PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1151	PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1152	PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1153	PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1154	PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1155	PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1156	PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1157	PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1158	PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1159	PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1160	PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1161	PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1162	PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1163	PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1164	PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1165	PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1166	PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1167	PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1168	PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1169	PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1170	PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1171	PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1172	PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1173	PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1174	PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1175	PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1176	PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1177	PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1178	PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1179	PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1180	PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1181
1182	PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1183	PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1184	PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1185	PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1186	PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1187	PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1188	PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1189	PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1190	PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1191	PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1192	PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1193	PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1194	PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1195	PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1196	PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1197	PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1198	PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1199	PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1200	PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1201	PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1202	PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1203	PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1204	PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1205	PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1206	PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1207	PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1208	PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1209	PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1210	PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1211	PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1212	PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1213	PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1214	PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1215	PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1216	PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1217	PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1218	PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1219	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1220	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1221	PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1222	PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1223	PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1224	PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1225	PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1226	PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1227
1228	PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1229	PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1230	PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1231	PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1232	PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1233	PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1234	PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1235	PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1236	PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1237	PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1238	PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1239	PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1240	PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1241	PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1242	PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1243	PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1244	PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1245	PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1246	PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1247	PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1248	PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1249	PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1250	PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1251	PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1252	PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1253	PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1254	PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1255	PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1256	PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1257	PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1258	PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1259	PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1260	PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1261	PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1262	PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1263	PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1264	PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1265	PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1266	PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1267	PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1268	PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1269	PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1270	PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1271	PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1272	PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1273
1274	PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1275	PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1276	PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1277	PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1278	PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1279	PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1280	PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1281	PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1282	PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1283	PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1284	PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1285	PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1286	PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1287	PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1288	PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1289	PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1290	PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1291	PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1292	PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1293	PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1294	PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1295	PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1296	PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1297	PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1298	PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1299	PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1300	PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1301	PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1302	PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1303	PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1304	PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1305	PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1306	PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1307	PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1308	PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1309	PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1310	PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1311	PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1312	PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1313	PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1314	PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1315	PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1316	PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1317	PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1318	PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1319	PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1320	PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1321	PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1322	PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1323	PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1324	PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1325	PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1326	PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1327	PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1328	PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1329	PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1330	PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1331
1332	PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1333	PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1334	PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1335	PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1336	PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1337	PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1338	PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1339	PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1340	PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1341	PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1342	PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1343	PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1344	PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1345	PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1346	PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1347	PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1348	PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1349	PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1350	PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1351	PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1352	PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1353	PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1354	PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1355	PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1356	PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1357	PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1358	PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1359	PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1360	PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1361	PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1362	PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1363	PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1364	PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1365	PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1366	PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1367	PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1368	PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1369	PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1370	PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1371	PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1372	PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1373	PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1374	PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1375	PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1376	PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1377	PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1378	PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1379	PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1380	PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1381	PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1382	PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1383	PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1384	PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1385	PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1386	PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1387	PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1388	PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1389	PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1390	PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1391	PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1392	PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1393	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1394	PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1395	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1396	PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1397	PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1398	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1399	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1400	PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1401
1402	PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1403	PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1404	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1405	PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1406	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1407	PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1408	PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1409	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1410	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1411	PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1412	PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1413	PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1414	PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1415	PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1416	PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1417	PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1418	PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1419	PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1420	PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1421	PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1422	PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1423	PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1424	PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1425	PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1426	PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1427	PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1428	PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1429	PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1430	PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1431	PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1432	PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1433	PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1434	PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1435	PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1436	PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1437	PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1438	PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1439	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1440	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1441	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1442	PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1443	PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1444	PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1445	PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1446	PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1447	PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1448	PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1449	PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1450	PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1451	PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1452	PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1453	PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1454	PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1455	PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1456	PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1457
1458	PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1459	PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1460	PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1461	PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1462	PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1463	PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1464	PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1465	PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1466	PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1467	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1468	PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1469	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1470	PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1471	PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1472	PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1473	PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1474	PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1475	PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1476	PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1477	PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1478	PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1479	PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1480	PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1481	PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1482	PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1483	PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1484	PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1485	PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1486	PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1487	PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1488	PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1489	PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1490	PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1491	PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1492	PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1493	PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1494	PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1495	PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1496	PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1497	PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1498	PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1499	PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1500	PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1501	PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1502	PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1503	PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1504	PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1505	PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1506	PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1507	PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1508	PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1509	PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1510	PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1511	PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1512	PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1513	PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1514
1515	PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1516	PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1517	PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1518	PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1519	PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1520	PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1521	PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1522	PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1523	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1524	PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1525	PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1526	PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1527	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1528	PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1529	PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1530	PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1531	PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1532	PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1533	PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1534	PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1535	PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1536	PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1537	PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1538	PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1539	PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1540	PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1541	PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1542	PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1543	PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1544	PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1545	PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1546	PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1547	PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1548	PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1549	PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1550	PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1551	PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1552	PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1553	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1554	PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1555	PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1556	PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1557	PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1558	PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1559	PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1560	PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1561	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1562	PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1563	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1564	PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1565	PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1566	PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1567	PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1568	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1569	PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1570	PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1571	PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1572	PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1573	PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1574	PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1575	PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1576	PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1577	PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1578
1579	PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1580	PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1581	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1582	PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1583	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1584	PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1585	PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1586	PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1587	PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1588	PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1589	PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1590	PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1591	PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1592	PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1593	PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1594	PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1595	PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1596	PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1597	PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1598	PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1599	PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1600	PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1601	PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1602	PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1603	PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1604	PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1605	PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1606	PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1607	PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1608	PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1609	PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1610	PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1611	PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1612	PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1613	PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1614	PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1615	PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1616	PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1617	PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1618	PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1619	PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1620	PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1621	PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1622	PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1623	PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1624	PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1625	PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1626	PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1627	PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1628	PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1629	PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1630	PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1631	PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1632	PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1633	PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1634	PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1635	PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1636	PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1637	PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1638	PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1639	PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1640	PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1641	PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1642	PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1643
1644	PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1645	PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1646	PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1647	PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1648	PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1649	PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1650	PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1651	PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1652	PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1653	PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1654	PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1655	PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1656	PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1657	PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1658	PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1659	PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1660	PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1661	PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1662	PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1663	PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1664	PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1665	PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1666	PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1667	PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1668	PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1669	PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1670	PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1671	PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1672	PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1673	PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1674	PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1675	PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1676	PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1677	PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1678	PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1679	PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1680	PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1681	PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1682	PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1683	PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1684	PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1685	PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1686	PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1687	PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1688	PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1689	PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1690	PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1691	PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1692	PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1693	PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1694	PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1695	PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1696	PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1697	PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1698	PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1699	PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1700	PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1701	PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1702	PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1703	PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1704
1705	PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1706	PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1707	PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1708	PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1709	PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1710	PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1711	PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1712	PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1713	PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1714	PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1715	PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1716	PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1717	PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1718	PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1719	PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1720	PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1721	PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1722	PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1723
1724	PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1725	PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1726	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1727	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1728
1729	PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1730	PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1731	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1732	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1733};
1734
1735/*
1736 * Pins not associated with a GPIO port.
1737 */
1738enum {
1739	GP_ASSIGN_LAST(),
1740	NOGP_ALL(),
1741};
1742
1743static const struct sh_pfc_pin pinmux_pins[] = {
1744	PINMUX_GPIO_GP_ALL(),
1745	PINMUX_NOGP_ALL(),
1746};
1747
1748/* - AUDIO CLOCK ------------------------------------------------------------ */
1749static const unsigned int audio_clk_a_pins[] = {
1750	/* CLK A */
1751	RCAR_GP_PIN(4, 25),
1752};
1753static const unsigned int audio_clk_a_mux[] = {
1754	AUDIO_CLKA_MARK,
1755};
1756static const unsigned int audio_clk_b_pins[] = {
1757	/* CLK B */
1758	RCAR_GP_PIN(4, 26),
1759};
1760static const unsigned int audio_clk_b_mux[] = {
1761	AUDIO_CLKB_MARK,
1762};
1763static const unsigned int audio_clk_c_pins[] = {
1764	/* CLK C */
1765	RCAR_GP_PIN(5, 27),
1766};
1767static const unsigned int audio_clk_c_mux[] = {
1768	AUDIO_CLKC_MARK,
1769};
1770static const unsigned int audio_clkout_pins[] = {
1771	/* CLK OUT */
1772	RCAR_GP_PIN(5, 16),
1773};
1774static const unsigned int audio_clkout_mux[] = {
1775	AUDIO_CLKOUT_MARK,
1776};
1777static const unsigned int audio_clkout_b_pins[] = {
1778	/* CLK OUT B */
1779	RCAR_GP_PIN(0, 23),
1780};
1781static const unsigned int audio_clkout_b_mux[] = {
1782	AUDIO_CLKOUT_B_MARK,
1783};
1784static const unsigned int audio_clkout_c_pins[] = {
1785	/* CLK OUT C */
1786	RCAR_GP_PIN(5, 27),
1787};
1788static const unsigned int audio_clkout_c_mux[] = {
1789	AUDIO_CLKOUT_C_MARK,
1790};
1791static const unsigned int audio_clkout_d_pins[] = {
1792	/* CLK OUT D */
1793	RCAR_GP_PIN(5, 20),
1794};
1795static const unsigned int audio_clkout_d_mux[] = {
1796	AUDIO_CLKOUT_D_MARK,
1797};
1798/* - AVB -------------------------------------------------------------------- */
1799static const unsigned int avb_link_pins[] = {
1800	RCAR_GP_PIN(3, 11),
1801};
1802static const unsigned int avb_link_mux[] = {
1803	AVB_LINK_MARK,
1804};
1805static const unsigned int avb_magic_pins[] = {
1806	RCAR_GP_PIN(2, 14),
1807};
1808static const unsigned int avb_magic_mux[] = {
1809	AVB_MAGIC_MARK,
1810};
1811static const unsigned int avb_phy_int_pins[] = {
1812	RCAR_GP_PIN(2, 15),
1813};
1814static const unsigned int avb_phy_int_mux[] = {
1815	AVB_PHY_INT_MARK,
1816};
1817static const unsigned int avb_mdio_pins[] = {
1818	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1819};
1820static const unsigned int avb_mdio_mux[] = {
1821	AVB_MDC_MARK, AVB_MDIO_MARK,
1822};
1823static const unsigned int avb_mii_pins[] = {
1824	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1825	RCAR_GP_PIN(0, 11),
1826
1827	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1828	RCAR_GP_PIN(2, 2),
1829
1830	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1831	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1832	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
1833};
1834static const unsigned int avb_mii_mux[] = {
1835	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1836	AVB_TXD3_MARK,
1837
1838	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1839	AVB_RXD3_MARK,
1840
1841	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1842	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1843	AVB_TX_CLK_MARK, AVB_COL_MARK,
1844};
1845static const unsigned int avb_gmii_pins[] = {
1846	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1847	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1848	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1849
1850	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1851	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1852	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1853
1854	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1855	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1856	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1857	RCAR_GP_PIN(3, 12),
1858};
1859static const unsigned int avb_gmii_mux[] = {
1860	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1861	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1862	AVB_TXD6_MARK, AVB_TXD7_MARK,
1863
1864	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1865	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1866	AVB_RXD6_MARK, AVB_RXD7_MARK,
1867
1868	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1869	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1870	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1871	AVB_COL_MARK,
1872};
1873/* - CAN0 ----------------------------------------------------------------- */
1874static const unsigned int can0_data_pins[] = {
1875	/* CAN0 RX */
1876	RCAR_GP_PIN(1, 17),
1877	/* CAN0 TX */
1878	RCAR_GP_PIN(1, 19),
1879};
1880static const unsigned int can0_data_mux[] = {
1881	CAN0_RX_MARK,
1882	CAN0_TX_MARK,
1883};
1884static const unsigned int can0_data_b_pins[] = {
1885	/* CAN0 RXB */
1886	RCAR_GP_PIN(4, 5),
1887	/* CAN0 TXB */
1888	RCAR_GP_PIN(4, 4),
1889};
1890static const unsigned int can0_data_b_mux[] = {
1891	CAN0_RX_B_MARK,
1892	CAN0_TX_B_MARK,
1893};
1894static const unsigned int can0_data_c_pins[] = {
1895	/* CAN0 RXC */
1896	RCAR_GP_PIN(4, 26),
1897	/* CAN0 TXC */
1898	RCAR_GP_PIN(4, 23),
1899};
1900static const unsigned int can0_data_c_mux[] = {
1901	CAN0_RX_C_MARK,
1902	CAN0_TX_C_MARK,
1903};
1904static const unsigned int can0_data_d_pins[] = {
1905	/* CAN0 RXD */
1906	RCAR_GP_PIN(4, 26),
1907	/* CAN0 TXD */
1908	RCAR_GP_PIN(4, 18),
1909};
1910static const unsigned int can0_data_d_mux[] = {
1911	CAN0_RX_D_MARK,
1912	CAN0_TX_D_MARK,
1913};
1914/* - CAN1 ----------------------------------------------------------------- */
1915static const unsigned int can1_data_pins[] = {
1916	/* CAN1 RX */
1917	RCAR_GP_PIN(1, 22),
1918	/* CAN1 TX */
1919	RCAR_GP_PIN(1, 18),
1920};
1921static const unsigned int can1_data_mux[] = {
1922	CAN1_RX_MARK,
1923	CAN1_TX_MARK,
1924};
1925static const unsigned int can1_data_b_pins[] = {
1926	/* CAN1 RXB */
1927	RCAR_GP_PIN(4, 7),
1928	/* CAN1 TXB */
1929	RCAR_GP_PIN(4, 6),
1930};
1931static const unsigned int can1_data_b_mux[] = {
1932	CAN1_RX_B_MARK,
1933	CAN1_TX_B_MARK,
1934};
1935/* - CAN Clock -------------------------------------------------------------- */
1936static const unsigned int can_clk_pins[] = {
1937	/* CLK */
1938	RCAR_GP_PIN(1, 21),
1939};
1940
1941static const unsigned int can_clk_mux[] = {
1942	CAN_CLK_MARK,
1943};
1944
1945static const unsigned int can_clk_b_pins[] = {
1946	/* CLK */
1947	RCAR_GP_PIN(4, 3),
1948};
1949
1950static const unsigned int can_clk_b_mux[] = {
1951	CAN_CLK_B_MARK,
1952};
1953/* - DU RGB ----------------------------------------------------------------- */
1954static const unsigned int du_rgb666_pins[] = {
1955	/* R[7:2], G[7:2], B[7:2] */
1956	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1957	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1958	RCAR_GP_PIN(5, 4),  RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1959	RCAR_GP_PIN(5, 7),  RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1960	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1961	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),  RCAR_GP_PIN(5, 8),
1962};
1963static const unsigned int du_rgb666_mux[] = {
1964	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1965	DU2_DR3_MARK, DU2_DR2_MARK,
1966	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1967	DU2_DG3_MARK, DU2_DG2_MARK,
1968	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1969	DU2_DB3_MARK, DU2_DB2_MARK,
1970};
1971static const unsigned int du_rgb888_pins[] = {
1972	/* R[7:0], G[7:0], B[7:0] */
1973	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1974	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1975	RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1976	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1977	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1978	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1979	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1980	RCAR_GP_PIN(5, 8),  RCAR_GP_PIN(5, 6),  RCAR_GP_PIN(5, 5),
1981};
1982static const unsigned int du_rgb888_mux[] = {
1983	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1984	DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1985	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1986	DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1987	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1988	DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1989};
1990static const unsigned int du_clk_out_0_pins[] = {
1991	/* CLKOUT */
1992	RCAR_GP_PIN(5, 2),
1993};
1994static const unsigned int du_clk_out_0_mux[] = {
1995	DU0_DOTCLKOUT_MARK
1996};
1997static const unsigned int du_clk_out_1_pins[] = {
1998	/* CLKOUT */
1999	RCAR_GP_PIN(5, 3),
2000};
2001static const unsigned int du_clk_out_1_mux[] = {
2002	DU1_DOTCLKOUT_MARK
2003};
2004static const unsigned int du_sync_0_pins[] = {
2005	/* VSYNC, HSYNC, DISP */
2006	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
2007};
2008static const unsigned int du_sync_0_mux[] = {
2009	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2010	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
2011};
2012static const unsigned int du_sync_1_pins[] = {
2013	/* VSYNC, HSYNC, DISP */
2014	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
2015};
2016static const unsigned int du_sync_1_mux[] = {
2017	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2018	DU2_DISP_MARK
2019};
2020static const unsigned int du_cde_pins[] = {
2021	/* CDE */
2022	RCAR_GP_PIN(5, 17),
2023};
2024static const unsigned int du_cde_mux[] = {
2025	DU2_CDE_MARK,
2026};
2027/* - DU0 -------------------------------------------------------------------- */
2028static const unsigned int du0_clk_in_pins[] = {
2029	/* CLKIN */
2030	RCAR_GP_PIN(5, 26),
2031};
2032static const unsigned int du0_clk_in_mux[] = {
2033	DU_DOTCLKIN0_MARK
2034};
2035/* - DU1 -------------------------------------------------------------------- */
2036static const unsigned int du1_clk_in_pins[] = {
2037	/* CLKIN */
2038	RCAR_GP_PIN(5, 27),
2039};
2040static const unsigned int du1_clk_in_mux[] = {
2041	DU_DOTCLKIN1_MARK,
2042};
2043/* - DU2 -------------------------------------------------------------------- */
2044static const unsigned int du2_clk_in_pins[] = {
2045	/* CLKIN */
2046	RCAR_GP_PIN(5, 28),
2047};
2048static const unsigned int du2_clk_in_mux[] = {
2049	DU_DOTCLKIN2_MARK,
2050};
2051/* - ETH -------------------------------------------------------------------- */
2052static const unsigned int eth_link_pins[] = {
2053	/* LINK */
2054	RCAR_GP_PIN(2, 22),
2055};
2056static const unsigned int eth_link_mux[] = {
2057	ETH_LINK_MARK,
2058};
2059static const unsigned int eth_magic_pins[] = {
2060	/* MAGIC */
2061	RCAR_GP_PIN(2, 27),
2062};
2063static const unsigned int eth_magic_mux[] = {
2064	ETH_MAGIC_MARK,
2065};
2066static const unsigned int eth_mdio_pins[] = {
2067	/* MDC, MDIO */
2068	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
2069};
2070static const unsigned int eth_mdio_mux[] = {
2071	ETH_MDC_MARK, ETH_MDIO_MARK,
2072};
2073static const unsigned int eth_rmii_pins[] = {
2074	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2075	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2076	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2077	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2078};
2079static const unsigned int eth_rmii_mux[] = {
2080	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2081	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2082};
2083/* - HSCIF0 ----------------------------------------------------------------- */
2084static const unsigned int hscif0_data_pins[] = {
2085	/* RX, TX */
2086	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2087};
2088static const unsigned int hscif0_data_mux[] = {
2089	HRX0_MARK, HTX0_MARK,
2090};
2091static const unsigned int hscif0_clk_pins[] = {
2092	/* SCK */
2093	RCAR_GP_PIN(5, 7),
2094};
2095static const unsigned int hscif0_clk_mux[] = {
2096	HSCK0_MARK,
2097};
2098static const unsigned int hscif0_ctrl_pins[] = {
2099	/* RTS, CTS */
2100	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2101};
2102static const unsigned int hscif0_ctrl_mux[] = {
2103	HRTS0_N_MARK, HCTS0_N_MARK,
2104};
2105static const unsigned int hscif0_data_b_pins[] = {
2106	/* RX, TX */
2107	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2108};
2109static const unsigned int hscif0_data_b_mux[] = {
2110	HRX0_B_MARK, HTX0_B_MARK,
2111};
2112static const unsigned int hscif0_ctrl_b_pins[] = {
2113	/* RTS, CTS */
2114	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2115};
2116static const unsigned int hscif0_ctrl_b_mux[] = {
2117	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2118};
2119static const unsigned int hscif0_data_c_pins[] = {
2120	/* RX, TX */
2121	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2122};
2123static const unsigned int hscif0_data_c_mux[] = {
2124	HRX0_C_MARK, HTX0_C_MARK,
2125};
2126static const unsigned int hscif0_ctrl_c_pins[] = {
2127	/* RTS, CTS */
2128	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2129};
2130static const unsigned int hscif0_ctrl_c_mux[] = {
2131	HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2132};
2133static const unsigned int hscif0_data_d_pins[] = {
2134	/* RX, TX */
2135	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2136};
2137static const unsigned int hscif0_data_d_mux[] = {
2138	HRX0_D_MARK, HTX0_D_MARK,
2139};
2140static const unsigned int hscif0_ctrl_d_pins[] = {
2141	/* RTS, CTS */
2142	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2143};
2144static const unsigned int hscif0_ctrl_d_mux[] = {
2145	HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2146};
2147static const unsigned int hscif0_data_e_pins[] = {
2148	/* RX, TX */
2149	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2150};
2151static const unsigned int hscif0_data_e_mux[] = {
2152	HRX0_E_MARK, HTX0_E_MARK,
2153};
2154static const unsigned int hscif0_ctrl_e_pins[] = {
2155	/* RTS, CTS */
2156	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2157};
2158static const unsigned int hscif0_ctrl_e_mux[] = {
2159	HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2160};
2161static const unsigned int hscif0_data_f_pins[] = {
2162	/* RX, TX */
2163	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2164};
2165static const unsigned int hscif0_data_f_mux[] = {
2166	HRX0_F_MARK, HTX0_F_MARK,
2167};
2168static const unsigned int hscif0_ctrl_f_pins[] = {
2169	/* RTS, CTS */
2170	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2171};
2172static const unsigned int hscif0_ctrl_f_mux[] = {
2173	HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2174};
2175/* - HSCIF1 ----------------------------------------------------------------- */
2176static const unsigned int hscif1_data_pins[] = {
2177	/* RX, TX */
2178	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2179};
2180static const unsigned int hscif1_data_mux[] = {
2181	HRX1_MARK, HTX1_MARK,
2182};
2183static const unsigned int hscif1_clk_pins[] = {
2184	/* SCK */
2185	RCAR_GP_PIN(4, 27),
2186};
2187static const unsigned int hscif1_clk_mux[] = {
2188	HSCK1_MARK,
2189};
2190static const unsigned int hscif1_ctrl_pins[] = {
2191	/* RTS, CTS */
2192	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2193};
2194static const unsigned int hscif1_ctrl_mux[] = {
2195	HRTS1_N_MARK, HCTS1_N_MARK,
2196};
2197static const unsigned int hscif1_data_b_pins[] = {
2198	/* RX, TX */
2199	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2200};
2201static const unsigned int hscif1_data_b_mux[] = {
2202	HRX1_B_MARK, HTX1_B_MARK,
2203};
2204static const unsigned int hscif1_clk_b_pins[] = {
2205	/* SCK */
2206	RCAR_GP_PIN(1, 28),
2207};
2208static const unsigned int hscif1_clk_b_mux[] = {
2209	HSCK1_B_MARK,
2210};
2211static const unsigned int hscif1_ctrl_b_pins[] = {
2212	/* RTS, CTS */
2213	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2214};
2215static const unsigned int hscif1_ctrl_b_mux[] = {
2216	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2217};
2218/* - I2C0 ------------------------------------------------------------------- */
2219static const unsigned int i2c0_pins[] = {
2220	/* SCL, SDA */
2221	PIN_IIC0_SCL, PIN_IIC0_SDA,
2222};
2223static const unsigned int i2c0_mux[] = {
2224	I2C0_SCL_MARK, I2C0_SDA_MARK,
2225};
2226/* - I2C1 ------------------------------------------------------------------- */
2227static const unsigned int i2c1_pins[] = {
2228	/* SCL, SDA */
2229	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2230};
2231static const unsigned int i2c1_mux[] = {
2232	I2C1_SCL_MARK, I2C1_SDA_MARK,
2233};
2234static const unsigned int i2c1_b_pins[] = {
2235	/* SCL, SDA */
2236	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2237};
2238static const unsigned int i2c1_b_mux[] = {
2239	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2240};
2241static const unsigned int i2c1_c_pins[] = {
2242	/* SCL, SDA */
2243	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2244};
2245static const unsigned int i2c1_c_mux[] = {
2246	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2247};
2248/* - I2C2 ------------------------------------------------------------------- */
2249static const unsigned int i2c2_pins[] = {
2250	/* SCL, SDA */
2251	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2252};
2253static const unsigned int i2c2_mux[] = {
2254	I2C2_SCL_MARK, I2C2_SDA_MARK,
2255};
2256static const unsigned int i2c2_b_pins[] = {
2257	/* SCL, SDA */
2258	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2259};
2260static const unsigned int i2c2_b_mux[] = {
2261	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2262};
2263static const unsigned int i2c2_c_pins[] = {
2264	/* SCL, SDA */
2265	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2266};
2267static const unsigned int i2c2_c_mux[] = {
2268	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2269};
2270static const unsigned int i2c2_d_pins[] = {
2271	/* SCL, SDA */
2272	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2273};
2274static const unsigned int i2c2_d_mux[] = {
2275	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2276};
2277static const unsigned int i2c2_e_pins[] = {
2278	/* SCL, SDA */
2279	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2280};
2281static const unsigned int i2c2_e_mux[] = {
2282	I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2283};
2284/* - I2C3 ------------------------------------------------------------------- */
2285static const unsigned int i2c3_pins[] = {
2286	/* SCL, SDA */
2287	PIN_IIC3_SCL, PIN_IIC3_SDA,
2288};
2289static const unsigned int i2c3_mux[] = {
2290	I2C3_SCL_MARK, I2C3_SDA_MARK,
2291};
2292/* - IIC0 (I2C4) ------------------------------------------------------------ */
2293static const unsigned int iic0_pins[] = {
2294	/* SCL, SDA */
2295	PIN_IIC0_SCL, PIN_IIC0_SDA,
2296};
2297static const unsigned int iic0_mux[] = {
2298	IIC0_SCL_MARK, IIC0_SDA_MARK,
2299};
2300/* - IIC1 (I2C5) ------------------------------------------------------------ */
2301static const unsigned int iic1_pins[] = {
2302	/* SCL, SDA */
2303	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2304};
2305static const unsigned int iic1_mux[] = {
2306	IIC1_SCL_MARK, IIC1_SDA_MARK,
2307};
2308static const unsigned int iic1_b_pins[] = {
2309	/* SCL, SDA */
2310	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2311};
2312static const unsigned int iic1_b_mux[] = {
2313	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2314};
2315static const unsigned int iic1_c_pins[] = {
2316	/* SCL, SDA */
2317	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2318};
2319static const unsigned int iic1_c_mux[] = {
2320	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2321};
2322/* - IIC2 (I2C6) ------------------------------------------------------------ */
2323static const unsigned int iic2_pins[] = {
2324	/* SCL, SDA */
2325	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2326};
2327static const unsigned int iic2_mux[] = {
2328	IIC2_SCL_MARK, IIC2_SDA_MARK,
2329};
2330static const unsigned int iic2_b_pins[] = {
2331	/* SCL, SDA */
2332	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2333};
2334static const unsigned int iic2_b_mux[] = {
2335	IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2336};
2337static const unsigned int iic2_c_pins[] = {
2338	/* SCL, SDA */
2339	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2340};
2341static const unsigned int iic2_c_mux[] = {
2342	IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2343};
2344static const unsigned int iic2_d_pins[] = {
2345	/* SCL, SDA */
2346	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2347};
2348static const unsigned int iic2_d_mux[] = {
2349	IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2350};
2351static const unsigned int iic2_e_pins[] = {
2352	/* SCL, SDA */
2353	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2354};
2355static const unsigned int iic2_e_mux[] = {
2356	IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2357};
2358/* - IIC3 (I2C7) ------------------------------------------------------------ */
2359static const unsigned int iic3_pins[] = {
2360	/* SCL, SDA */
2361	PIN_IIC3_SCL, PIN_IIC3_SDA,
2362};
2363static const unsigned int iic3_mux[] = {
2364	IIC3_SCL_MARK, IIC3_SDA_MARK,
2365};
2366/* - INTC ------------------------------------------------------------------- */
2367static const unsigned int intc_irq0_pins[] = {
2368	/* IRQ */
2369	RCAR_GP_PIN(1, 25),
2370};
2371static const unsigned int intc_irq0_mux[] = {
2372	IRQ0_MARK,
2373};
2374static const unsigned int intc_irq1_pins[] = {
2375	/* IRQ */
2376	RCAR_GP_PIN(1, 27),
2377};
2378static const unsigned int intc_irq1_mux[] = {
2379	IRQ1_MARK,
2380};
2381static const unsigned int intc_irq2_pins[] = {
2382	/* IRQ */
2383	RCAR_GP_PIN(1, 29),
2384};
2385static const unsigned int intc_irq2_mux[] = {
2386	IRQ2_MARK,
2387};
2388static const unsigned int intc_irq3_pins[] = {
2389	/* IRQ */
2390	RCAR_GP_PIN(1, 23),
2391};
2392static const unsigned int intc_irq3_mux[] = {
2393	IRQ3_MARK,
2394};
2395
2396#ifdef CONFIG_PINCTRL_PFC_R8A7790
2397/* - MLB+ ------------------------------------------------------------------- */
2398static const unsigned int mlb_3pin_pins[] = {
2399	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2400};
2401static const unsigned int mlb_3pin_mux[] = {
2402	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2403};
2404#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
2405
2406/* - MMCIF0 ----------------------------------------------------------------- */
2407static const unsigned int mmc0_data_pins[] = {
2408	/* D[0:7] */
2409	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2410	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2411	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2412	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2413};
2414static const unsigned int mmc0_data_mux[] = {
2415	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2416	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2417};
2418static const unsigned int mmc0_ctrl_pins[] = {
2419	/* CLK, CMD */
2420	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2421};
2422static const unsigned int mmc0_ctrl_mux[] = {
2423	MMC0_CLK_MARK, MMC0_CMD_MARK,
2424};
2425/* - MMCIF1 ----------------------------------------------------------------- */
2426static const unsigned int mmc1_data_pins[] = {
2427	/* D[0:7] */
2428	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2429	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2430	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2431	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2432};
2433static const unsigned int mmc1_data_mux[] = {
2434	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2435	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2436};
2437static const unsigned int mmc1_ctrl_pins[] = {
2438	/* CLK, CMD */
2439	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2440};
2441static const unsigned int mmc1_ctrl_mux[] = {
2442	MMC1_CLK_MARK, MMC1_CMD_MARK,
2443};
2444/* - MSIOF0 ----------------------------------------------------------------- */
2445static const unsigned int msiof0_clk_pins[] = {
2446	/* SCK */
2447	RCAR_GP_PIN(5, 12),
2448};
2449static const unsigned int msiof0_clk_mux[] = {
2450	MSIOF0_SCK_MARK,
2451};
2452static const unsigned int msiof0_sync_pins[] = {
2453	/* SYNC */
2454	RCAR_GP_PIN(5, 13),
2455};
2456static const unsigned int msiof0_sync_mux[] = {
2457	MSIOF0_SYNC_MARK,
2458};
2459static const unsigned int msiof0_ss1_pins[] = {
2460	/* SS1 */
2461	RCAR_GP_PIN(5, 14),
2462};
2463static const unsigned int msiof0_ss1_mux[] = {
2464	MSIOF0_SS1_MARK,
2465};
2466static const unsigned int msiof0_ss2_pins[] = {
2467	/* SS2 */
2468	RCAR_GP_PIN(5, 16),
2469};
2470static const unsigned int msiof0_ss2_mux[] = {
2471	MSIOF0_SS2_MARK,
2472};
2473static const unsigned int msiof0_rx_pins[] = {
2474	/* RXD */
2475	RCAR_GP_PIN(5, 17),
2476};
2477static const unsigned int msiof0_rx_mux[] = {
2478	MSIOF0_RXD_MARK,
2479};
2480static const unsigned int msiof0_tx_pins[] = {
2481	/* TXD */
2482	RCAR_GP_PIN(5, 15),
2483};
2484static const unsigned int msiof0_tx_mux[] = {
2485	MSIOF0_TXD_MARK,
2486};
2487
2488static const unsigned int msiof0_clk_b_pins[] = {
2489	/* SCK */
2490	RCAR_GP_PIN(1, 23),
2491};
2492static const unsigned int msiof0_clk_b_mux[] = {
2493	MSIOF0_SCK_B_MARK,
2494};
2495static const unsigned int msiof0_ss1_b_pins[] = {
2496	/* SS1 */
2497	RCAR_GP_PIN(1, 12),
2498};
2499static const unsigned int msiof0_ss1_b_mux[] = {
2500	MSIOF0_SS1_B_MARK,
2501};
2502static const unsigned int msiof0_ss2_b_pins[] = {
2503	/* SS2 */
2504	RCAR_GP_PIN(1, 10),
2505};
2506static const unsigned int msiof0_ss2_b_mux[] = {
2507	MSIOF0_SS2_B_MARK,
2508};
2509static const unsigned int msiof0_rx_b_pins[] = {
2510	/* RXD */
2511	RCAR_GP_PIN(1, 29),
2512};
2513static const unsigned int msiof0_rx_b_mux[] = {
2514	MSIOF0_RXD_B_MARK,
2515};
2516static const unsigned int msiof0_tx_b_pins[] = {
2517	/* TXD */
2518	RCAR_GP_PIN(1, 28),
2519};
2520static const unsigned int msiof0_tx_b_mux[] = {
2521	MSIOF0_TXD_B_MARK,
2522};
2523/* - MSIOF1 ----------------------------------------------------------------- */
2524static const unsigned int msiof1_clk_pins[] = {
2525	/* SCK */
2526	RCAR_GP_PIN(4, 8),
2527};
2528static const unsigned int msiof1_clk_mux[] = {
2529	MSIOF1_SCK_MARK,
2530};
2531static const unsigned int msiof1_sync_pins[] = {
2532	/* SYNC */
2533	RCAR_GP_PIN(4, 9),
2534};
2535static const unsigned int msiof1_sync_mux[] = {
2536	MSIOF1_SYNC_MARK,
2537};
2538static const unsigned int msiof1_ss1_pins[] = {
2539	/* SS1 */
2540	RCAR_GP_PIN(4, 10),
2541};
2542static const unsigned int msiof1_ss1_mux[] = {
2543	MSIOF1_SS1_MARK,
2544};
2545static const unsigned int msiof1_ss2_pins[] = {
2546	/* SS2 */
2547	RCAR_GP_PIN(4, 11),
2548};
2549static const unsigned int msiof1_ss2_mux[] = {
2550	MSIOF1_SS2_MARK,
2551};
2552static const unsigned int msiof1_rx_pins[] = {
2553	/* RXD */
2554	RCAR_GP_PIN(4, 13),
2555};
2556static const unsigned int msiof1_rx_mux[] = {
2557	MSIOF1_RXD_MARK,
2558};
2559static const unsigned int msiof1_tx_pins[] = {
2560	/* TXD */
2561	RCAR_GP_PIN(4, 12),
2562};
2563static const unsigned int msiof1_tx_mux[] = {
2564	MSIOF1_TXD_MARK,
2565};
2566
2567static const unsigned int msiof1_clk_b_pins[] = {
2568	/* SCK */
2569	RCAR_GP_PIN(1, 16),
2570};
2571static const unsigned int msiof1_clk_b_mux[] = {
2572	MSIOF1_SCK_B_MARK,
2573};
2574static const unsigned int msiof1_ss1_b_pins[] = {
2575	/* SS1 */
2576	RCAR_GP_PIN(0, 18),
2577};
2578static const unsigned int msiof1_ss1_b_mux[] = {
2579	MSIOF1_SS1_B_MARK,
2580};
2581static const unsigned int msiof1_ss2_b_pins[] = {
2582	/* SS2 */
2583	RCAR_GP_PIN(0, 19),
2584};
2585static const unsigned int msiof1_ss2_b_mux[] = {
2586	MSIOF1_SS2_B_MARK,
2587};
2588static const unsigned int msiof1_rx_b_pins[] = {
2589	/* RXD */
2590	RCAR_GP_PIN(1, 17),
2591};
2592static const unsigned int msiof1_rx_b_mux[] = {
2593	MSIOF1_RXD_B_MARK,
2594};
2595static const unsigned int msiof1_tx_b_pins[] = {
2596	/* TXD */
2597	RCAR_GP_PIN(0, 20),
2598};
2599static const unsigned int msiof1_tx_b_mux[] = {
2600	MSIOF1_TXD_B_MARK,
2601};
2602/* - MSIOF2 ----------------------------------------------------------------- */
2603static const unsigned int msiof2_clk_pins[] = {
2604	/* SCK */
2605	RCAR_GP_PIN(0, 27),
2606};
2607static const unsigned int msiof2_clk_mux[] = {
2608	MSIOF2_SCK_MARK,
2609};
2610static const unsigned int msiof2_sync_pins[] = {
2611	/* SYNC */
2612	RCAR_GP_PIN(0, 26),
2613};
2614static const unsigned int msiof2_sync_mux[] = {
2615	MSIOF2_SYNC_MARK,
2616};
2617static const unsigned int msiof2_ss1_pins[] = {
2618	/* SS1 */
2619	RCAR_GP_PIN(0, 30),
2620};
2621static const unsigned int msiof2_ss1_mux[] = {
2622	MSIOF2_SS1_MARK,
2623};
2624static const unsigned int msiof2_ss2_pins[] = {
2625	/* SS2 */
2626	RCAR_GP_PIN(0, 31),
2627};
2628static const unsigned int msiof2_ss2_mux[] = {
2629	MSIOF2_SS2_MARK,
2630};
2631static const unsigned int msiof2_rx_pins[] = {
2632	/* RXD */
2633	RCAR_GP_PIN(0, 29),
2634};
2635static const unsigned int msiof2_rx_mux[] = {
2636	MSIOF2_RXD_MARK,
2637};
2638static const unsigned int msiof2_tx_pins[] = {
2639	/* TXD */
2640	RCAR_GP_PIN(0, 28),
2641};
2642static const unsigned int msiof2_tx_mux[] = {
2643	MSIOF2_TXD_MARK,
2644};
2645/* - MSIOF3 ----------------------------------------------------------------- */
2646static const unsigned int msiof3_clk_pins[] = {
2647	/* SCK */
2648	RCAR_GP_PIN(5, 4),
2649};
2650static const unsigned int msiof3_clk_mux[] = {
2651	MSIOF3_SCK_MARK,
2652};
2653static const unsigned int msiof3_sync_pins[] = {
2654	/* SYNC */
2655	RCAR_GP_PIN(4, 30),
2656};
2657static const unsigned int msiof3_sync_mux[] = {
2658	MSIOF3_SYNC_MARK,
2659};
2660static const unsigned int msiof3_ss1_pins[] = {
2661	/* SS1 */
2662	RCAR_GP_PIN(4, 31),
2663};
2664static const unsigned int msiof3_ss1_mux[] = {
2665	MSIOF3_SS1_MARK,
2666};
2667static const unsigned int msiof3_ss2_pins[] = {
2668	/* SS2 */
2669	RCAR_GP_PIN(4, 27),
2670};
2671static const unsigned int msiof3_ss2_mux[] = {
2672	MSIOF3_SS2_MARK,
2673};
2674static const unsigned int msiof3_rx_pins[] = {
2675	/* RXD */
2676	RCAR_GP_PIN(5, 2),
2677};
2678static const unsigned int msiof3_rx_mux[] = {
2679	MSIOF3_RXD_MARK,
2680};
2681static const unsigned int msiof3_tx_pins[] = {
2682	/* TXD */
2683	RCAR_GP_PIN(5, 3),
2684};
2685static const unsigned int msiof3_tx_mux[] = {
2686	MSIOF3_TXD_MARK,
2687};
2688
2689static const unsigned int msiof3_clk_b_pins[] = {
2690	/* SCK */
2691	RCAR_GP_PIN(0, 0),
2692};
2693static const unsigned int msiof3_clk_b_mux[] = {
2694	MSIOF3_SCK_B_MARK,
2695};
2696static const unsigned int msiof3_sync_b_pins[] = {
2697	/* SYNC */
2698	RCAR_GP_PIN(0, 1),
2699};
2700static const unsigned int msiof3_sync_b_mux[] = {
2701	MSIOF3_SYNC_B_MARK,
2702};
2703static const unsigned int msiof3_rx_b_pins[] = {
2704	/* RXD */
2705	RCAR_GP_PIN(0, 2),
2706};
2707static const unsigned int msiof3_rx_b_mux[] = {
2708	MSIOF3_RXD_B_MARK,
2709};
2710static const unsigned int msiof3_tx_b_pins[] = {
2711	/* TXD */
2712	RCAR_GP_PIN(0, 3),
2713};
2714static const unsigned int msiof3_tx_b_mux[] = {
2715	MSIOF3_TXD_B_MARK,
2716};
2717/* - PWM -------------------------------------------------------------------- */
2718static const unsigned int pwm0_pins[] = {
2719	RCAR_GP_PIN(5, 29),
2720};
2721static const unsigned int pwm0_mux[] = {
2722	PWM0_MARK,
2723};
2724static const unsigned int pwm0_b_pins[] = {
2725	RCAR_GP_PIN(4, 30),
2726};
2727static const unsigned int pwm0_b_mux[] = {
2728	PWM0_B_MARK,
2729};
2730static const unsigned int pwm1_pins[] = {
2731	RCAR_GP_PIN(5, 30),
2732};
2733static const unsigned int pwm1_mux[] = {
2734	PWM1_MARK,
2735};
2736static const unsigned int pwm1_b_pins[] = {
2737	RCAR_GP_PIN(4, 31),
2738};
2739static const unsigned int pwm1_b_mux[] = {
2740	PWM1_B_MARK,
2741};
2742static const unsigned int pwm2_pins[] = {
2743	RCAR_GP_PIN(5, 31),
2744};
2745static const unsigned int pwm2_mux[] = {
2746	PWM2_MARK,
2747};
2748static const unsigned int pwm3_pins[] = {
2749	RCAR_GP_PIN(0, 16),
2750};
2751static const unsigned int pwm3_mux[] = {
2752	PWM3_MARK,
2753};
2754static const unsigned int pwm4_pins[] = {
2755	RCAR_GP_PIN(0, 17),
2756};
2757static const unsigned int pwm4_mux[] = {
2758	PWM4_MARK,
2759};
2760static const unsigned int pwm5_pins[] = {
2761	RCAR_GP_PIN(0, 18),
2762};
2763static const unsigned int pwm5_mux[] = {
2764	PWM5_MARK,
2765};
2766static const unsigned int pwm6_pins[] = {
2767	RCAR_GP_PIN(0, 19),
2768};
2769static const unsigned int pwm6_mux[] = {
2770	PWM6_MARK,
2771};
2772/* - QSPI ------------------------------------------------------------------- */
2773static const unsigned int qspi_ctrl_pins[] = {
2774	/* SPCLK, SSL */
2775	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2776};
2777static const unsigned int qspi_ctrl_mux[] = {
2778	SPCLK_MARK, SSL_MARK,
2779};
2780static const unsigned int qspi_data_pins[] = {
2781	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2782	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2783	RCAR_GP_PIN(1, 8),
2784};
2785static const unsigned int qspi_data_mux[] = {
2786	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2787};
2788/* - SCIF0 ------------------------------------------------------------------ */
2789static const unsigned int scif0_data_pins[] = {
2790	/* RX, TX */
2791	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2792};
2793static const unsigned int scif0_data_mux[] = {
2794	RX0_MARK, TX0_MARK,
2795};
2796static const unsigned int scif0_clk_pins[] = {
2797	/* SCK */
2798	RCAR_GP_PIN(4, 27),
2799};
2800static const unsigned int scif0_clk_mux[] = {
2801	SCK0_MARK,
2802};
2803static const unsigned int scif0_ctrl_pins[] = {
2804	/* RTS, CTS */
2805	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2806};
2807static const unsigned int scif0_ctrl_mux[] = {
2808	RTS0_N_MARK, CTS0_N_MARK,
2809};
2810static const unsigned int scif0_data_b_pins[] = {
2811	/* RX, TX */
2812	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2813};
2814static const unsigned int scif0_data_b_mux[] = {
2815	RX0_B_MARK, TX0_B_MARK,
2816};
2817/* - SCIF1 ------------------------------------------------------------------ */
2818static const unsigned int scif1_data_pins[] = {
2819	/* RX, TX */
2820	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2821};
2822static const unsigned int scif1_data_mux[] = {
2823	RX1_MARK, TX1_MARK,
2824};
2825static const unsigned int scif1_clk_pins[] = {
2826	/* SCK */
2827	RCAR_GP_PIN(4, 20),
2828};
2829static const unsigned int scif1_clk_mux[] = {
2830	SCK1_MARK,
2831};
2832static const unsigned int scif1_ctrl_pins[] = {
2833	/* RTS, CTS */
2834	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2835};
2836static const unsigned int scif1_ctrl_mux[] = {
2837	RTS1_N_MARK, CTS1_N_MARK,
2838};
2839static const unsigned int scif1_data_b_pins[] = {
2840	/* RX, TX */
2841	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2842};
2843static const unsigned int scif1_data_b_mux[] = {
2844	RX1_B_MARK, TX1_B_MARK,
2845};
2846static const unsigned int scif1_data_c_pins[] = {
2847	/* RX, TX */
2848	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2849};
2850static const unsigned int scif1_data_c_mux[] = {
2851	RX1_C_MARK, TX1_C_MARK,
2852};
2853static const unsigned int scif1_data_d_pins[] = {
2854	/* RX, TX */
2855	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2856};
2857static const unsigned int scif1_data_d_mux[] = {
2858	RX1_D_MARK, TX1_D_MARK,
2859};
2860static const unsigned int scif1_clk_d_pins[] = {
2861	/* SCK */
2862	RCAR_GP_PIN(3, 17),
2863};
2864static const unsigned int scif1_clk_d_mux[] = {
2865	SCK1_D_MARK,
2866};
2867static const unsigned int scif1_data_e_pins[] = {
2868	/* RX, TX */
2869	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2870};
2871static const unsigned int scif1_data_e_mux[] = {
2872	RX1_E_MARK, TX1_E_MARK,
2873};
2874static const unsigned int scif1_clk_e_pins[] = {
2875	/* SCK */
2876	RCAR_GP_PIN(2, 20),
2877};
2878static const unsigned int scif1_clk_e_mux[] = {
2879	SCK1_E_MARK,
2880};
2881/* - SCIF2 ------------------------------------------------------------------ */
2882static const unsigned int scif2_data_pins[] = {
2883	/* RX, TX */
2884	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2885};
2886static const unsigned int scif2_data_mux[] = {
2887	RX2_MARK, TX2_MARK,
2888};
2889static const unsigned int scif2_clk_pins[] = {
2890	/* SCK */
2891	RCAR_GP_PIN(5, 4),
2892};
2893static const unsigned int scif2_clk_mux[] = {
2894	SCK2_MARK,
2895};
2896static const unsigned int scif2_data_b_pins[] = {
2897	/* RX, TX */
2898	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2899};
2900static const unsigned int scif2_data_b_mux[] = {
2901	RX2_B_MARK, TX2_B_MARK,
2902};
2903/* - SCIFA0 ----------------------------------------------------------------- */
2904static const unsigned int scifa0_data_pins[] = {
2905	/* RXD, TXD */
2906	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2907};
2908static const unsigned int scifa0_data_mux[] = {
2909	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2910};
2911static const unsigned int scifa0_clk_pins[] = {
2912	/* SCK */
2913	RCAR_GP_PIN(4, 27),
2914};
2915static const unsigned int scifa0_clk_mux[] = {
2916	SCIFA0_SCK_MARK,
2917};
2918static const unsigned int scifa0_ctrl_pins[] = {
2919	/* RTS, CTS */
2920	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2921};
2922static const unsigned int scifa0_ctrl_mux[] = {
2923	SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2924};
2925static const unsigned int scifa0_data_b_pins[] = {
2926	/* RXD, TXD */
2927	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2928};
2929static const unsigned int scifa0_data_b_mux[] = {
2930	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2931};
2932static const unsigned int scifa0_clk_b_pins[] = {
2933	/* SCK */
2934	RCAR_GP_PIN(1, 19),
2935};
2936static const unsigned int scifa0_clk_b_mux[] = {
2937	SCIFA0_SCK_B_MARK,
2938};
2939static const unsigned int scifa0_ctrl_b_pins[] = {
2940	/* RTS, CTS */
2941	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2942};
2943static const unsigned int scifa0_ctrl_b_mux[] = {
2944	SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2945};
2946/* - SCIFA1 ----------------------------------------------------------------- */
2947static const unsigned int scifa1_data_pins[] = {
2948	/* RXD, TXD */
2949	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2950};
2951static const unsigned int scifa1_data_mux[] = {
2952	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2953};
2954static const unsigned int scifa1_clk_pins[] = {
2955	/* SCK */
2956	RCAR_GP_PIN(4, 20),
2957};
2958static const unsigned int scifa1_clk_mux[] = {
2959	SCIFA1_SCK_MARK,
2960};
2961static const unsigned int scifa1_ctrl_pins[] = {
2962	/* RTS, CTS */
2963	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2964};
2965static const unsigned int scifa1_ctrl_mux[] = {
2966	SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2967};
2968static const unsigned int scifa1_data_b_pins[] = {
2969	/* RXD, TXD */
2970	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2971};
2972static const unsigned int scifa1_data_b_mux[] = {
2973	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2974};
2975static const unsigned int scifa1_clk_b_pins[] = {
2976	/* SCK */
2977	RCAR_GP_PIN(0, 23),
2978};
2979static const unsigned int scifa1_clk_b_mux[] = {
2980	SCIFA1_SCK_B_MARK,
2981};
2982static const unsigned int scifa1_ctrl_b_pins[] = {
2983	/* RTS, CTS */
2984	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2985};
2986static const unsigned int scifa1_ctrl_b_mux[] = {
2987	SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2988};
2989static const unsigned int scifa1_data_c_pins[] = {
2990	/* RXD, TXD */
2991	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2992};
2993static const unsigned int scifa1_data_c_mux[] = {
2994	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2995};
2996static const unsigned int scifa1_clk_c_pins[] = {
2997	/* SCK */
2998	RCAR_GP_PIN(0, 8),
2999};
3000static const unsigned int scifa1_clk_c_mux[] = {
3001	SCIFA1_SCK_C_MARK,
3002};
3003static const unsigned int scifa1_ctrl_c_pins[] = {
3004	/* RTS, CTS */
3005	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
3006};
3007static const unsigned int scifa1_ctrl_c_mux[] = {
3008	SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
3009};
3010static const unsigned int scifa1_data_d_pins[] = {
3011	/* RXD, TXD */
3012	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3013};
3014static const unsigned int scifa1_data_d_mux[] = {
3015	SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
3016};
3017static const unsigned int scifa1_clk_d_pins[] = {
3018	/* SCK */
3019	RCAR_GP_PIN(2, 10),
3020};
3021static const unsigned int scifa1_clk_d_mux[] = {
3022	SCIFA1_SCK_D_MARK,
3023};
3024static const unsigned int scifa1_ctrl_d_pins[] = {
3025	/* RTS, CTS */
3026	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3027};
3028static const unsigned int scifa1_ctrl_d_mux[] = {
3029	SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
3030};
3031/* - SCIFA2 ----------------------------------------------------------------- */
3032static const unsigned int scifa2_data_pins[] = {
3033	/* RXD, TXD */
3034	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3035};
3036static const unsigned int scifa2_data_mux[] = {
3037	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3038};
3039static const unsigned int scifa2_clk_pins[] = {
3040	/* SCK */
3041	RCAR_GP_PIN(5, 4),
3042};
3043static const unsigned int scifa2_clk_mux[] = {
3044	SCIFA2_SCK_MARK,
3045};
3046static const unsigned int scifa2_ctrl_pins[] = {
3047	/* RTS, CTS */
3048	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3049};
3050static const unsigned int scifa2_ctrl_mux[] = {
3051	SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3052};
3053static const unsigned int scifa2_data_b_pins[] = {
3054	/* RXD, TXD */
3055	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3056};
3057static const unsigned int scifa2_data_b_mux[] = {
3058	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3059};
3060static const unsigned int scifa2_data_c_pins[] = {
3061	/* RXD, TXD */
3062	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3063};
3064static const unsigned int scifa2_data_c_mux[] = {
3065	SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3066};
3067static const unsigned int scifa2_clk_c_pins[] = {
3068	/* SCK */
3069	RCAR_GP_PIN(5, 29),
3070};
3071static const unsigned int scifa2_clk_c_mux[] = {
3072	SCIFA2_SCK_C_MARK,
3073};
3074/* - SCIFB0 ----------------------------------------------------------------- */
3075static const unsigned int scifb0_data_pins[] = {
3076	/* RXD, TXD */
3077	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3078};
3079static const unsigned int scifb0_data_mux[] = {
3080	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3081};
3082static const unsigned int scifb0_clk_pins[] = {
3083	/* SCK */
3084	RCAR_GP_PIN(4, 8),
3085};
3086static const unsigned int scifb0_clk_mux[] = {
3087	SCIFB0_SCK_MARK,
3088};
3089static const unsigned int scifb0_ctrl_pins[] = {
3090	/* RTS, CTS */
3091	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3092};
3093static const unsigned int scifb0_ctrl_mux[] = {
3094	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3095};
3096static const unsigned int scifb0_data_b_pins[] = {
3097	/* RXD, TXD */
3098	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3099};
3100static const unsigned int scifb0_data_b_mux[] = {
3101	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3102};
3103static const unsigned int scifb0_clk_b_pins[] = {
3104	/* SCK */
3105	RCAR_GP_PIN(3, 9),
3106};
3107static const unsigned int scifb0_clk_b_mux[] = {
3108	SCIFB0_SCK_B_MARK,
3109};
3110static const unsigned int scifb0_ctrl_b_pins[] = {
3111	/* RTS, CTS */
3112	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3113};
3114static const unsigned int scifb0_ctrl_b_mux[] = {
3115	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3116};
3117static const unsigned int scifb0_data_c_pins[] = {
3118	/* RXD, TXD */
3119	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3120};
3121static const unsigned int scifb0_data_c_mux[] = {
3122	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3123};
3124/* - SCIFB1 ----------------------------------------------------------------- */
3125static const unsigned int scifb1_data_pins[] = {
3126	/* RXD, TXD */
3127	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3128};
3129static const unsigned int scifb1_data_mux[] = {
3130	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3131};
3132static const unsigned int scifb1_clk_pins[] = {
3133	/* SCK */
3134	RCAR_GP_PIN(4, 14),
3135};
3136static const unsigned int scifb1_clk_mux[] = {
3137	SCIFB1_SCK_MARK,
3138};
3139static const unsigned int scifb1_ctrl_pins[] = {
3140	/* RTS, CTS */
3141	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3142};
3143static const unsigned int scifb1_ctrl_mux[] = {
3144	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3145};
3146static const unsigned int scifb1_data_b_pins[] = {
3147	/* RXD, TXD */
3148	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3149};
3150static const unsigned int scifb1_data_b_mux[] = {
3151	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3152};
3153static const unsigned int scifb1_clk_b_pins[] = {
3154	/* SCK */
3155	RCAR_GP_PIN(3, 1),
3156};
3157static const unsigned int scifb1_clk_b_mux[] = {
3158	SCIFB1_SCK_B_MARK,
3159};
3160static const unsigned int scifb1_ctrl_b_pins[] = {
3161	/* RTS, CTS */
3162	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3163};
3164static const unsigned int scifb1_ctrl_b_mux[] = {
3165	SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3166};
3167static const unsigned int scifb1_data_c_pins[] = {
3168	/* RXD, TXD */
3169	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3170};
3171static const unsigned int scifb1_data_c_mux[] = {
3172	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3173};
3174static const unsigned int scifb1_data_d_pins[] = {
3175	/* RXD, TXD */
3176	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3177};
3178static const unsigned int scifb1_data_d_mux[] = {
3179	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3180};
3181static const unsigned int scifb1_data_e_pins[] = {
3182	/* RXD, TXD */
3183	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3184};
3185static const unsigned int scifb1_data_e_mux[] = {
3186	SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3187};
3188static const unsigned int scifb1_clk_e_pins[] = {
3189	/* SCK */
3190	RCAR_GP_PIN(3, 17),
3191};
3192static const unsigned int scifb1_clk_e_mux[] = {
3193	SCIFB1_SCK_E_MARK,
3194};
3195static const unsigned int scifb1_data_f_pins[] = {
3196	/* RXD, TXD */
3197	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3198};
3199static const unsigned int scifb1_data_f_mux[] = {
3200	SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3201};
3202static const unsigned int scifb1_data_g_pins[] = {
3203	/* RXD, TXD */
3204	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3205};
3206static const unsigned int scifb1_data_g_mux[] = {
3207	SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3208};
3209static const unsigned int scifb1_clk_g_pins[] = {
3210	/* SCK */
3211	RCAR_GP_PIN(2, 20),
3212};
3213static const unsigned int scifb1_clk_g_mux[] = {
3214	SCIFB1_SCK_G_MARK,
3215};
3216/* - SCIFB2 ----------------------------------------------------------------- */
3217static const unsigned int scifb2_data_pins[] = {
3218	/* RXD, TXD */
3219	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3220};
3221static const unsigned int scifb2_data_mux[] = {
3222	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3223};
3224static const unsigned int scifb2_clk_pins[] = {
3225	/* SCK */
3226	RCAR_GP_PIN(4, 21),
3227};
3228static const unsigned int scifb2_clk_mux[] = {
3229	SCIFB2_SCK_MARK,
3230};
3231static const unsigned int scifb2_ctrl_pins[] = {
3232	/* RTS, CTS */
3233	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3234};
3235static const unsigned int scifb2_ctrl_mux[] = {
3236	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3237};
3238static const unsigned int scifb2_data_b_pins[] = {
3239	/* RXD, TXD */
3240	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3241};
3242static const unsigned int scifb2_data_b_mux[] = {
3243	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3244};
3245static const unsigned int scifb2_clk_b_pins[] = {
3246	/* SCK */
3247	RCAR_GP_PIN(0, 31),
3248};
3249static const unsigned int scifb2_clk_b_mux[] = {
3250	SCIFB2_SCK_B_MARK,
3251};
3252static const unsigned int scifb2_ctrl_b_pins[] = {
3253	/* RTS, CTS */
3254	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3255};
3256static const unsigned int scifb2_ctrl_b_mux[] = {
3257	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3258};
3259static const unsigned int scifb2_data_c_pins[] = {
3260	/* RXD, TXD */
3261	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3262};
3263static const unsigned int scifb2_data_c_mux[] = {
3264	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3265};
3266/* - SCIF Clock ------------------------------------------------------------- */
3267static const unsigned int scif_clk_pins[] = {
3268	/* SCIF_CLK */
3269	RCAR_GP_PIN(4, 26),
3270};
3271static const unsigned int scif_clk_mux[] = {
3272	SCIF_CLK_MARK,
3273};
3274static const unsigned int scif_clk_b_pins[] = {
3275	/* SCIF_CLK */
3276	RCAR_GP_PIN(5, 4),
3277};
3278static const unsigned int scif_clk_b_mux[] = {
3279	SCIF_CLK_B_MARK,
3280};
3281/* - SDHI0 ------------------------------------------------------------------ */
3282static const unsigned int sdhi0_data_pins[] = {
3283	/* D[0:3] */
3284	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3285};
3286static const unsigned int sdhi0_data_mux[] = {
3287	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3288};
3289static const unsigned int sdhi0_ctrl_pins[] = {
3290	/* CLK, CMD */
3291	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3292};
3293static const unsigned int sdhi0_ctrl_mux[] = {
3294	SD0_CLK_MARK, SD0_CMD_MARK,
3295};
3296static const unsigned int sdhi0_cd_pins[] = {
3297	/* CD */
3298	RCAR_GP_PIN(3, 6),
3299};
3300static const unsigned int sdhi0_cd_mux[] = {
3301	SD0_CD_MARK,
3302};
3303static const unsigned int sdhi0_wp_pins[] = {
3304	/* WP */
3305	RCAR_GP_PIN(3, 7),
3306};
3307static const unsigned int sdhi0_wp_mux[] = {
3308	SD0_WP_MARK,
3309};
3310/* - SDHI1 ------------------------------------------------------------------ */
3311static const unsigned int sdhi1_data_pins[] = {
3312	/* D[0:3] */
3313	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3314};
3315static const unsigned int sdhi1_data_mux[] = {
3316	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3317};
3318static const unsigned int sdhi1_ctrl_pins[] = {
3319	/* CLK, CMD */
3320	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3321};
3322static const unsigned int sdhi1_ctrl_mux[] = {
3323	SD1_CLK_MARK, SD1_CMD_MARK,
3324};
3325static const unsigned int sdhi1_cd_pins[] = {
3326	/* CD */
3327	RCAR_GP_PIN(3, 14),
3328};
3329static const unsigned int sdhi1_cd_mux[] = {
3330	SD1_CD_MARK,
3331};
3332static const unsigned int sdhi1_wp_pins[] = {
3333	/* WP */
3334	RCAR_GP_PIN(3, 15),
3335};
3336static const unsigned int sdhi1_wp_mux[] = {
3337	SD1_WP_MARK,
3338};
3339/* - SDHI2 ------------------------------------------------------------------ */
3340static const unsigned int sdhi2_data_pins[] = {
3341	/* D[0:3] */
3342	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3343};
3344static const unsigned int sdhi2_data_mux[] = {
3345	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3346};
3347static const unsigned int sdhi2_ctrl_pins[] = {
3348	/* CLK, CMD */
3349	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3350};
3351static const unsigned int sdhi2_ctrl_mux[] = {
3352	SD2_CLK_MARK, SD2_CMD_MARK,
3353};
3354static const unsigned int sdhi2_cd_pins[] = {
3355	/* CD */
3356	RCAR_GP_PIN(3, 22),
3357};
3358static const unsigned int sdhi2_cd_mux[] = {
3359	SD2_CD_MARK,
3360};
3361static const unsigned int sdhi2_wp_pins[] = {
3362	/* WP */
3363	RCAR_GP_PIN(3, 23),
3364};
3365static const unsigned int sdhi2_wp_mux[] = {
3366	SD2_WP_MARK,
3367};
3368/* - SDHI3 ------------------------------------------------------------------ */
3369static const unsigned int sdhi3_data_pins[] = {
3370	/* D[0:3] */
3371	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3372};
3373static const unsigned int sdhi3_data_mux[] = {
3374	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3375};
3376static const unsigned int sdhi3_ctrl_pins[] = {
3377	/* CLK, CMD */
3378	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3379};
3380static const unsigned int sdhi3_ctrl_mux[] = {
3381	SD3_CLK_MARK, SD3_CMD_MARK,
3382};
3383static const unsigned int sdhi3_cd_pins[] = {
3384	/* CD */
3385	RCAR_GP_PIN(3, 30),
3386};
3387static const unsigned int sdhi3_cd_mux[] = {
3388	SD3_CD_MARK,
3389};
3390static const unsigned int sdhi3_wp_pins[] = {
3391	/* WP */
3392	RCAR_GP_PIN(3, 31),
3393};
3394static const unsigned int sdhi3_wp_mux[] = {
3395	SD3_WP_MARK,
3396};
3397/* - SSI -------------------------------------------------------------------- */
3398static const unsigned int ssi0_data_pins[] = {
3399	/* SDATA0 */
3400	RCAR_GP_PIN(4, 5),
3401};
3402static const unsigned int ssi0_data_mux[] = {
3403	SSI_SDATA0_MARK,
3404};
3405static const unsigned int ssi0129_ctrl_pins[] = {
3406	/* SCK, WS */
3407	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3408};
3409static const unsigned int ssi0129_ctrl_mux[] = {
3410	SSI_SCK0129_MARK, SSI_WS0129_MARK,
3411};
3412static const unsigned int ssi1_data_pins[] = {
3413	/* SDATA1 */
3414	RCAR_GP_PIN(4, 6),
3415};
3416static const unsigned int ssi1_data_mux[] = {
3417	SSI_SDATA1_MARK,
3418};
3419static const unsigned int ssi1_ctrl_pins[] = {
3420	/* SCK, WS */
3421	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3422};
3423static const unsigned int ssi1_ctrl_mux[] = {
3424	SSI_SCK1_MARK, SSI_WS1_MARK,
3425};
3426static const unsigned int ssi2_data_pins[] = {
3427	/* SDATA2 */
3428	RCAR_GP_PIN(4, 7),
3429};
3430static const unsigned int ssi2_data_mux[] = {
3431	SSI_SDATA2_MARK,
3432};
3433static const unsigned int ssi2_ctrl_pins[] = {
3434	/* SCK, WS */
3435	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3436};
3437static const unsigned int ssi2_ctrl_mux[] = {
3438	SSI_SCK2_MARK, SSI_WS2_MARK,
3439};
3440static const unsigned int ssi3_data_pins[] = {
3441	/* SDATA3 */
3442	RCAR_GP_PIN(4, 10),
3443};
3444static const unsigned int ssi3_data_mux[] = {
3445	SSI_SDATA3_MARK
3446};
3447static const unsigned int ssi34_ctrl_pins[] = {
3448	/* SCK, WS */
3449	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3450};
3451static const unsigned int ssi34_ctrl_mux[] = {
3452	SSI_SCK34_MARK, SSI_WS34_MARK,
3453};
3454static const unsigned int ssi4_data_pins[] = {
3455	/* SDATA4 */
3456	RCAR_GP_PIN(4, 13),
3457};
3458static const unsigned int ssi4_data_mux[] = {
3459	SSI_SDATA4_MARK,
3460};
3461static const unsigned int ssi4_ctrl_pins[] = {
3462	/* SCK, WS */
3463	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3464};
3465static const unsigned int ssi4_ctrl_mux[] = {
3466	SSI_SCK4_MARK, SSI_WS4_MARK,
3467};
3468static const unsigned int ssi5_pins[] = {
3469	/* SDATA5, SCK, WS */
3470	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3471};
3472static const unsigned int ssi5_mux[] = {
3473	SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3474};
3475static const unsigned int ssi5_b_pins[] = {
3476	/* SDATA5, SCK, WS */
3477	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3478};
3479static const unsigned int ssi5_b_mux[] = {
3480	SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3481};
3482static const unsigned int ssi5_c_pins[] = {
3483	/* SDATA5, SCK, WS */
3484	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3485};
3486static const unsigned int ssi5_c_mux[] = {
3487	SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3488};
3489static const unsigned int ssi6_pins[] = {
3490	/* SDATA6, SCK, WS */
3491	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3492};
3493static const unsigned int ssi6_mux[] = {
3494	SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3495};
3496static const unsigned int ssi6_b_pins[] = {
3497	/* SDATA6, SCK, WS */
3498	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3499};
3500static const unsigned int ssi6_b_mux[] = {
3501	SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3502};
3503static const unsigned int ssi7_data_pins[] = {
3504	/* SDATA7 */
3505	RCAR_GP_PIN(4, 22),
3506};
3507static const unsigned int ssi7_data_mux[] = {
3508	SSI_SDATA7_MARK,
3509};
3510static const unsigned int ssi7_b_data_pins[] = {
3511	/* SDATA7 */
3512	RCAR_GP_PIN(4, 22),
3513};
3514static const unsigned int ssi7_b_data_mux[] = {
3515	SSI_SDATA7_B_MARK,
3516};
3517static const unsigned int ssi7_c_data_pins[] = {
3518	/* SDATA7 */
3519	RCAR_GP_PIN(1, 26),
3520};
3521static const unsigned int ssi7_c_data_mux[] = {
3522	SSI_SDATA7_C_MARK,
3523};
3524static const unsigned int ssi78_ctrl_pins[] = {
3525	/* SCK, WS */
3526	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3527};
3528static const unsigned int ssi78_ctrl_mux[] = {
3529	SSI_SCK78_MARK, SSI_WS78_MARK,
3530};
3531static const unsigned int ssi78_b_ctrl_pins[] = {
3532	/* SCK, WS */
3533	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3534};
3535static const unsigned int ssi78_b_ctrl_mux[] = {
3536	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3537};
3538static const unsigned int ssi78_c_ctrl_pins[] = {
3539	/* SCK, WS */
3540	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3541};
3542static const unsigned int ssi78_c_ctrl_mux[] = {
3543	SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3544};
3545static const unsigned int ssi8_data_pins[] = {
3546	/* SDATA8 */
3547	RCAR_GP_PIN(4, 23),
3548};
3549static const unsigned int ssi8_data_mux[] = {
3550	SSI_SDATA8_MARK,
3551};
3552static const unsigned int ssi8_b_data_pins[] = {
3553	/* SDATA8 */
3554	RCAR_GP_PIN(4, 23),
3555};
3556static const unsigned int ssi8_b_data_mux[] = {
3557	SSI_SDATA8_B_MARK,
3558};
3559static const unsigned int ssi8_c_data_pins[] = {
3560	/* SDATA8 */
3561	RCAR_GP_PIN(1, 27),
3562};
3563static const unsigned int ssi8_c_data_mux[] = {
3564	SSI_SDATA8_C_MARK,
3565};
3566static const unsigned int ssi9_data_pins[] = {
3567	/* SDATA9 */
3568	RCAR_GP_PIN(4, 24),
3569};
3570static const unsigned int ssi9_data_mux[] = {
3571	SSI_SDATA9_MARK,
3572};
3573static const unsigned int ssi9_ctrl_pins[] = {
3574	/* SCK, WS */
3575	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3576};
3577static const unsigned int ssi9_ctrl_mux[] = {
3578	SSI_SCK9_MARK, SSI_WS9_MARK,
3579};
3580/* - TPU0 ------------------------------------------------------------------- */
3581static const unsigned int tpu0_to0_pins[] = {
3582	/* TO */
3583	RCAR_GP_PIN(0, 20),
3584};
3585static const unsigned int tpu0_to0_mux[] = {
3586	TPU0TO0_MARK,
3587};
3588static const unsigned int tpu0_to1_pins[] = {
3589	/* TO */
3590	RCAR_GP_PIN(0, 21),
3591};
3592static const unsigned int tpu0_to1_mux[] = {
3593	TPU0TO1_MARK,
3594};
3595static const unsigned int tpu0_to2_pins[] = {
3596	/* TO */
3597	RCAR_GP_PIN(0, 22),
3598};
3599static const unsigned int tpu0_to2_mux[] = {
3600	TPU0TO2_MARK,
3601};
3602static const unsigned int tpu0_to3_pins[] = {
3603	/* TO */
3604	RCAR_GP_PIN(0, 23),
3605};
3606static const unsigned int tpu0_to3_mux[] = {
3607	TPU0TO3_MARK,
3608};
3609/* - USB0 ------------------------------------------------------------------- */
3610static const unsigned int usb0_pins[] = {
3611	/* OVC/VBUS, PWEN */
3612	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18),
3613};
3614static const unsigned int usb0_mux[] = {
3615	USB0_OVC_VBUS_MARK, USB0_PWEN_MARK,
3616};
3617/* - USB1 ------------------------------------------------------------------- */
3618static const unsigned int usb1_pins[] = {
3619	/* PWEN, OVC */
3620	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3621};
3622static const unsigned int usb1_mux[] = {
3623	USB1_PWEN_MARK, USB1_OVC_MARK,
3624};
3625/* - USB2 ------------------------------------------------------------------- */
3626static const unsigned int usb2_pins[] = {
3627	/* PWEN, OVC */
3628	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3629};
3630static const unsigned int usb2_mux[] = {
3631	USB2_PWEN_MARK, USB2_OVC_MARK,
3632};
3633/* - VIN0 ------------------------------------------------------------------- */
3634static const unsigned int vin0_data_pins[] = {
3635	/* B */
3636	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3637	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3638	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3639	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3640	/* G */
3641	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3642	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3643	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3644	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3645	/* R */
3646	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3647	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3648	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3649	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3650};
3651static const unsigned int vin0_data_mux[] = {
3652	/* B */
3653	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3654	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3655	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3656	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3657	/* G */
3658	VI0_G0_MARK, VI0_G1_MARK,
3659	VI0_G2_MARK, VI0_G3_MARK,
3660	VI0_G4_MARK, VI0_G5_MARK,
3661	VI0_G6_MARK, VI0_G7_MARK,
3662	/* R */
3663	VI0_R0_MARK, VI0_R1_MARK,
3664	VI0_R2_MARK, VI0_R3_MARK,
3665	VI0_R4_MARK, VI0_R5_MARK,
3666	VI0_R6_MARK, VI0_R7_MARK,
3667};
3668static const unsigned int vin0_data18_pins[] = {
3669	/* B */
3670	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3671	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3672	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3673	/* G */
3674	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3675	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3676	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3677	/* R */
3678	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3679	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3680	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3681};
3682static const unsigned int vin0_data18_mux[] = {
3683	/* B */
3684	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3685	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3686	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3687	/* G */
3688	VI0_G2_MARK, VI0_G3_MARK,
3689	VI0_G4_MARK, VI0_G5_MARK,
3690	VI0_G6_MARK, VI0_G7_MARK,
3691	/* R */
3692	VI0_R2_MARK, VI0_R3_MARK,
3693	VI0_R4_MARK, VI0_R5_MARK,
3694	VI0_R6_MARK, VI0_R7_MARK,
3695};
3696static const unsigned int vin0_sync_pins[] = {
3697	RCAR_GP_PIN(0, 12), /* HSYNC */
3698	RCAR_GP_PIN(0, 13), /* VSYNC */
3699};
3700static const unsigned int vin0_sync_mux[] = {
3701	VI0_HSYNC_N_MARK,
3702	VI0_VSYNC_N_MARK,
3703};
3704static const unsigned int vin0_field_pins[] = {
3705	RCAR_GP_PIN(0, 15),
3706};
3707static const unsigned int vin0_field_mux[] = {
3708	VI0_FIELD_MARK,
3709};
3710static const unsigned int vin0_clkenb_pins[] = {
3711	RCAR_GP_PIN(0, 14),
3712};
3713static const unsigned int vin0_clkenb_mux[] = {
3714	VI0_CLKENB_MARK,
3715};
3716static const unsigned int vin0_clk_pins[] = {
3717	RCAR_GP_PIN(2, 0),
3718};
3719static const unsigned int vin0_clk_mux[] = {
3720	VI0_CLK_MARK,
3721};
3722/* - VIN1 ------------------------------------------------------------------- */
3723static const unsigned int vin1_data_pins[] = {
3724	/* B */
3725	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3726	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3727	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3728	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3729	/* G */
3730	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3731	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3732	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3733	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3734	/* R */
3735	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3736	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3737	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3738	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3739};
3740static const unsigned int vin1_data_mux[] = {
3741	/* B */
3742	VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3743	VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3744	VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3745	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3746	/* G */
3747	VI1_G0_MARK, VI1_G1_MARK,
3748	VI1_G2_MARK, VI1_G3_MARK,
3749	VI1_G4_MARK, VI1_G5_MARK,
3750	VI1_G6_MARK, VI1_G7_MARK,
3751	/* R */
3752	VI1_R0_MARK, VI1_R1_MARK,
3753	VI1_R2_MARK, VI1_R3_MARK,
3754	VI1_R4_MARK, VI1_R5_MARK,
3755	VI1_R6_MARK, VI1_R7_MARK,
3756};
3757static const unsigned int vin1_data18_pins[] = {
3758	/* B */
3759	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3760	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3761	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3762	/* G */
3763	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3764	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3765	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3766	/* R */
3767	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3768	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3769	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3770};
3771static const unsigned int vin1_data18_mux[] = {
3772	/* B */
3773	VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3774	VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3775	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3776	/* G */
3777	VI1_G2_MARK, VI1_G3_MARK,
3778	VI1_G4_MARK, VI1_G5_MARK,
3779	VI1_G6_MARK, VI1_G7_MARK,
3780	/* R */
3781	VI1_R2_MARK, VI1_R3_MARK,
3782	VI1_R4_MARK, VI1_R5_MARK,
3783	VI1_R6_MARK, VI1_R7_MARK,
3784};
3785static const unsigned int vin1_data_b_pins[] = {
3786	/* B */
3787	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3788	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3789	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3790	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3791	/* G */
3792	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3793	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3794	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3795	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3796	/* R */
3797	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3798	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3799	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3800	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3801};
3802static const unsigned int vin1_data_b_mux[] = {
3803	/* B */
3804	VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
3805	VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3806	VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3807	VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3808	/* G */
3809	VI1_G0_B_MARK, VI1_G1_B_MARK,
3810	VI1_G2_B_MARK, VI1_G3_B_MARK,
3811	VI1_G4_B_MARK, VI1_G5_B_MARK,
3812	VI1_G6_B_MARK, VI1_G7_B_MARK,
3813	/* R */
3814	VI1_R0_B_MARK, VI1_R1_B_MARK,
3815	VI1_R2_B_MARK, VI1_R3_B_MARK,
3816	VI1_R4_B_MARK, VI1_R5_B_MARK,
3817	VI1_R6_B_MARK, VI1_R7_B_MARK,
3818};
3819static const unsigned int vin1_data18_b_pins[] = {
3820	/* B */
3821	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3822	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3823	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3824	/* G */
3825	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3826	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3827	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3828	/* R */
3829	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3830	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3831	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3832};
3833static const unsigned int vin1_data18_b_mux[] = {
3834	/* B */
3835	VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3836	VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3837	VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3838	/* G */
3839	VI1_G2_B_MARK, VI1_G3_B_MARK,
3840	VI1_G4_B_MARK, VI1_G5_B_MARK,
3841	VI1_G6_B_MARK, VI1_G7_B_MARK,
3842	/* R */
3843	VI1_R2_B_MARK, VI1_R3_B_MARK,
3844	VI1_R4_B_MARK, VI1_R5_B_MARK,
3845	VI1_R6_B_MARK, VI1_R7_B_MARK,
3846};
3847static const unsigned int vin1_sync_pins[] = {
3848	RCAR_GP_PIN(1, 24), /* HSYNC */
3849	RCAR_GP_PIN(1, 25), /* VSYNC */
3850};
3851static const unsigned int vin1_sync_mux[] = {
3852	VI1_HSYNC_N_MARK,
3853	VI1_VSYNC_N_MARK,
3854};
3855static const unsigned int vin1_sync_b_pins[] = {
3856	RCAR_GP_PIN(1, 24), /* HSYNC */
3857	RCAR_GP_PIN(1, 25), /* VSYNC */
3858};
3859static const unsigned int vin1_sync_b_mux[] = {
3860	VI1_HSYNC_N_B_MARK,
3861	VI1_VSYNC_N_B_MARK,
3862};
3863static const unsigned int vin1_field_pins[] = {
3864	RCAR_GP_PIN(1, 13),
3865};
3866static const unsigned int vin1_field_mux[] = {
3867	VI1_FIELD_MARK,
3868};
3869static const unsigned int vin1_field_b_pins[] = {
3870	RCAR_GP_PIN(1, 13),
3871};
3872static const unsigned int vin1_field_b_mux[] = {
3873	VI1_FIELD_B_MARK,
3874};
3875static const unsigned int vin1_clkenb_pins[] = {
3876	RCAR_GP_PIN(1, 26),
3877};
3878static const unsigned int vin1_clkenb_mux[] = {
3879	VI1_CLKENB_MARK,
3880};
3881static const unsigned int vin1_clkenb_b_pins[] = {
3882	RCAR_GP_PIN(1, 26),
3883};
3884static const unsigned int vin1_clkenb_b_mux[] = {
3885	VI1_CLKENB_B_MARK,
3886};
3887static const unsigned int vin1_clk_pins[] = {
3888	RCAR_GP_PIN(2, 9),
3889};
3890static const unsigned int vin1_clk_mux[] = {
3891	VI1_CLK_MARK,
3892};
3893static const unsigned int vin1_clk_b_pins[] = {
3894	RCAR_GP_PIN(3, 15),
3895};
3896static const unsigned int vin1_clk_b_mux[] = {
3897	VI1_CLK_B_MARK,
3898};
3899/* - VIN2 ----------------------------------------------------------------- */
3900static const unsigned int vin2_data_pins[] = {
3901	/* B */
3902	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3903	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3904	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3905	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3906	/* G */
3907	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3908	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3909	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3910	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3911	/* R */
3912	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3913	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3914	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3915	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3916};
3917static const unsigned int vin2_data_mux[] = {
3918	/* B */
3919	VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3920	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3921	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3922	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3923	/* G */
3924	VI2_G0_MARK, VI2_G1_MARK,
3925	VI2_G2_MARK, VI2_G3_MARK,
3926	VI2_G4_MARK, VI2_G5_MARK,
3927	VI2_G6_MARK, VI2_G7_MARK,
3928	/* R */
3929	VI2_R0_MARK, VI2_R1_MARK,
3930	VI2_R2_MARK, VI2_R3_MARK,
3931	VI2_R4_MARK, VI2_R5_MARK,
3932	VI2_R6_MARK, VI2_R7_MARK,
3933};
3934static const unsigned int vin2_data18_pins[] = {
3935	/* B */
3936	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3937	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3938	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3939	/* G */
3940	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3941	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3942	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3943	/* R */
3944	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3945	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3946	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3947};
3948static const unsigned int vin2_data18_mux[] = {
3949	/* B */
3950	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3951	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3952	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3953	/* G */
3954	VI2_G2_MARK, VI2_G3_MARK,
3955	VI2_G4_MARK, VI2_G5_MARK,
3956	VI2_G6_MARK, VI2_G7_MARK,
3957	/* R */
3958	VI2_R2_MARK, VI2_R3_MARK,
3959	VI2_R4_MARK, VI2_R5_MARK,
3960	VI2_R6_MARK, VI2_R7_MARK,
3961};
3962static const unsigned int vin2_sync_pins[] = {
3963	RCAR_GP_PIN(1, 16), /* HSYNC */
3964	RCAR_GP_PIN(1, 21), /* VSYNC */
3965};
3966static const unsigned int vin2_sync_mux[] = {
3967	VI2_HSYNC_N_MARK,
3968	VI2_VSYNC_N_MARK,
3969};
3970static const unsigned int vin2_field_pins[] = {
3971	RCAR_GP_PIN(1, 9),
3972};
3973static const unsigned int vin2_field_mux[] = {
3974	VI2_FIELD_MARK,
3975};
3976static const unsigned int vin2_clkenb_pins[] = {
3977	RCAR_GP_PIN(1, 8),
3978};
3979static const unsigned int vin2_clkenb_mux[] = {
3980	VI2_CLKENB_MARK,
3981};
3982static const unsigned int vin2_clk_pins[] = {
3983	RCAR_GP_PIN(1, 11),
3984};
3985static const unsigned int vin2_clk_mux[] = {
3986	VI2_CLK_MARK,
3987};
3988/* - VIN3 ----------------------------------------------------------------- */
3989static const unsigned int vin3_data8_pins[] = {
3990	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3991	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3992	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3993	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3994};
3995static const unsigned int vin3_data8_mux[] = {
3996	VI3_DATA0_MARK, VI3_DATA1_MARK,
3997	VI3_DATA2_MARK, VI3_DATA3_MARK,
3998	VI3_DATA4_MARK, VI3_DATA5_MARK,
3999	VI3_DATA6_MARK, VI3_DATA7_MARK,
4000};
4001static const unsigned int vin3_sync_pins[] = {
4002	RCAR_GP_PIN(1, 16), /* HSYNC */
4003	RCAR_GP_PIN(1, 17), /* VSYNC */
4004};
4005static const unsigned int vin3_sync_mux[] = {
4006	VI3_HSYNC_N_MARK,
4007	VI3_VSYNC_N_MARK,
4008};
4009static const unsigned int vin3_field_pins[] = {
4010	RCAR_GP_PIN(1, 15),
4011};
4012static const unsigned int vin3_field_mux[] = {
4013	VI3_FIELD_MARK,
4014};
4015static const unsigned int vin3_clkenb_pins[] = {
4016	RCAR_GP_PIN(1, 14),
4017};
4018static const unsigned int vin3_clkenb_mux[] = {
4019	VI3_CLKENB_MARK,
4020};
4021static const unsigned int vin3_clk_pins[] = {
4022	RCAR_GP_PIN(1, 23),
4023};
4024static const unsigned int vin3_clk_mux[] = {
4025	VI3_CLK_MARK,
4026};
4027
4028static const struct {
4029	struct sh_pfc_pin_group common[311];
4030#ifdef CONFIG_PINCTRL_PFC_R8A7790
4031	struct sh_pfc_pin_group automotive[1];
4032#endif
4033} pinmux_groups = {
4034	.common = {
4035		SH_PFC_PIN_GROUP(audio_clk_a),
4036		SH_PFC_PIN_GROUP(audio_clk_b),
4037		SH_PFC_PIN_GROUP(audio_clk_c),
4038		SH_PFC_PIN_GROUP(audio_clkout),
4039		SH_PFC_PIN_GROUP(audio_clkout_b),
4040		SH_PFC_PIN_GROUP(audio_clkout_c),
4041		SH_PFC_PIN_GROUP(audio_clkout_d),
4042		SH_PFC_PIN_GROUP(avb_link),
4043		SH_PFC_PIN_GROUP(avb_magic),
4044		SH_PFC_PIN_GROUP(avb_phy_int),
4045		SH_PFC_PIN_GROUP(avb_mdio),
4046		SH_PFC_PIN_GROUP(avb_mii),
4047		SH_PFC_PIN_GROUP(avb_gmii),
4048		SH_PFC_PIN_GROUP(can0_data),
4049		SH_PFC_PIN_GROUP(can0_data_b),
4050		SH_PFC_PIN_GROUP(can0_data_c),
4051		SH_PFC_PIN_GROUP(can0_data_d),
4052		SH_PFC_PIN_GROUP(can1_data),
4053		SH_PFC_PIN_GROUP(can1_data_b),
4054		SH_PFC_PIN_GROUP(can_clk),
4055		SH_PFC_PIN_GROUP(can_clk_b),
4056		SH_PFC_PIN_GROUP(du_rgb666),
4057		SH_PFC_PIN_GROUP(du_rgb888),
4058		SH_PFC_PIN_GROUP(du_clk_out_0),
4059		SH_PFC_PIN_GROUP(du_clk_out_1),
4060		SH_PFC_PIN_GROUP(du_sync_0),
4061		SH_PFC_PIN_GROUP(du_sync_1),
4062		SH_PFC_PIN_GROUP(du_cde),
4063		SH_PFC_PIN_GROUP(du0_clk_in),
4064		SH_PFC_PIN_GROUP(du1_clk_in),
4065		SH_PFC_PIN_GROUP(du2_clk_in),
4066		SH_PFC_PIN_GROUP(eth_link),
4067		SH_PFC_PIN_GROUP(eth_magic),
4068		SH_PFC_PIN_GROUP(eth_mdio),
4069		SH_PFC_PIN_GROUP(eth_rmii),
4070		SH_PFC_PIN_GROUP(hscif0_data),
4071		SH_PFC_PIN_GROUP(hscif0_clk),
4072		SH_PFC_PIN_GROUP(hscif0_ctrl),
4073		SH_PFC_PIN_GROUP(hscif0_data_b),
4074		SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4075		SH_PFC_PIN_GROUP(hscif0_data_c),
4076		SH_PFC_PIN_GROUP(hscif0_ctrl_c),
4077		SH_PFC_PIN_GROUP(hscif0_data_d),
4078		SH_PFC_PIN_GROUP(hscif0_ctrl_d),
4079		SH_PFC_PIN_GROUP(hscif0_data_e),
4080		SH_PFC_PIN_GROUP(hscif0_ctrl_e),
4081		SH_PFC_PIN_GROUP(hscif0_data_f),
4082		SH_PFC_PIN_GROUP(hscif0_ctrl_f),
4083		SH_PFC_PIN_GROUP(hscif1_data),
4084		SH_PFC_PIN_GROUP(hscif1_clk),
4085		SH_PFC_PIN_GROUP(hscif1_ctrl),
4086		SH_PFC_PIN_GROUP(hscif1_data_b),
4087		SH_PFC_PIN_GROUP(hscif1_clk_b),
4088		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4089		SH_PFC_PIN_GROUP(i2c0),
4090		SH_PFC_PIN_GROUP(i2c1),
4091		SH_PFC_PIN_GROUP(i2c1_b),
4092		SH_PFC_PIN_GROUP(i2c1_c),
4093		SH_PFC_PIN_GROUP(i2c2),
4094		SH_PFC_PIN_GROUP(i2c2_b),
4095		SH_PFC_PIN_GROUP(i2c2_c),
4096		SH_PFC_PIN_GROUP(i2c2_d),
4097		SH_PFC_PIN_GROUP(i2c2_e),
4098		SH_PFC_PIN_GROUP(i2c3),
4099		SH_PFC_PIN_GROUP(iic0),
4100		SH_PFC_PIN_GROUP(iic1),
4101		SH_PFC_PIN_GROUP(iic1_b),
4102		SH_PFC_PIN_GROUP(iic1_c),
4103		SH_PFC_PIN_GROUP(iic2),
4104		SH_PFC_PIN_GROUP(iic2_b),
4105		SH_PFC_PIN_GROUP(iic2_c),
4106		SH_PFC_PIN_GROUP(iic2_d),
4107		SH_PFC_PIN_GROUP(iic2_e),
4108		SH_PFC_PIN_GROUP(iic3),
4109		SH_PFC_PIN_GROUP(intc_irq0),
4110		SH_PFC_PIN_GROUP(intc_irq1),
4111		SH_PFC_PIN_GROUP(intc_irq2),
4112		SH_PFC_PIN_GROUP(intc_irq3),
4113		BUS_DATA_PIN_GROUP(mmc0_data, 1),
4114		BUS_DATA_PIN_GROUP(mmc0_data, 4),
4115		BUS_DATA_PIN_GROUP(mmc0_data, 8),
4116		SH_PFC_PIN_GROUP(mmc0_ctrl),
4117		BUS_DATA_PIN_GROUP(mmc1_data, 1),
4118		BUS_DATA_PIN_GROUP(mmc1_data, 4),
4119		BUS_DATA_PIN_GROUP(mmc1_data, 8),
4120		SH_PFC_PIN_GROUP(mmc1_ctrl),
4121		SH_PFC_PIN_GROUP(msiof0_clk),
4122		SH_PFC_PIN_GROUP(msiof0_sync),
4123		SH_PFC_PIN_GROUP(msiof0_ss1),
4124		SH_PFC_PIN_GROUP(msiof0_ss2),
4125		SH_PFC_PIN_GROUP(msiof0_rx),
4126		SH_PFC_PIN_GROUP(msiof0_tx),
4127		SH_PFC_PIN_GROUP(msiof0_clk_b),
4128		SH_PFC_PIN_GROUP(msiof0_ss1_b),
4129		SH_PFC_PIN_GROUP(msiof0_ss2_b),
4130		SH_PFC_PIN_GROUP(msiof0_rx_b),
4131		SH_PFC_PIN_GROUP(msiof0_tx_b),
4132		SH_PFC_PIN_GROUP(msiof1_clk),
4133		SH_PFC_PIN_GROUP(msiof1_sync),
4134		SH_PFC_PIN_GROUP(msiof1_ss1),
4135		SH_PFC_PIN_GROUP(msiof1_ss2),
4136		SH_PFC_PIN_GROUP(msiof1_rx),
4137		SH_PFC_PIN_GROUP(msiof1_tx),
4138		SH_PFC_PIN_GROUP(msiof1_clk_b),
4139		SH_PFC_PIN_GROUP(msiof1_ss1_b),
4140		SH_PFC_PIN_GROUP(msiof1_ss2_b),
4141		SH_PFC_PIN_GROUP(msiof1_rx_b),
4142		SH_PFC_PIN_GROUP(msiof1_tx_b),
4143		SH_PFC_PIN_GROUP(msiof2_clk),
4144		SH_PFC_PIN_GROUP(msiof2_sync),
4145		SH_PFC_PIN_GROUP(msiof2_ss1),
4146		SH_PFC_PIN_GROUP(msiof2_ss2),
4147		SH_PFC_PIN_GROUP(msiof2_rx),
4148		SH_PFC_PIN_GROUP(msiof2_tx),
4149		SH_PFC_PIN_GROUP(msiof3_clk),
4150		SH_PFC_PIN_GROUP(msiof3_sync),
4151		SH_PFC_PIN_GROUP(msiof3_ss1),
4152		SH_PFC_PIN_GROUP(msiof3_ss2),
4153		SH_PFC_PIN_GROUP(msiof3_rx),
4154		SH_PFC_PIN_GROUP(msiof3_tx),
4155		SH_PFC_PIN_GROUP(msiof3_clk_b),
4156		SH_PFC_PIN_GROUP(msiof3_sync_b),
4157		SH_PFC_PIN_GROUP(msiof3_rx_b),
4158		SH_PFC_PIN_GROUP(msiof3_tx_b),
4159		SH_PFC_PIN_GROUP(pwm0),
4160		SH_PFC_PIN_GROUP(pwm0_b),
4161		SH_PFC_PIN_GROUP(pwm1),
4162		SH_PFC_PIN_GROUP(pwm1_b),
4163		SH_PFC_PIN_GROUP(pwm2),
4164		SH_PFC_PIN_GROUP(pwm3),
4165		SH_PFC_PIN_GROUP(pwm4),
4166		SH_PFC_PIN_GROUP(pwm5),
4167		SH_PFC_PIN_GROUP(pwm6),
4168		SH_PFC_PIN_GROUP(qspi_ctrl),
4169		BUS_DATA_PIN_GROUP(qspi_data, 2),
4170		BUS_DATA_PIN_GROUP(qspi_data, 4),
4171		SH_PFC_PIN_GROUP(scif0_data),
4172		SH_PFC_PIN_GROUP(scif0_clk),
4173		SH_PFC_PIN_GROUP(scif0_ctrl),
4174		SH_PFC_PIN_GROUP(scif0_data_b),
4175		SH_PFC_PIN_GROUP(scif1_data),
4176		SH_PFC_PIN_GROUP(scif1_clk),
4177		SH_PFC_PIN_GROUP(scif1_ctrl),
4178		SH_PFC_PIN_GROUP(scif1_data_b),
4179		SH_PFC_PIN_GROUP(scif1_data_c),
4180		SH_PFC_PIN_GROUP(scif1_data_d),
4181		SH_PFC_PIN_GROUP(scif1_clk_d),
4182		SH_PFC_PIN_GROUP(scif1_data_e),
4183		SH_PFC_PIN_GROUP(scif1_clk_e),
4184		SH_PFC_PIN_GROUP(scif2_data),
4185		SH_PFC_PIN_GROUP(scif2_clk),
4186		SH_PFC_PIN_GROUP(scif2_data_b),
4187		SH_PFC_PIN_GROUP(scifa0_data),
4188		SH_PFC_PIN_GROUP(scifa0_clk),
4189		SH_PFC_PIN_GROUP(scifa0_ctrl),
4190		SH_PFC_PIN_GROUP(scifa0_data_b),
4191		SH_PFC_PIN_GROUP(scifa0_clk_b),
4192		SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4193		SH_PFC_PIN_GROUP(scifa1_data),
4194		SH_PFC_PIN_GROUP(scifa1_clk),
4195		SH_PFC_PIN_GROUP(scifa1_ctrl),
4196		SH_PFC_PIN_GROUP(scifa1_data_b),
4197		SH_PFC_PIN_GROUP(scifa1_clk_b),
4198		SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4199		SH_PFC_PIN_GROUP(scifa1_data_c),
4200		SH_PFC_PIN_GROUP(scifa1_clk_c),
4201		SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4202		SH_PFC_PIN_GROUP(scifa1_data_d),
4203		SH_PFC_PIN_GROUP(scifa1_clk_d),
4204		SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4205		SH_PFC_PIN_GROUP(scifa2_data),
4206		SH_PFC_PIN_GROUP(scifa2_clk),
4207		SH_PFC_PIN_GROUP(scifa2_ctrl),
4208		SH_PFC_PIN_GROUP(scifa2_data_b),
4209		SH_PFC_PIN_GROUP(scifa2_data_c),
4210		SH_PFC_PIN_GROUP(scifa2_clk_c),
4211		SH_PFC_PIN_GROUP(scifb0_data),
4212		SH_PFC_PIN_GROUP(scifb0_clk),
4213		SH_PFC_PIN_GROUP(scifb0_ctrl),
4214		SH_PFC_PIN_GROUP(scifb0_data_b),
4215		SH_PFC_PIN_GROUP(scifb0_clk_b),
4216		SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4217		SH_PFC_PIN_GROUP(scifb0_data_c),
4218		SH_PFC_PIN_GROUP(scifb1_data),
4219		SH_PFC_PIN_GROUP(scifb1_clk),
4220		SH_PFC_PIN_GROUP(scifb1_ctrl),
4221		SH_PFC_PIN_GROUP(scifb1_data_b),
4222		SH_PFC_PIN_GROUP(scifb1_clk_b),
4223		SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4224		SH_PFC_PIN_GROUP(scifb1_data_c),
4225		SH_PFC_PIN_GROUP(scifb1_data_d),
4226		SH_PFC_PIN_GROUP(scifb1_data_e),
4227		SH_PFC_PIN_GROUP(scifb1_clk_e),
4228		SH_PFC_PIN_GROUP(scifb1_data_f),
4229		SH_PFC_PIN_GROUP(scifb1_data_g),
4230		SH_PFC_PIN_GROUP(scifb1_clk_g),
4231		SH_PFC_PIN_GROUP(scifb2_data),
4232		SH_PFC_PIN_GROUP(scifb2_clk),
4233		SH_PFC_PIN_GROUP(scifb2_ctrl),
4234		SH_PFC_PIN_GROUP(scifb2_data_b),
4235		SH_PFC_PIN_GROUP(scifb2_clk_b),
4236		SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4237		SH_PFC_PIN_GROUP(scifb2_data_c),
4238		SH_PFC_PIN_GROUP(scif_clk),
4239		SH_PFC_PIN_GROUP(scif_clk_b),
4240		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4241		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4242		SH_PFC_PIN_GROUP(sdhi0_ctrl),
4243		SH_PFC_PIN_GROUP(sdhi0_cd),
4244		SH_PFC_PIN_GROUP(sdhi0_wp),
4245		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4246		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4247		SH_PFC_PIN_GROUP(sdhi1_ctrl),
4248		SH_PFC_PIN_GROUP(sdhi1_cd),
4249		SH_PFC_PIN_GROUP(sdhi1_wp),
4250		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4251		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4252		SH_PFC_PIN_GROUP(sdhi2_ctrl),
4253		SH_PFC_PIN_GROUP(sdhi2_cd),
4254		SH_PFC_PIN_GROUP(sdhi2_wp),
4255		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4256		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4257		SH_PFC_PIN_GROUP(sdhi3_ctrl),
4258		SH_PFC_PIN_GROUP(sdhi3_cd),
4259		SH_PFC_PIN_GROUP(sdhi3_wp),
4260		SH_PFC_PIN_GROUP(ssi0_data),
4261		SH_PFC_PIN_GROUP(ssi0129_ctrl),
4262		SH_PFC_PIN_GROUP(ssi1_data),
4263		SH_PFC_PIN_GROUP(ssi1_ctrl),
4264		SH_PFC_PIN_GROUP(ssi2_data),
4265		SH_PFC_PIN_GROUP(ssi2_ctrl),
4266		SH_PFC_PIN_GROUP(ssi3_data),
4267		SH_PFC_PIN_GROUP(ssi34_ctrl),
4268		SH_PFC_PIN_GROUP(ssi4_data),
4269		SH_PFC_PIN_GROUP(ssi4_ctrl),
4270		SH_PFC_PIN_GROUP(ssi5),
4271		SH_PFC_PIN_GROUP(ssi5_b),
4272		SH_PFC_PIN_GROUP(ssi5_c),
4273		SH_PFC_PIN_GROUP(ssi6),
4274		SH_PFC_PIN_GROUP(ssi6_b),
4275		SH_PFC_PIN_GROUP(ssi7_data),
4276		SH_PFC_PIN_GROUP(ssi7_b_data),
4277		SH_PFC_PIN_GROUP(ssi7_c_data),
4278		SH_PFC_PIN_GROUP(ssi78_ctrl),
4279		SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4280		SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4281		SH_PFC_PIN_GROUP(ssi8_data),
4282		SH_PFC_PIN_GROUP(ssi8_b_data),
4283		SH_PFC_PIN_GROUP(ssi8_c_data),
4284		SH_PFC_PIN_GROUP(ssi9_data),
4285		SH_PFC_PIN_GROUP(ssi9_ctrl),
4286		SH_PFC_PIN_GROUP(tpu0_to0),
4287		SH_PFC_PIN_GROUP(tpu0_to1),
4288		SH_PFC_PIN_GROUP(tpu0_to2),
4289		SH_PFC_PIN_GROUP(tpu0_to3),
4290		SH_PFC_PIN_GROUP(usb0),
4291		SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
4292		SH_PFC_PIN_GROUP(usb1),
4293		SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
4294		SH_PFC_PIN_GROUP(usb2),
4295		BUS_DATA_PIN_GROUP(vin0_data, 24),
4296		BUS_DATA_PIN_GROUP(vin0_data, 20),
4297		SH_PFC_PIN_GROUP(vin0_data18),
4298		BUS_DATA_PIN_GROUP(vin0_data, 16),
4299		BUS_DATA_PIN_GROUP(vin0_data, 12),
4300		BUS_DATA_PIN_GROUP(vin0_data, 10),
4301		BUS_DATA_PIN_GROUP(vin0_data, 8),
4302		BUS_DATA_PIN_GROUP(vin0_data, 4),
4303		SH_PFC_PIN_GROUP(vin0_sync),
4304		SH_PFC_PIN_GROUP(vin0_field),
4305		SH_PFC_PIN_GROUP(vin0_clkenb),
4306		SH_PFC_PIN_GROUP(vin0_clk),
4307		BUS_DATA_PIN_GROUP(vin1_data, 24),
4308		BUS_DATA_PIN_GROUP(vin1_data, 20),
4309		SH_PFC_PIN_GROUP(vin1_data18),
4310		BUS_DATA_PIN_GROUP(vin1_data, 16),
4311		BUS_DATA_PIN_GROUP(vin1_data, 12),
4312		BUS_DATA_PIN_GROUP(vin1_data, 10),
4313		BUS_DATA_PIN_GROUP(vin1_data, 8),
4314		BUS_DATA_PIN_GROUP(vin1_data, 4),
4315		BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
4316		BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
4317		SH_PFC_PIN_GROUP(vin1_data18_b),
4318		BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
4319		BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
4320		BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
4321		BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
4322		BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
4323		SH_PFC_PIN_GROUP(vin1_sync),
4324		SH_PFC_PIN_GROUP(vin1_sync_b),
4325		SH_PFC_PIN_GROUP(vin1_field),
4326		SH_PFC_PIN_GROUP(vin1_field_b),
4327		SH_PFC_PIN_GROUP(vin1_clkenb),
4328		SH_PFC_PIN_GROUP(vin1_clkenb_b),
4329		SH_PFC_PIN_GROUP(vin1_clk),
4330		SH_PFC_PIN_GROUP(vin1_clk_b),
4331		BUS_DATA_PIN_GROUP(vin2_data, 24),
4332		SH_PFC_PIN_GROUP(vin2_data18),
4333		BUS_DATA_PIN_GROUP(vin2_data, 16),
4334		BUS_DATA_PIN_GROUP(vin2_data, 8),
4335		BUS_DATA_PIN_GROUP(vin2_data, 4),
4336		SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8),
4337		SH_PFC_PIN_GROUP(vin2_sync),
4338		SH_PFC_PIN_GROUP(vin2_field),
4339		SH_PFC_PIN_GROUP(vin2_clkenb),
4340		SH_PFC_PIN_GROUP(vin2_clk),
4341		SH_PFC_PIN_GROUP(vin3_data8),
4342		SH_PFC_PIN_GROUP(vin3_sync),
4343		SH_PFC_PIN_GROUP(vin3_field),
4344		SH_PFC_PIN_GROUP(vin3_clkenb),
4345		SH_PFC_PIN_GROUP(vin3_clk),
4346	},
4347#ifdef CONFIG_PINCTRL_PFC_R8A7790
4348	.automotive = {
4349		SH_PFC_PIN_GROUP(mlb_3pin),
4350	}
4351#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4352};
4353
4354static const char * const audio_clk_groups[] = {
4355	"audio_clk_a",
4356	"audio_clk_b",
4357	"audio_clk_c",
4358	"audio_clkout",
4359	"audio_clkout_b",
4360	"audio_clkout_c",
4361	"audio_clkout_d",
4362};
4363
4364static const char * const avb_groups[] = {
4365	"avb_link",
4366	"avb_magic",
4367	"avb_phy_int",
4368	"avb_mdio",
4369	"avb_mii",
4370	"avb_gmii",
4371};
4372
4373static const char * const can0_groups[] = {
4374	"can0_data",
4375	"can0_data_b",
4376	"can0_data_c",
4377	"can0_data_d",
4378};
4379
4380static const char * const can1_groups[] = {
4381	"can1_data",
4382	"can1_data_b",
4383};
4384
4385static const char * const can_clk_groups[] = {
4386	"can_clk",
4387	"can_clk_b",
4388};
4389
4390static const char * const du_groups[] = {
4391	"du_rgb666",
4392	"du_rgb888",
4393	"du_clk_out_0",
4394	"du_clk_out_1",
4395	"du_sync_0",
4396	"du_sync_1",
4397	"du_cde",
4398};
4399
4400static const char * const du0_groups[] = {
4401	"du0_clk_in",
4402};
4403
4404static const char * const du1_groups[] = {
4405	"du1_clk_in",
4406};
4407
4408static const char * const du2_groups[] = {
4409	"du2_clk_in",
4410};
4411
4412static const char * const eth_groups[] = {
4413	"eth_link",
4414	"eth_magic",
4415	"eth_mdio",
4416	"eth_rmii",
4417};
4418
4419static const char * const hscif0_groups[] = {
4420	"hscif0_data",
4421	"hscif0_clk",
4422	"hscif0_ctrl",
4423	"hscif0_data_b",
4424	"hscif0_ctrl_b",
4425	"hscif0_data_c",
4426	"hscif0_ctrl_c",
4427	"hscif0_data_d",
4428	"hscif0_ctrl_d",
4429	"hscif0_data_e",
4430	"hscif0_ctrl_e",
4431	"hscif0_data_f",
4432	"hscif0_ctrl_f",
4433};
4434
4435static const char * const hscif1_groups[] = {
4436	"hscif1_data",
4437	"hscif1_clk",
4438	"hscif1_ctrl",
4439	"hscif1_data_b",
4440	"hscif1_clk_b",
4441	"hscif1_ctrl_b",
4442};
4443
4444static const char * const i2c0_groups[] = {
4445	"i2c0",
4446};
4447
4448static const char * const i2c1_groups[] = {
4449	"i2c1",
4450	"i2c1_b",
4451	"i2c1_c",
4452};
4453
4454static const char * const i2c2_groups[] = {
4455	"i2c2",
4456	"i2c2_b",
4457	"i2c2_c",
4458	"i2c2_d",
4459	"i2c2_e",
4460};
4461
4462static const char * const i2c3_groups[] = {
4463	"i2c3",
4464};
4465
4466static const char * const iic0_groups[] = {
4467	"iic0",
4468};
4469
4470static const char * const iic1_groups[] = {
4471	"iic1",
4472	"iic1_b",
4473	"iic1_c",
4474};
4475
4476static const char * const iic2_groups[] = {
4477	"iic2",
4478	"iic2_b",
4479	"iic2_c",
4480	"iic2_d",
4481	"iic2_e",
4482};
4483
4484static const char * const iic3_groups[] = {
4485	"iic3",
4486};
4487
4488static const char * const intc_groups[] = {
4489	"intc_irq0",
4490	"intc_irq1",
4491	"intc_irq2",
4492	"intc_irq3",
4493};
4494
4495#ifdef CONFIG_PINCTRL_PFC_R8A7790
4496static const char * const mlb_groups[] = {
4497	"mlb_3pin",
4498};
4499#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4500
4501static const char * const mmc0_groups[] = {
4502	"mmc0_data1",
4503	"mmc0_data4",
4504	"mmc0_data8",
4505	"mmc0_ctrl",
4506};
4507
4508static const char * const mmc1_groups[] = {
4509	"mmc1_data1",
4510	"mmc1_data4",
4511	"mmc1_data8",
4512	"mmc1_ctrl",
4513};
4514
4515static const char * const msiof0_groups[] = {
4516	"msiof0_clk",
4517	"msiof0_sync",
4518	"msiof0_ss1",
4519	"msiof0_ss2",
4520	"msiof0_rx",
4521	"msiof0_tx",
4522	"msiof0_clk_b",
4523	"msiof0_ss1_b",
4524	"msiof0_ss2_b",
4525	"msiof0_rx_b",
4526	"msiof0_tx_b",
4527};
4528
4529static const char * const msiof1_groups[] = {
4530	"msiof1_clk",
4531	"msiof1_sync",
4532	"msiof1_ss1",
4533	"msiof1_ss2",
4534	"msiof1_rx",
4535	"msiof1_tx",
4536	"msiof1_clk_b",
4537	"msiof1_ss1_b",
4538	"msiof1_ss2_b",
4539	"msiof1_rx_b",
4540	"msiof1_tx_b",
4541};
4542
4543static const char * const msiof2_groups[] = {
4544	"msiof2_clk",
4545	"msiof2_sync",
4546	"msiof2_ss1",
4547	"msiof2_ss2",
4548	"msiof2_rx",
4549	"msiof2_tx",
4550};
4551
4552static const char * const msiof3_groups[] = {
4553	"msiof3_clk",
4554	"msiof3_sync",
4555	"msiof3_ss1",
4556	"msiof3_ss2",
4557	"msiof3_rx",
4558	"msiof3_tx",
4559	"msiof3_clk_b",
4560	"msiof3_sync_b",
4561	"msiof3_rx_b",
4562	"msiof3_tx_b",
4563};
4564
4565static const char * const pwm0_groups[] = {
4566	"pwm0",
4567	"pwm0_b",
4568};
4569
4570static const char * const pwm1_groups[] = {
4571	"pwm1",
4572	"pwm1_b",
4573};
4574
4575static const char * const pwm2_groups[] = {
4576	"pwm2",
4577};
4578
4579static const char * const pwm3_groups[] = {
4580	"pwm3",
4581};
4582
4583static const char * const pwm4_groups[] = {
4584	"pwm4",
4585};
4586
4587static const char * const pwm5_groups[] = {
4588	"pwm5",
4589};
4590
4591static const char * const pwm6_groups[] = {
4592	"pwm6",
4593};
4594
4595static const char * const qspi_groups[] = {
4596	"qspi_ctrl",
4597	"qspi_data2",
4598	"qspi_data4",
4599};
4600
4601static const char * const scif0_groups[] = {
4602	"scif0_data",
4603	"scif0_clk",
4604	"scif0_ctrl",
4605	"scif0_data_b",
4606};
4607
4608static const char * const scif1_groups[] = {
4609	"scif1_data",
4610	"scif1_clk",
4611	"scif1_ctrl",
4612	"scif1_data_b",
4613	"scif1_data_c",
4614	"scif1_data_d",
4615	"scif1_clk_d",
4616	"scif1_data_e",
4617	"scif1_clk_e",
4618};
4619
4620static const char * const scif2_groups[] = {
4621	"scif2_data",
4622	"scif2_clk",
4623	"scif2_data_b",
4624};
4625
4626static const char * const scifa0_groups[] = {
4627	"scifa0_data",
4628	"scifa0_clk",
4629	"scifa0_ctrl",
4630	"scifa0_data_b",
4631	"scifa0_clk_b",
4632	"scifa0_ctrl_b",
4633};
4634
4635static const char * const scifa1_groups[] = {
4636	"scifa1_data",
4637	"scifa1_clk",
4638	"scifa1_ctrl",
4639	"scifa1_data_b",
4640	"scifa1_clk_b",
4641	"scifa1_ctrl_b",
4642	"scifa1_data_c",
4643	"scifa1_clk_c",
4644	"scifa1_ctrl_c",
4645	"scifa1_data_d",
4646	"scifa1_clk_d",
4647	"scifa1_ctrl_d",
4648};
4649
4650static const char * const scifa2_groups[] = {
4651	"scifa2_data",
4652	"scifa2_clk",
4653	"scifa2_ctrl",
4654	"scifa2_data_b",
4655	"scifa2_data_c",
4656	"scifa2_clk_c",
4657};
4658
4659static const char * const scifb0_groups[] = {
4660	"scifb0_data",
4661	"scifb0_clk",
4662	"scifb0_ctrl",
4663	"scifb0_data_b",
4664	"scifb0_clk_b",
4665	"scifb0_ctrl_b",
4666	"scifb0_data_c",
4667};
4668
4669static const char * const scifb1_groups[] = {
4670	"scifb1_data",
4671	"scifb1_clk",
4672	"scifb1_ctrl",
4673	"scifb1_data_b",
4674	"scifb1_clk_b",
4675	"scifb1_ctrl_b",
4676	"scifb1_data_c",
4677	"scifb1_data_d",
4678	"scifb1_data_e",
4679	"scifb1_clk_e",
4680	"scifb1_data_f",
4681	"scifb1_data_g",
4682	"scifb1_clk_g",
4683};
4684
4685static const char * const scifb2_groups[] = {
4686	"scifb2_data",
4687	"scifb2_clk",
4688	"scifb2_ctrl",
4689	"scifb2_data_b",
4690	"scifb2_clk_b",
4691	"scifb2_ctrl_b",
4692	"scifb2_data_c",
4693};
4694
4695static const char * const scif_clk_groups[] = {
4696	"scif_clk",
4697	"scif_clk_b",
4698};
4699
4700static const char * const sdhi0_groups[] = {
4701	"sdhi0_data1",
4702	"sdhi0_data4",
4703	"sdhi0_ctrl",
4704	"sdhi0_cd",
4705	"sdhi0_wp",
4706};
4707
4708static const char * const sdhi1_groups[] = {
4709	"sdhi1_data1",
4710	"sdhi1_data4",
4711	"sdhi1_ctrl",
4712	"sdhi1_cd",
4713	"sdhi1_wp",
4714};
4715
4716static const char * const sdhi2_groups[] = {
4717	"sdhi2_data1",
4718	"sdhi2_data4",
4719	"sdhi2_ctrl",
4720	"sdhi2_cd",
4721	"sdhi2_wp",
4722};
4723
4724static const char * const sdhi3_groups[] = {
4725	"sdhi3_data1",
4726	"sdhi3_data4",
4727	"sdhi3_ctrl",
4728	"sdhi3_cd",
4729	"sdhi3_wp",
4730};
4731
4732static const char * const ssi_groups[] = {
4733	"ssi0_data",
4734	"ssi0129_ctrl",
4735	"ssi1_data",
4736	"ssi1_ctrl",
4737	"ssi2_data",
4738	"ssi2_ctrl",
4739	"ssi3_data",
4740	"ssi34_ctrl",
4741	"ssi4_data",
4742	"ssi4_ctrl",
4743	"ssi5",
4744	"ssi5_b",
4745	"ssi5_c",
4746	"ssi6",
4747	"ssi6_b",
4748	"ssi7_data",
4749	"ssi7_b_data",
4750	"ssi7_c_data",
4751	"ssi78_ctrl",
4752	"ssi78_b_ctrl",
4753	"ssi78_c_ctrl",
4754	"ssi8_data",
4755	"ssi8_b_data",
4756	"ssi8_c_data",
4757	"ssi9_data",
4758	"ssi9_ctrl",
4759};
4760
4761static const char * const tpu0_groups[] = {
4762	"tpu0_to0",
4763	"tpu0_to1",
4764	"tpu0_to2",
4765	"tpu0_to3",
4766};
4767
4768static const char * const usb0_groups[] = {
4769	"usb0",
4770	"usb0_ovc_vbus",
4771};
4772
4773static const char * const usb1_groups[] = {
4774	"usb1",
4775	"usb1_pwen",
4776};
4777
4778static const char * const usb2_groups[] = {
4779	"usb2",
4780};
4781
4782static const char * const vin0_groups[] = {
4783	"vin0_data24",
4784	"vin0_data20",
4785	"vin0_data18",
4786	"vin0_data16",
4787	"vin0_data12",
4788	"vin0_data10",
4789	"vin0_data8",
4790	"vin0_data4",
4791	"vin0_sync",
4792	"vin0_field",
4793	"vin0_clkenb",
4794	"vin0_clk",
4795};
4796
4797static const char * const vin1_groups[] = {
4798	"vin1_data24",
4799	"vin1_data20",
4800	"vin1_data18",
4801	"vin1_data16",
4802	"vin1_data12",
4803	"vin1_data10",
4804	"vin1_data8",
4805	"vin1_data4",
4806	"vin1_data24_b",
4807	"vin1_data20_b",
4808	"vin1_data18_b",
4809	"vin1_data16_b",
4810	"vin1_data12_b",
4811	"vin1_data10_b",
4812	"vin1_data8_b",
4813	"vin1_data4_b",
4814	"vin1_sync",
4815	"vin1_sync_b",
4816	"vin1_field",
4817	"vin1_field_b",
4818	"vin1_clkenb",
4819	"vin1_clkenb_b",
4820	"vin1_clk",
4821	"vin1_clk_b",
4822};
4823
4824static const char * const vin2_groups[] = {
4825	"vin2_data24",
4826	"vin2_data18",
4827	"vin2_data16",
4828	"vin2_data8",
4829	"vin2_data4",
4830	"vin2_g8",
4831	"vin2_sync",
4832	"vin2_field",
4833	"vin2_clkenb",
4834	"vin2_clk",
4835};
4836
4837static const char * const vin3_groups[] = {
4838	"vin3_data8",
4839	"vin3_sync",
4840	"vin3_field",
4841	"vin3_clkenb",
4842	"vin3_clk",
4843};
4844
4845static const struct {
4846	struct sh_pfc_function common[58];
4847#ifdef CONFIG_PINCTRL_PFC_R8A7790
4848	struct sh_pfc_function automotive[1];
4849#endif
4850} pinmux_functions = {
4851	.common = {
4852		SH_PFC_FUNCTION(audio_clk),
4853		SH_PFC_FUNCTION(avb),
4854		SH_PFC_FUNCTION(can0),
4855		SH_PFC_FUNCTION(can1),
4856		SH_PFC_FUNCTION(can_clk),
4857		SH_PFC_FUNCTION(du),
4858		SH_PFC_FUNCTION(du0),
4859		SH_PFC_FUNCTION(du1),
4860		SH_PFC_FUNCTION(du2),
4861		SH_PFC_FUNCTION(eth),
4862		SH_PFC_FUNCTION(hscif0),
4863		SH_PFC_FUNCTION(hscif1),
4864		SH_PFC_FUNCTION(i2c0),
4865		SH_PFC_FUNCTION(i2c1),
4866		SH_PFC_FUNCTION(i2c2),
4867		SH_PFC_FUNCTION(i2c3),
4868		SH_PFC_FUNCTION(iic0),
4869		SH_PFC_FUNCTION(iic1),
4870		SH_PFC_FUNCTION(iic2),
4871		SH_PFC_FUNCTION(iic3),
4872		SH_PFC_FUNCTION(intc),
4873		SH_PFC_FUNCTION(mmc0),
4874		SH_PFC_FUNCTION(mmc1),
4875		SH_PFC_FUNCTION(msiof0),
4876		SH_PFC_FUNCTION(msiof1),
4877		SH_PFC_FUNCTION(msiof2),
4878		SH_PFC_FUNCTION(msiof3),
4879		SH_PFC_FUNCTION(pwm0),
4880		SH_PFC_FUNCTION(pwm1),
4881		SH_PFC_FUNCTION(pwm2),
4882		SH_PFC_FUNCTION(pwm3),
4883		SH_PFC_FUNCTION(pwm4),
4884		SH_PFC_FUNCTION(pwm5),
4885		SH_PFC_FUNCTION(pwm6),
4886		SH_PFC_FUNCTION(qspi),
4887		SH_PFC_FUNCTION(scif0),
4888		SH_PFC_FUNCTION(scif1),
4889		SH_PFC_FUNCTION(scif2),
4890		SH_PFC_FUNCTION(scifa0),
4891		SH_PFC_FUNCTION(scifa1),
4892		SH_PFC_FUNCTION(scifa2),
4893		SH_PFC_FUNCTION(scifb0),
4894		SH_PFC_FUNCTION(scifb1),
4895		SH_PFC_FUNCTION(scifb2),
4896		SH_PFC_FUNCTION(scif_clk),
4897		SH_PFC_FUNCTION(sdhi0),
4898		SH_PFC_FUNCTION(sdhi1),
4899		SH_PFC_FUNCTION(sdhi2),
4900		SH_PFC_FUNCTION(sdhi3),
4901		SH_PFC_FUNCTION(ssi),
4902		SH_PFC_FUNCTION(tpu0),
4903		SH_PFC_FUNCTION(usb0),
4904		SH_PFC_FUNCTION(usb1),
4905		SH_PFC_FUNCTION(usb2),
4906		SH_PFC_FUNCTION(vin0),
4907		SH_PFC_FUNCTION(vin1),
4908		SH_PFC_FUNCTION(vin2),
4909		SH_PFC_FUNCTION(vin3),
4910	},
4911#ifdef CONFIG_PINCTRL_PFC_R8A7790
4912	.automotive = {
4913		SH_PFC_FUNCTION(mlb),
4914	}
4915#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4916};
4917
4918static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4919	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4920		GP_0_31_FN, FN_IP3_17_15,
4921		GP_0_30_FN, FN_IP3_14_12,
4922		GP_0_29_FN, FN_IP3_11_8,
4923		GP_0_28_FN, FN_IP3_7_4,
4924		GP_0_27_FN, FN_IP3_3_0,
4925		GP_0_26_FN, FN_IP2_28_26,
4926		GP_0_25_FN, FN_IP2_25_22,
4927		GP_0_24_FN, FN_IP2_21_18,
4928		GP_0_23_FN, FN_IP2_17_15,
4929		GP_0_22_FN, FN_IP2_14_12,
4930		GP_0_21_FN, FN_IP2_11_9,
4931		GP_0_20_FN, FN_IP2_8_6,
4932		GP_0_19_FN, FN_IP2_5_3,
4933		GP_0_18_FN, FN_IP2_2_0,
4934		GP_0_17_FN, FN_IP1_29_28,
4935		GP_0_16_FN, FN_IP1_27_26,
4936		GP_0_15_FN, FN_IP1_25_22,
4937		GP_0_14_FN, FN_IP1_21_18,
4938		GP_0_13_FN, FN_IP1_17_15,
4939		GP_0_12_FN, FN_IP1_14_12,
4940		GP_0_11_FN, FN_IP1_11_8,
4941		GP_0_10_FN, FN_IP1_7_4,
4942		GP_0_9_FN, FN_IP1_3_0,
4943		GP_0_8_FN, FN_IP0_30_27,
4944		GP_0_7_FN, FN_IP0_26_23,
4945		GP_0_6_FN, FN_IP0_22_20,
4946		GP_0_5_FN, FN_IP0_19_16,
4947		GP_0_4_FN, FN_IP0_15_12,
4948		GP_0_3_FN, FN_IP0_11_9,
4949		GP_0_2_FN, FN_IP0_8_6,
4950		GP_0_1_FN, FN_IP0_5_3,
4951		GP_0_0_FN, FN_IP0_2_0 ))
4952	},
4953	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4954		0, 0,
4955		0, 0,
4956		GP_1_29_FN, FN_IP6_13_11,
4957		GP_1_28_FN, FN_IP6_10_9,
4958		GP_1_27_FN, FN_IP6_8_6,
4959		GP_1_26_FN, FN_IP6_5_3,
4960		GP_1_25_FN, FN_IP6_2_0,
4961		GP_1_24_FN, FN_IP5_29_27,
4962		GP_1_23_FN, FN_IP5_26_24,
4963		GP_1_22_FN, FN_IP5_23_21,
4964		GP_1_21_FN, FN_IP5_20_18,
4965		GP_1_20_FN, FN_IP5_17_15,
4966		GP_1_19_FN, FN_IP5_14_13,
4967		GP_1_18_FN, FN_IP5_12_10,
4968		GP_1_17_FN, FN_IP5_9_6,
4969		GP_1_16_FN, FN_IP5_5_3,
4970		GP_1_15_FN, FN_IP5_2_0,
4971		GP_1_14_FN, FN_IP4_29_27,
4972		GP_1_13_FN, FN_IP4_26_24,
4973		GP_1_12_FN, FN_IP4_23_21,
4974		GP_1_11_FN, FN_IP4_20_18,
4975		GP_1_10_FN, FN_IP4_17_15,
4976		GP_1_9_FN, FN_IP4_14_12,
4977		GP_1_8_FN, FN_IP4_11_9,
4978		GP_1_7_FN, FN_IP4_8_6,
4979		GP_1_6_FN, FN_IP4_5_3,
4980		GP_1_5_FN, FN_IP4_2_0,
4981		GP_1_4_FN, FN_IP3_31_29,
4982		GP_1_3_FN, FN_IP3_28_26,
4983		GP_1_2_FN, FN_IP3_25_23,
4984		GP_1_1_FN, FN_IP3_22_20,
4985		GP_1_0_FN, FN_IP3_19_18, ))
4986	},
4987	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4988		0, 0,
4989		0, 0,
4990		GP_2_29_FN, FN_IP7_15_13,
4991		GP_2_28_FN, FN_IP7_12_10,
4992		GP_2_27_FN, FN_IP7_9_8,
4993		GP_2_26_FN, FN_IP7_7_6,
4994		GP_2_25_FN, FN_IP7_5_3,
4995		GP_2_24_FN, FN_IP7_2_0,
4996		GP_2_23_FN, FN_IP6_31_29,
4997		GP_2_22_FN, FN_IP6_28_26,
4998		GP_2_21_FN, FN_IP6_25_23,
4999		GP_2_20_FN, FN_IP6_22_20,
5000		GP_2_19_FN, FN_IP6_19_17,
5001		GP_2_18_FN, FN_IP6_16_14,
5002		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
5003		GP_2_16_FN, FN_IP8_27,
5004		GP_2_15_FN, FN_IP8_26,
5005		GP_2_14_FN, FN_IP8_25_24,
5006		GP_2_13_FN, FN_IP8_23_22,
5007		GP_2_12_FN, FN_IP8_21_20,
5008		GP_2_11_FN, FN_IP8_19_18,
5009		GP_2_10_FN, FN_IP8_17_16,
5010		GP_2_9_FN, FN_IP8_15_14,
5011		GP_2_8_FN, FN_IP8_13_12,
5012		GP_2_7_FN, FN_IP8_11_10,
5013		GP_2_6_FN, FN_IP8_9_8,
5014		GP_2_5_FN, FN_IP8_7_6,
5015		GP_2_4_FN, FN_IP8_5_4,
5016		GP_2_3_FN, FN_IP8_3_2,
5017		GP_2_2_FN, FN_IP8_1_0,
5018		GP_2_1_FN, FN_IP7_30_29,
5019		GP_2_0_FN, FN_IP7_28_27 ))
5020	},
5021	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5022		GP_3_31_FN, FN_IP11_21_18,
5023		GP_3_30_FN, FN_IP11_17_15,
5024		GP_3_29_FN, FN_IP11_14_13,
5025		GP_3_28_FN, FN_IP11_12_11,
5026		GP_3_27_FN, FN_IP11_10_9,
5027		GP_3_26_FN, FN_IP11_8_7,
5028		GP_3_25_FN, FN_IP11_6_5,
5029		GP_3_24_FN, FN_IP11_4,
5030		GP_3_23_FN, FN_IP11_3_0,
5031		GP_3_22_FN, FN_IP10_29_26,
5032		GP_3_21_FN, FN_IP10_25_23,
5033		GP_3_20_FN, FN_IP10_22_19,
5034		GP_3_19_FN, FN_IP10_18_15,
5035		GP_3_18_FN, FN_IP10_14_11,
5036		GP_3_17_FN, FN_IP10_10_7,
5037		GP_3_16_FN, FN_IP10_6_4,
5038		GP_3_15_FN, FN_IP10_3_0,
5039		GP_3_14_FN, FN_IP9_31_28,
5040		GP_3_13_FN, FN_IP9_27_26,
5041		GP_3_12_FN, FN_IP9_25_24,
5042		GP_3_11_FN, FN_IP9_23_22,
5043		GP_3_10_FN, FN_IP9_21_20,
5044		GP_3_9_FN, FN_IP9_19_18,
5045		GP_3_8_FN, FN_IP9_17_16,
5046		GP_3_7_FN, FN_IP9_15_12,
5047		GP_3_6_FN, FN_IP9_11_8,
5048		GP_3_5_FN, FN_IP9_7_6,
5049		GP_3_4_FN, FN_IP9_5_4,
5050		GP_3_3_FN, FN_IP9_3_2,
5051		GP_3_2_FN, FN_IP9_1_0,
5052		GP_3_1_FN, FN_IP8_30_29,
5053		GP_3_0_FN, FN_IP8_28 ))
5054	},
5055	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5056		GP_4_31_FN, FN_IP14_18_16,
5057		GP_4_30_FN, FN_IP14_15_12,
5058		GP_4_29_FN, FN_IP14_11_9,
5059		GP_4_28_FN, FN_IP14_8_6,
5060		GP_4_27_FN, FN_IP14_5_3,
5061		GP_4_26_FN, FN_IP14_2_0,
5062		GP_4_25_FN, FN_IP13_30_29,
5063		GP_4_24_FN, FN_IP13_28_26,
5064		GP_4_23_FN, FN_IP13_25_23,
5065		GP_4_22_FN, FN_IP13_22_19,
5066		GP_4_21_FN, FN_IP13_18_16,
5067		GP_4_20_FN, FN_IP13_15_13,
5068		GP_4_19_FN, FN_IP13_12_10,
5069		GP_4_18_FN, FN_IP13_9_7,
5070		GP_4_17_FN, FN_IP13_6_3,
5071		GP_4_16_FN, FN_IP13_2_0,
5072		GP_4_15_FN, FN_IP12_30_28,
5073		GP_4_14_FN, FN_IP12_27_25,
5074		GP_4_13_FN, FN_IP12_24_23,
5075		GP_4_12_FN, FN_IP12_22_20,
5076		GP_4_11_FN, FN_IP12_19_17,
5077		GP_4_10_FN, FN_IP12_16_14,
5078		GP_4_9_FN, FN_IP12_13_11,
5079		GP_4_8_FN, FN_IP12_10_8,
5080		GP_4_7_FN, FN_IP12_7_6,
5081		GP_4_6_FN, FN_IP12_5_4,
5082		GP_4_5_FN, FN_IP12_3_2,
5083		GP_4_4_FN, FN_IP12_1_0,
5084		GP_4_3_FN, FN_IP11_31_30,
5085		GP_4_2_FN, FN_IP11_29_27,
5086		GP_4_1_FN, FN_IP11_26_24,
5087		GP_4_0_FN, FN_IP11_23_22 ))
5088	},
5089	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5090		GP_5_31_FN, FN_IP7_24_22,
5091		GP_5_30_FN, FN_IP7_21_19,
5092		GP_5_29_FN, FN_IP7_18_16,
5093		GP_5_28_FN, FN_DU_DOTCLKIN2,
5094		GP_5_27_FN, FN_IP7_26_25,
5095		GP_5_26_FN, FN_DU_DOTCLKIN0,
5096		GP_5_25_FN, FN_AVS2,
5097		GP_5_24_FN, FN_AVS1,
5098		GP_5_23_FN, FN_USB2_OVC,
5099		GP_5_22_FN, FN_USB2_PWEN,
5100		GP_5_21_FN, FN_IP16_7,
5101		GP_5_20_FN, FN_IP16_6,
5102		GP_5_19_FN, FN_USB0_OVC_VBUS,
5103		GP_5_18_FN, FN_USB0_PWEN,
5104		GP_5_17_FN, FN_IP16_5_3,
5105		GP_5_16_FN, FN_IP16_2_0,
5106		GP_5_15_FN, FN_IP15_29_28,
5107		GP_5_14_FN, FN_IP15_27_26,
5108		GP_5_13_FN, FN_IP15_25_23,
5109		GP_5_12_FN, FN_IP15_22_20,
5110		GP_5_11_FN, FN_IP15_19_18,
5111		GP_5_10_FN, FN_IP15_17_16,
5112		GP_5_9_FN, FN_IP15_15_14,
5113		GP_5_8_FN, FN_IP15_13_12,
5114		GP_5_7_FN, FN_IP15_11_9,
5115		GP_5_6_FN, FN_IP15_8_6,
5116		GP_5_5_FN, FN_IP15_5_3,
5117		GP_5_4_FN, FN_IP15_2_0,
5118		GP_5_3_FN, FN_IP14_30_28,
5119		GP_5_2_FN, FN_IP14_27_25,
5120		GP_5_1_FN, FN_IP14_24_22,
5121		GP_5_0_FN, FN_IP14_21_19 ))
5122	},
5123	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5124			     GROUP(-1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
5125			     GROUP(
5126		/* IP0_31 [1] RESERVED */
5127		/* IP0_30_27 [4] */
5128		FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
5129		FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
5130		0, 0, 0, 0, 0, 0, 0, 0, 0,
5131		/* IP0_26_23 [4] */
5132		FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
5133		FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
5134		FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
5135		/* IP0_22_20 [3] */
5136		FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
5137		FN_I2C2_SCL_C, 0, 0,
5138		/* IP0_19_16 [4] */
5139		FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
5140		FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
5141		0, 0, 0, 0, 0, 0, 0, 0, 0,
5142		/* IP0_15_12 [4] */
5143		FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
5144		FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
5145		0, 0, 0, 0, 0, 0, 0, 0, 0,
5146		/* IP0_11_9 [3] */
5147		FN_D3, FN_MSIOF3_TXD_B,	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
5148		0, 0, 0,
5149		/* IP0_8_6 [3] */
5150		FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
5151		0, 0, 0,
5152		/* IP0_5_3 [3] */
5153		FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
5154		0, 0, 0,
5155		/* IP0_2_0 [3] */
5156		FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
5157		0, 0, 0, ))
5158	},
5159	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5160			     GROUP(-2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
5161			     GROUP(
5162		/* IP1_31_30 [2] RESERVED */
5163		/* IP1_29_28 [2] */
5164		FN_A1, FN_PWM4, 0, 0,
5165		/* IP1_27_26 [2] */
5166		FN_A0, FN_PWM3, 0, 0,
5167		/* IP1_25_22 [4] */
5168		FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5169		FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5170		0, 0, 0, 0, 0, 0, 0, 0, 0,
5171		/* IP1_21_18 [4] */
5172		FN_D14,	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5173		FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5174		0, 0, 0, 0, 0, 0, 0, 0, 0,
5175		/* IP1_17_15 [3] */
5176		FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5177		FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5178		0, 0, 0,
5179		/* IP1_14_12 [3] */
5180		FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5181		FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5182		0, 0,
5183		/* IP1_11_8 [4] */
5184		FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5185		FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5186		0, 0, 0, 0, 0, 0, 0, 0, 0,
5187		/* IP1_7_4 [4] */
5188		FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5189		FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5190		0, 0, 0, 0, 0, 0, 0, 0, 0,
5191		/* IP1_3_0 [4] */
5192		FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5193		FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5194		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
5195	},
5196	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5197			     GROUP(-3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
5198			     GROUP(
5199		/* IP2_31_29 [3] RESERVED */
5200		/* IP2_28_26 [3] */
5201		FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5202		FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5203		/* IP2_25_22 [4] */
5204		FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5205		FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5206		0, 0, 0, 0, 0, 0, 0, 0,
5207		/* IP2_21_18 [4] */
5208		FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5209		FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5210		0, 0, 0, 0, 0, 0, 0, 0,
5211		/* IP2_17_15 [3] */
5212		FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5213		0, 0, 0, 0,
5214		/* IP2_14_12 [3] */
5215		FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5216		/* IP2_11_9 [3] */
5217		FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5218		/* IP2_8_6 [3] */
5219		FN_A4, FN_MSIOF1_TXD_B,	FN_TPU0TO0, 0, 0, 0, 0, 0,
5220		/* IP2_5_3 [3] */
5221		FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5222		/* IP2_2_0 [3] */
5223		FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0,	))
5224	},
5225	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5226			     GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
5227			     GROUP(
5228		/* IP3_31_29 [3] */
5229		FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5230		0, 0, 0,
5231		/* IP3_28_26 [3] */
5232		FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5233		0, 0, 0, 0,
5234		/* IP3_25_23 [3] */
5235		FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5236		/* IP3_22_20 [3] */
5237		FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5238		/* IP3_19_18 [2] */
5239		FN_A16, FN_ATAWR1_N, 0, 0,
5240		/* IP3_17_15 [3] */
5241		FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5242		0, 0, 0, 0,
5243		/* IP3_14_12 [3] */
5244		FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5245		0, 0, 0, 0,
5246		/* IP3_11_8 [4] */
5247		FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5248		FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5249		FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5250		/* IP3_7_4 [4] */
5251		FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5252		FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5253		0, 0, 0, 0, 0, 0, 0, 0, 0,
5254		/* IP3_3_0 [4] */
5255		FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5256		FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5257		0, 0, 0, 0, 0, 0, 0, 0, ))
5258	},
5259	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5260			     GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5261			     GROUP(
5262		/* IP4_31_30 [2] RESERVED */
5263		/* IP4_29_27 [3] */
5264		FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5265		FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5266		/* IP4_26_24 [3] */
5267		FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5268		FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5269		/* IP4_23_21 [3] */
5270		FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5271		FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5272		/* IP4_20_18 [3] */
5273		FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5274		FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5275		/* IP4_17_15 [3] */
5276		FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5277		0, 0, 0,
5278		/* IP4_14_12 [3] */
5279		FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5280		FN_VI2_FIELD_B, 0, 0,
5281		/* IP4_11_9 [3] */
5282		FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5283		FN_VI2_CLKENB_B, 0, 0,
5284		/* IP4_8_6 [3] */
5285		FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5286		/* IP4_5_3 [3] */
5287		FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5288		/* IP4_2_0 [3] */
5289		FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5290		))
5291	},
5292	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5293			     GROUP(-2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
5294			     GROUP(
5295		/* IP5_31_30 [2] RESERVED */
5296		/* IP5_29_27 [3] */
5297		FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5298		FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5299		/* IP5_26_24 [3] */
5300		FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
5301		FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
5302		/* IP5_23_21 [3] */
5303		FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5304		FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5305		/* IP5_20_18 [3] */
5306		FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5307		FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5308		/* IP5_17_15 [3] */
5309		FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5310		0, 0, 0,
5311		/* IP5_14_13 [2] */
5312		FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5313		/* IP5_12_10 [3] */
5314		FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5315		0, 0,
5316		/* IP5_9_6 [4] */
5317		FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5318		FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5319		FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5320		/* IP5_5_3 [3] */
5321		FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5322		FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5323		FN_INTC_EN0_N, FN_I2C1_SCL,
5324		/* IP5_2_0 [3] */
5325		FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5326		FN_VI2_R3, 0, 0, ))
5327	},
5328	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5329			     GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
5330			     GROUP(
5331		/* IP6_31_29 [3] */
5332		FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5333		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5334		/* IP6_28_26 [3] */
5335		FN_ETH_LINK, 0, FN_HTX0_E,
5336		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5337		/* IP6_25_23 [3] */
5338		FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5339		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5340		/* IP6_22_20 [3] */
5341		FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5342		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5343		/* IP6_19_17 [3] */
5344		FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5345		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5346		/* IP6_16_14 [3] */
5347		FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5348		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5349		FN_I2C2_SCL_E, 0,
5350		/* IP6_13_11 [3] */
5351		FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
5352		FN_MSIOF0_RXD_B, 0, 0,
5353		/* IP6_10_9 [2] */
5354		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5355		/* IP6_8_6 [3] */
5356		FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
5357		/* IP6_5_3 [3] */
5358		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5359		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5360		/* IP6_2_0 [3] */
5361		FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
5362		FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5363	},
5364	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5365			     GROUP(-1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
5366			     GROUP(
5367		/* IP7_31 [1] RESERVED */
5368		/* IP7_30_29 [2] */
5369		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5370		/* IP7_28_27 [2] */
5371		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5372		/* IP7_26_25 [2] */
5373		FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5374		/* IP7_24_22 [3] */
5375		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5376		0, 0, 0,
5377		/* IP7_21_19 [3] */
5378		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5379		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5380		/* IP7_18_16 [3] */
5381		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5382		FN_GLO_SS_C, 0, 0, 0,
5383		/* IP7_15_13 [3] */
5384		FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5385		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5386		/* IP7_12_10 [3] */
5387		FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5388		FN_GLO_SCLK_C, 0, 0, 0,
5389		/* IP7_9_8 [2] */
5390		FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5391		/* IP7_7_6 [2] */
5392		FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5393		/* IP7_5_3 [3] */
5394		FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5395		/* IP7_2_0 [3] */
5396		FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5397		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
5398	},
5399	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5400			     GROUP(-1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
5401				   2, 2, 2, 2, 2, 2),
5402			     GROUP(
5403		/* IP8_31 [1] RESERVED */
5404		/* IP8_30_29 [2] */
5405		FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5406		/* IP8_28 [1] */
5407		FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5408		/* IP8_27 [1] */
5409		FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5410		/* IP8_26 [1] */
5411		FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5412		/* IP8_25_24 [2] */
5413		FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5414		FN_AVB_MAGIC, 0,
5415		/* IP8_23_22 [2] */
5416		FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5417		/* IP8_21_20 [2] */
5418		FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5419		/* IP8_19_18 [2] */
5420		FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5421		/* IP8_17_16 [2] */
5422		FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5423		/* IP8_15_14 [2] */
5424		FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5425		/* IP8_13_12 [2] */
5426		FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5427		/* IP8_11_10 [2] */
5428		FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5429		/* IP8_9_8 [2] */
5430		FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5431		/* IP8_7_6 [2] */
5432		FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5433		/* IP8_5_4 [2] */
5434		FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5435		/* IP8_3_2 [2] */
5436		FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5437		/* IP8_1_0 [2] */
5438		FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
5439	},
5440	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5441			     GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
5442			     GROUP(
5443		/* IP9_31_28 [4] */
5444		FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5445		FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5446		FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5447		/* IP9_27_26 [2] */
5448		FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5449		/* IP9_25_24 [2] */
5450		FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5451		/* IP9_23_22 [2] */
5452		FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5453		/* IP9_21_20 [2] */
5454		FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5455		/* IP9_19_18 [2] */
5456		FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5457		/* IP9_17_16 [2] */
5458		FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5459		/* IP9_15_12 [4] */
5460		FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5461		FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5462		FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5463		/* IP9_11_8 [4] */
5464		FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5465		FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5466		FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5467		/* IP9_7_6 [2] */
5468		FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5469		/* IP9_5_4 [2] */
5470		FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5471		/* IP9_3_2 [2] */
5472		FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5473		/* IP9_1_0 [2] */
5474		FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
5475	},
5476	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5477			     GROUP(-2, 4, 3, 4, 4, 4, 4, 3, 4),
5478			     GROUP(
5479		/* IP10_31_30 [2] RESERVED */
5480		/* IP10_29_26 [4] */
5481		FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5482		FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5483		FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5484		/* IP10_25_23 [3] */
5485		FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5486		FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5487		/* IP10_22_19 [4] */
5488		FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5489		FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5490		FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5491		/* IP10_18_15 [4] */
5492		FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5493		FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5494		FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5495		0, 0, 0, 0, 0, 0,
5496		/* IP10_14_11 [4] */
5497		FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5498		FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5499		FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5500		0, 0, 0, 0, 0, 0, 0,
5501		/* IP10_10_7 [4] */
5502		FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5503		FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5504		FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5505		0, 0, 0, 0, 0, 0, 0,
5506		/* IP10_6_4 [3] */
5507		FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5508		FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5509		FN_VI3_DATA0_B, 0,
5510		/* IP10_3_0 [4] */
5511		FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5512		FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5513		FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
5514	},
5515	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5516			     GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
5517			     GROUP(
5518		/* IP11_31_30 [2] */
5519		FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5520		/* IP11_29_27 [3] */
5521		FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5522		0, 0, 0,
5523		/* IP11_26_24 [3] */
5524		FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5525		0, 0, 0,
5526		/* IP11_23_22 [2] */
5527		FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5528		/* IP11_21_18 [4] */
5529		FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5530		0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5531		/* IP11_17_15 [3] */
5532		FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5533		FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5534		/* IP11_14_13 [2] */
5535		FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5536		/* IP11_12_11 [2] */
5537		FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5538		/* IP11_10_9 [2] */
5539		FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5540		/* IP11_8_7 [2] */
5541		FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5542		/* IP11_6_5 [2] */
5543		FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5544		/* IP11_4 [1] */
5545		FN_SD3_CLK, FN_MMC1_CLK,
5546		/* IP11_3_0 [4] */
5547		FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5548		FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5549		FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
5550	},
5551	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5552			     GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5553			     GROUP(
5554		/* IP12_31 [1] RESERVED */
5555		/* IP12_30_28 [3] */
5556		FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5557		FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5558		FN_CAN_DEBUGOUT4, 0, 0,
5559		/* IP12_27_25 [3] */
5560		FN_SSI_SCK5, FN_SCIFB1_SCK,
5561		FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5562		FN_CAN_DEBUGOUT3, 0, 0,
5563		/* IP12_24_23 [2] */
5564		FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5565		FN_CAN_DEBUGOUT2,
5566		/* IP12_22_20 [3] */
5567		FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5568		FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5569		/* IP12_19_17 [3] */
5570		FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5571		FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5572		/* IP12_16_14 [3] */
5573		FN_SSI_SDATA3, FN_STP_ISCLK_0,
5574		FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5575		/* IP12_13_11 [3] */
5576		FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5577		FN_CAN_STEP0, 0, 0, 0,
5578		/* IP12_10_8 [3] */
5579		FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5580		FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5581		/* IP12_7_6 [2] */
5582		FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5583		/* IP12_5_4 [2] */
5584		FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5585		/* IP12_3_2 [2] */
5586		FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5587		/* IP12_1_0 [2] */
5588		FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
5589	},
5590	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5591			     GROUP(-1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
5592			     GROUP(
5593		/* IP13_31 [1] RESERVED */
5594		/* IP13_30_29 [2] */
5595		FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5596		/* IP13_28_26 [3] */
5597		FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5598		FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5599		/* IP13_25_23 [3] */
5600		FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5601		FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5602		/* IP13_22_19 [4] */
5603		FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5604		FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5605		0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5606		/* IP13_18_16 [3] */
5607		FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5608		FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5609		/* IP13_15_13 [3] */
5610		FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5611		FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5612		/* IP13_12_10 [3] */
5613		FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5614		FN_CAN_DEBUGOUT8, 0, 0,
5615		/* IP13_9_7 [3] */
5616		FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5617		FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5618		/* IP13_6_3 [4] */
5619		FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5620		FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5621		FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5622		/* IP13_2_0 [3] */
5623		FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5624		FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
5625	},
5626	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5627			     GROUP(-1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
5628			     GROUP(
5629		/* IP14_30 [1] RESERVED */
5630		/* IP14_30_28 [3] */
5631		FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5632		FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5633		FN_HRTS0_N_C, 0,
5634		/* IP14_27_25 [3] */
5635		FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5636		FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5637		/* IP14_24_22 [3] */
5638		FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5639		FN_LCDOUT9, 0, 0, 0,
5640		/* IP14_21_19 [3] */
5641		FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5642		FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5643		/* IP14_18_16 [3] */
5644		FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5645		FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5646		/* IP14_15_12 [4] */
5647		FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5648		FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5649		0, 0, 0, 0, 0, 0, 0,
5650		/* IP14_11_9 [3] */
5651		FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5652		0, 0, 0,
5653		/* IP14_8_6 [3] */
5654		FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5655		0, 0, 0,
5656		/* IP14_5_3 [3] */
5657		FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5658		FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5659		/* IP14_2_0 [3] */
5660		FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5661		FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5662		FN_REMOCON, 0, ))
5663	},
5664	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5665			     GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
5666			     GROUP(
5667		/* IP15_31_30 [2] RESERVED */
5668		/* IP15_29_28 [2] */
5669		FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5670		/* IP15_27_26 [2] */
5671		FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5672		/* IP15_25_23 [3] */
5673		FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5674		FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5675		/* IP15_22_20 [3] */
5676		FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5677		FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5678		/* IP15_19_18 [2] */
5679		FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5680		/* IP15_17_16 [2] */
5681		FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5682		/* IP15_15_14 [2] */
5683		FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5684		/* IP15_13_12 [2] */
5685		FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5686		/* IP15_11_9 [3] */
5687		FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5688		0, 0, 0,
5689		/* IP15_8_6 [3] */
5690		FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5691		FN_IIC2_SDA, FN_I2C2_SDA, 0,
5692		/* IP15_5_3 [3] */
5693		FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5694		FN_IIC2_SCL, FN_I2C2_SCL, 0,
5695		/* IP15_2_0 [3] */
5696		FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5697		FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
5698	},
5699	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5700			     GROUP(-24, 1, 1, 3, 3),
5701			     GROUP(
5702		/* IP16_31_8 [24] RESERVED */
5703		/* IP16_7 [1] */
5704		FN_USB1_OVC, FN_TCLK1_B,
5705		/* IP16_6 [1] */
5706		FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5707		/* IP16_5_3 [3] */
5708		FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5709		FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5710		/* IP16_2_0 [3] */
5711		FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5712		FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
5713	},
5714	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5715			     GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
5716				   1, 1, 1, 2, -1, 1, 2, 1, 1),
5717			     GROUP(
5718		/* SEL_SCIF1 [3] */
5719		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5720		FN_SEL_SCIF1_4, 0, 0, 0,
5721		/* SEL_SCIFB [2] */
5722		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5723		/* SEL_SCIFB2 [2] */
5724		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5725		/* SEL_SCIFB1 [3] */
5726		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5727		FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5728		FN_SEL_SCIFB1_6, 0,
5729		/* SEL_SCIFA1 [2] */
5730		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5731		FN_SEL_SCIFA1_3,
5732		/* SEL_SCIF0 [1] */
5733		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5734		/* SEL_SCIFA [1] */
5735		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5736		/* SEL_SOF1 [1] */
5737		FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5738		/* SEL_SSI7 [2] */
5739		FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5740		/* SEL_SSI6 [1] */
5741		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5742		/* SEL_SSI5 [2] */
5743		FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5744		/* SEL_VI3 [1] */
5745		FN_SEL_VI3_0, FN_SEL_VI3_1,
5746		/* SEL_VI2 [1] */
5747		FN_SEL_VI2_0, FN_SEL_VI2_1,
5748		/* SEL_VI1 [1] */
5749		FN_SEL_VI1_0, FN_SEL_VI1_1,
5750		/* SEL_VI0 [1] */
5751		FN_SEL_VI0_0, FN_SEL_VI0_1,
5752		/* SEL_TSIF1 [2] */
5753		FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5754		/* RESERVED [1] */
5755		/* SEL_LBS [1] */
5756		FN_SEL_LBS_0, FN_SEL_LBS_1,
5757		/* SEL_TSIF0 [2] */
5758		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5759		/* SEL_SOF3 [1] */
5760		FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5761		/* SEL_SOF0 [1] */
5762		FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
5763	},
5764	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5765			     GROUP(-3, 1, 1, 1, 2, 1, 2, 1, -2, 1, 1, 1,
5766				   3, 3, 2, -3, 2, 2),
5767			     GROUP(
5768		/* RESERVED [3] */
5769		/* SEL_TMU1 [1] */
5770		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5771		/* SEL_HSCIF1 [1] */
5772		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5773		/* SEL_SCIFCLK [1] */
5774		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5775		/* SEL_CAN0 [2] */
5776		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5777		/* SEL_CANCLK [1] */
5778		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5779		/* SEL_SCIFA2 [2] */
5780		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5781		/* SEL_CAN1 [1] */
5782		FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5783		/* RESERVED [2] */
5784		/* SEL_SCIF2 [1] */
5785		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5786		/* SEL_ADI [1] */
5787		FN_SEL_ADI_0, FN_SEL_ADI_1,
5788		/* SEL_SSP [1] */
5789		FN_SEL_SSP_0, FN_SEL_SSP_1,
5790		/* SEL_FM [3] */
5791		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5792		FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5793		/* SEL_HSCIF0 [3] */
5794		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5795		FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5796		/* SEL_GPS [2] */
5797		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5798		/* RESERVED [3] */
5799		/* SEL_SIM [2] */
5800		FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5801		/* SEL_SSI8 [2] */
5802		FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
5803	},
5804	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5805			     GROUP(1, 1, -12, 2, -6, 3, 2, 3, 2),
5806			     GROUP(
5807		/* SEL_IICDVFS [1] */
5808		FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5809		/* SEL_IIC0 [1] */
5810		FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5811		/* RESERVED [12] */
5812		/* SEL_IEB [2] */
5813		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5814		/* RESERVED [6] */
5815		/* SEL_IIC2 [3] */
5816		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5817		FN_SEL_IIC2_4, 0, 0, 0,
5818		/* SEL_IIC1 [2] */
5819		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5820		/* SEL_I2C2 [3] */
5821		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5822		FN_SEL_I2C2_4, 0, 0, 0,
5823		/* SEL_I2C1 [2] */
5824		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
5825	},
5826	{ /* sentinel */ }
5827};
5828
5829static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5830{
5831	if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
5832		return -EINVAL;
5833
5834	*pocctrl = 0xe606008c;
5835
5836	return 31 - (pin & 0x1f);
5837}
5838
5839static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5840	{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
5841		[ 0] = RCAR_GP_PIN(0, 16),	/* A0 */
5842		[ 1] = RCAR_GP_PIN(0, 17),	/* A1 */
5843		[ 2] = RCAR_GP_PIN(0, 18),	/* A2 */
5844		[ 3] = RCAR_GP_PIN(0, 19),	/* A3 */
5845		[ 4] = RCAR_GP_PIN(0, 20),	/* A4 */
5846		[ 5] = RCAR_GP_PIN(0, 21),	/* A5 */
5847		[ 6] = RCAR_GP_PIN(0, 22),	/* A6 */
5848		[ 7] = RCAR_GP_PIN(0, 23),	/* A7 */
5849		[ 8] = RCAR_GP_PIN(0, 24),	/* A8 */
5850		[ 9] = RCAR_GP_PIN(0, 25),	/* A9 */
5851		[10] = RCAR_GP_PIN(0, 26),	/* A10 */
5852		[11] = RCAR_GP_PIN(0, 27),	/* A11 */
5853		[12] = RCAR_GP_PIN(0, 28),	/* A12 */
5854		[13] = RCAR_GP_PIN(0, 29),	/* A13 */
5855		[14] = RCAR_GP_PIN(0, 30),	/* A14 */
5856		[15] = RCAR_GP_PIN(0, 31),	/* A15 */
5857		[16] = RCAR_GP_PIN(1, 0),	/* A16 */
5858		[17] = RCAR_GP_PIN(1, 1),	/* A17 */
5859		[18] = RCAR_GP_PIN(1, 2),	/* A18 */
5860		[19] = RCAR_GP_PIN(1, 3),	/* A19 */
5861		[20] = RCAR_GP_PIN(1, 4),	/* A20 */
5862		[21] = RCAR_GP_PIN(1, 5),	/* A21 */
5863		[22] = RCAR_GP_PIN(1, 6),	/* A22 */
5864		[23] = RCAR_GP_PIN(1, 7),	/* A23 */
5865		[24] = RCAR_GP_PIN(1, 8),	/* A24 */
5866		[25] = RCAR_GP_PIN(1, 9),	/* A25 */
5867		[26] = RCAR_GP_PIN(1, 12),	/* EX_CS0# */
5868		[27] = RCAR_GP_PIN(1, 13),	/* EX_CS1# */
5869		[28] = RCAR_GP_PIN(1, 14),	/* EX_CS2# */
5870		[29] = RCAR_GP_PIN(1, 15),	/* EX_CS3# */
5871		[30] = RCAR_GP_PIN(1, 16),	/* EX_CS4# */
5872		[31] = RCAR_GP_PIN(1, 17),	/* EX_CS5# */
5873	} },
5874	{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
5875		/* PUPR1 pull-up pins */
5876		[ 0] = RCAR_GP_PIN(1, 18),	/* BS# */
5877		[ 1] = RCAR_GP_PIN(1, 19),	/* RD# */
5878		[ 2] = RCAR_GP_PIN(1, 20),	/* RD/WR# */
5879		[ 3] = RCAR_GP_PIN(1, 21),	/* WE0# */
5880		[ 4] = RCAR_GP_PIN(1, 22),	/* WE1# */
5881		[ 5] = RCAR_GP_PIN(1, 23),	/* EX_WAIT0 */
5882		[ 6] = RCAR_GP_PIN(5, 24),	/* AVS1 */
5883		[ 7] = RCAR_GP_PIN(5, 25),	/* AVS2 */
5884		[ 8] = RCAR_GP_PIN(1, 10),	/* CS0# */
5885		[ 9] = RCAR_GP_PIN(1, 11),	/* CS1#/A26 */
5886		[10] = PIN_TRST_N,		/* TRST# */
5887		[11] = PIN_TCK,			/* TCK */
5888		[12] = PIN_TMS,			/* TMS */
5889		[13] = PIN_TDI,			/* TDI */
5890		[14] = SH_PFC_PIN_NONE,
5891		[15] = SH_PFC_PIN_NONE,
5892		[16] = RCAR_GP_PIN(0, 0),	/* D0 */
5893		[17] = RCAR_GP_PIN(0, 1),	/* D1 */
5894		[18] = RCAR_GP_PIN(0, 2),	/* D2 */
5895		[19] = RCAR_GP_PIN(0, 3),	/* D3 */
5896		[20] = RCAR_GP_PIN(0, 4),	/* D4 */
5897		[21] = RCAR_GP_PIN(0, 5),	/* D5 */
5898		[22] = RCAR_GP_PIN(0, 6),	/* D6 */
5899		[23] = RCAR_GP_PIN(0, 7),	/* D7 */
5900		[24] = RCAR_GP_PIN(0, 8),	/* D8 */
5901		[25] = RCAR_GP_PIN(0, 9),	/* D9 */
5902		[26] = RCAR_GP_PIN(0, 10),	/* D10 */
5903		[27] = RCAR_GP_PIN(0, 11),	/* D11 */
5904		[28] = RCAR_GP_PIN(0, 12),	/* D12 */
5905		[29] = RCAR_GP_PIN(0, 13),	/* D13 */
5906		[30] = RCAR_GP_PIN(0, 14),	/* D14 */
5907		[31] = RCAR_GP_PIN(0, 15),	/* D15 */
5908	} },
5909	{ PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
5910		/* PUPR1 pull-down pins */
5911		[ 0] = SH_PFC_PIN_NONE,
5912		[ 1] = SH_PFC_PIN_NONE,
5913		[ 2] = SH_PFC_PIN_NONE,
5914		[ 3] = SH_PFC_PIN_NONE,
5915		[ 4] = SH_PFC_PIN_NONE,
5916		[ 5] = SH_PFC_PIN_NONE,
5917		[ 6] = SH_PFC_PIN_NONE,
5918		[ 7] = SH_PFC_PIN_NONE,
5919		[ 8] = SH_PFC_PIN_NONE,
5920		[ 9] = SH_PFC_PIN_NONE,
5921		[10] = SH_PFC_PIN_NONE,
5922		[11] = SH_PFC_PIN_NONE,
5923		[12] = SH_PFC_PIN_NONE,
5924		[13] = SH_PFC_PIN_NONE,
5925		[14] = SH_PFC_PIN_NONE,
5926		[15] = PIN_ASEBRK_N_ACK,	/* ASEBRK#/ACK */
5927		[16] = SH_PFC_PIN_NONE,
5928		[17] = SH_PFC_PIN_NONE,
5929		[18] = SH_PFC_PIN_NONE,
5930		[19] = SH_PFC_PIN_NONE,
5931		[20] = SH_PFC_PIN_NONE,
5932		[21] = SH_PFC_PIN_NONE,
5933		[22] = SH_PFC_PIN_NONE,
5934		[23] = SH_PFC_PIN_NONE,
5935		[24] = SH_PFC_PIN_NONE,
5936		[25] = SH_PFC_PIN_NONE,
5937		[26] = SH_PFC_PIN_NONE,
5938		[27] = SH_PFC_PIN_NONE,
5939		[28] = SH_PFC_PIN_NONE,
5940		[29] = SH_PFC_PIN_NONE,
5941		[30] = SH_PFC_PIN_NONE,
5942		[31] = SH_PFC_PIN_NONE,
5943	} },
5944	{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
5945		[ 0] = RCAR_GP_PIN(5, 28),	/* DU_DOTCLKIN2 */
5946		[ 1] = SH_PFC_PIN_NONE,
5947		[ 2] = SH_PFC_PIN_NONE,
5948		[ 3] = SH_PFC_PIN_NONE,
5949		[ 4] = SH_PFC_PIN_NONE,
5950		[ 5] = RCAR_GP_PIN(2, 0),	/* VI0_CLK */
5951		[ 6] = RCAR_GP_PIN(2, 1),	/* VI0_DATA0_VI0_B0 */
5952		[ 7] = RCAR_GP_PIN(2, 2),	/* VI0_DATA1_VI0_B1 */
5953		[ 8] = RCAR_GP_PIN(2, 3),	/* VI0_DATA2_VI0_B2 */
5954		[ 9] = RCAR_GP_PIN(2, 4),	/* VI0_DATA3_VI0_B3 */
5955		[10] = RCAR_GP_PIN(2, 5),	/* VI0_DATA4_VI0_B4 */
5956		[11] = RCAR_GP_PIN(2, 6),	/* VI0_DATA5_VI0_B5 */
5957		[12] = RCAR_GP_PIN(2, 7),	/* VI0_DATA6_VI0_B6 */
5958		[13] = RCAR_GP_PIN(2, 8),	/* VI0_DATA7_VI0_B7 */
5959		[14] = RCAR_GP_PIN(2, 9),	/* VI1_CLK */
5960		[15] = RCAR_GP_PIN(2, 10),	/* VI1_DATA0_VI1_B0 */
5961		[16] = RCAR_GP_PIN(2, 11),	/* VI1_DATA1_VI1_B1 */
5962		[17] = RCAR_GP_PIN(2, 12),	/* VI1_DATA2_VI1_B2 */
5963		[18] = RCAR_GP_PIN(2, 13),	/* VI1_DATA3_VI1_B3 */
5964		[19] = RCAR_GP_PIN(2, 14),	/* VI1_DATA4_VI1_B4 */
5965		[20] = RCAR_GP_PIN(2, 15),	/* VI1_DATA5_VI1_B5 */
5966		[21] = RCAR_GP_PIN(2, 16),	/* VI1_DATA6_VI1_B6 */
5967		[22] = RCAR_GP_PIN(2, 17),	/* VI1_DATA7_VI1_B7 */
5968		[23] = RCAR_GP_PIN(5, 27),	/* DU_DOTCLKIN1 */
5969		[24] = SH_PFC_PIN_NONE,
5970		[25] = SH_PFC_PIN_NONE,
5971		[26] = SH_PFC_PIN_NONE,
5972		[27] = RCAR_GP_PIN(4, 0),	/* MLB_CLK */
5973		[28] = RCAR_GP_PIN(4, 1),	/* MLB_SIG */
5974		[29] = RCAR_GP_PIN(4, 2),	/* MLB_DAT */
5975		[30] = SH_PFC_PIN_NONE,
5976		[31] = RCAR_GP_PIN(5, 26),	/* DU_DOTCLKIN0 */
5977	} },
5978	{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
5979		[ 0] = RCAR_GP_PIN(3, 0),	/* SD0_CLK */
5980		[ 1] = RCAR_GP_PIN(3, 1),	/* SD0_CMD */
5981		[ 2] = RCAR_GP_PIN(3, 2),	/* SD0_DAT0 */
5982		[ 3] = RCAR_GP_PIN(3, 3),	/* SD0_DAT1 */
5983		[ 4] = RCAR_GP_PIN(3, 4),	/* SD0_DAT2 */
5984		[ 5] = RCAR_GP_PIN(3, 5),	/* SD0_DAT3 */
5985		[ 6] = RCAR_GP_PIN(3, 6),	/* SD0_CD */
5986		[ 7] = RCAR_GP_PIN(3, 7),	/* SD0_WP */
5987		[ 8] = RCAR_GP_PIN(3, 8),	/* SD1_CLK */
5988		[ 9] = RCAR_GP_PIN(3, 9),	/* SD1_CMD */
5989		[10] = RCAR_GP_PIN(3, 10),	/* SD1_DAT0 */
5990		[11] = RCAR_GP_PIN(3, 11),	/* SD1_DAT1 */
5991		[12] = RCAR_GP_PIN(3, 12),	/* SD1_DAT2 */
5992		[13] = RCAR_GP_PIN(3, 13),	/* SD1_DAT3 */
5993		[14] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
5994		[15] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
5995		[16] = RCAR_GP_PIN(3, 16),	/* SD2_CLK */
5996		[17] = RCAR_GP_PIN(3, 17),	/* SD2_CMD */
5997		[18] = RCAR_GP_PIN(3, 18),	/* SD2_DAT0 */
5998		[19] = RCAR_GP_PIN(3, 19),	/* SD2_DAT1 */
5999		[20] = RCAR_GP_PIN(3, 20),	/* SD2_DAT2 */
6000		[21] = RCAR_GP_PIN(3, 21),	/* SD2_DAT3 */
6001		[22] = RCAR_GP_PIN(3, 22),	/* SD2_CD */
6002		[23] = RCAR_GP_PIN(3, 23),	/* SD2_WP */
6003		[24] = RCAR_GP_PIN(3, 24),	/* SD3_CLK */
6004		[25] = RCAR_GP_PIN(3, 25),	/* SD3_CMD */
6005		[26] = RCAR_GP_PIN(3, 26),	/* SD3_DAT0 */
6006		[27] = RCAR_GP_PIN(3, 27),	/* SD3_DAT1 */
6007		[28] = RCAR_GP_PIN(3, 28),	/* SD3_DAT2 */
6008		[29] = RCAR_GP_PIN(3, 29),	/* SD3_DAT3 */
6009		[30] = RCAR_GP_PIN(3, 30),	/* SD3_CD */
6010		[31] = RCAR_GP_PIN(3, 31),	/* SD3_WP */
6011	} },
6012	{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6013		[ 0] = RCAR_GP_PIN(4, 3),	/* SSI_SCK0129 */
6014		[ 1] = RCAR_GP_PIN(4, 4),	/* SSI_WS0129 */
6015		[ 2] = RCAR_GP_PIN(4, 5),	/* SSI_SDATA0 */
6016		[ 3] = RCAR_GP_PIN(4, 6),	/* SSI_SDATA1 */
6017		[ 4] = RCAR_GP_PIN(4, 7),	/* SSI_SDATA2 */
6018		[ 5] = RCAR_GP_PIN(4, 8),	/* SSI_SCK34 */
6019		[ 6] = RCAR_GP_PIN(4, 9),	/* SSI_WS34 */
6020		[ 7] = RCAR_GP_PIN(4, 10),	/* SSI_SDATA3 */
6021		[ 8] = RCAR_GP_PIN(4, 11),	/* SSI_SCK4 */
6022		[ 9] = RCAR_GP_PIN(4, 12),	/* SSI_WS4 */
6023		[10] = RCAR_GP_PIN(4, 13),	/* SSI_SDATA4 */
6024		[11] = RCAR_GP_PIN(4, 14),	/* SSI_SCK5 */
6025		[12] = RCAR_GP_PIN(4, 15),	/* SSI_WS5 */
6026		[13] = RCAR_GP_PIN(4, 16),	/* SSI_SDATA5 */
6027		[14] = RCAR_GP_PIN(4, 17),	/* SSI_SCK6 */
6028		[15] = RCAR_GP_PIN(4, 18),	/* SSI_WS6 */
6029		[16] = RCAR_GP_PIN(4, 19),	/* SSI_SDATA6 */
6030		[17] = RCAR_GP_PIN(4, 20),	/* SSI_SCK78 */
6031		[18] = RCAR_GP_PIN(4, 21),	/* SSI_WS78 */
6032		[19] = RCAR_GP_PIN(4, 22),	/* SSI_SDATA7 */
6033		[20] = RCAR_GP_PIN(4, 23),	/* SSI_SDATA8 */
6034		[21] = RCAR_GP_PIN(4, 24),	/* SSI_SDATA9 */
6035		[22] = RCAR_GP_PIN(4, 25),	/* AUDIO_CLKA */
6036		[23] = RCAR_GP_PIN(4, 26),	/* AUDIO_CLKB */
6037		[24] = RCAR_GP_PIN(1, 24),	/* DREQ0 */
6038		[25] = RCAR_GP_PIN(1, 25),	/* DACK0 */
6039		[26] = RCAR_GP_PIN(1, 26),	/* DREQ1 */
6040		[27] = RCAR_GP_PIN(1, 27),	/* DACK1 */
6041		[28] = RCAR_GP_PIN(1, 28),	/* DREQ2 */
6042		[29] = RCAR_GP_PIN(1, 29),	/* DACK2 */
6043		[30] = RCAR_GP_PIN(2, 18),	/* ETH_CRS_DV */
6044		[31] = RCAR_GP_PIN(2, 19),	/* ETH_RX_ER */
6045	} },
6046	{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6047		[ 0] = RCAR_GP_PIN(4, 27),	/* SCIFA0_SCK */
6048		[ 1] = RCAR_GP_PIN(4, 28),	/* SCIFA0_RXD */
6049		[ 2] = RCAR_GP_PIN(4, 29),	/* SCIFA0_TXD */
6050		[ 3] = RCAR_GP_PIN(4, 30),	/* SCIFA0_CTS# */
6051		[ 4] = RCAR_GP_PIN(4, 31),	/* SCIFA0_RTS# */
6052		[ 5] = RCAR_GP_PIN(5, 0),	/* SCIFA1_RXD */
6053		[ 6] = RCAR_GP_PIN(5, 1),	/* SCIFA1_TXD */
6054		[ 7] = RCAR_GP_PIN(5, 2),	/* SCIFA1_CTS# */
6055		[ 8] = RCAR_GP_PIN(5, 3),	/* SCIFA1_RTS# */
6056		[ 9] = RCAR_GP_PIN(5, 4),	/* SCIFA2_SCK */
6057		[10] = RCAR_GP_PIN(5, 5),	/* SCIFA2_RXD */
6058		[11] = RCAR_GP_PIN(5, 6),	/* SCIFA2_TXD */
6059		[12] = RCAR_GP_PIN(5, 7),	/* HSCK0 */
6060		[13] = RCAR_GP_PIN(5, 8),	/* HRX0 */
6061		[14] = RCAR_GP_PIN(5, 9),	/* HTX0 */
6062		[15] = RCAR_GP_PIN(5, 10),	/* HCTS0# */
6063		[16] = RCAR_GP_PIN(5, 11),	/* HRTS0# */
6064		[17] = RCAR_GP_PIN(5, 12),	/* MSIOF0_SCK */
6065		[18] = RCAR_GP_PIN(5, 13),	/* MSIOF0_SYNC */
6066		[19] = RCAR_GP_PIN(5, 14),	/* MSIOF0_SS1 */
6067		[20] = RCAR_GP_PIN(5, 15),	/* MSIOF0_TXD */
6068		[21] = RCAR_GP_PIN(5, 16),	/* MSIOF0_SS2 */
6069		[22] = RCAR_GP_PIN(5, 17),	/* MSIOF0_RXD */
6070		[23] = RCAR_GP_PIN(5, 18),	/* USB0_PWEN */
6071		[24] = RCAR_GP_PIN(5, 19),	/* USB0_OVC_VBUS */
6072		[25] = RCAR_GP_PIN(5, 20),	/* USB1_PWEN */
6073		[26] = RCAR_GP_PIN(5, 21),	/* USB1_OVC */
6074		[27] = RCAR_GP_PIN(5, 22),	/* USB2_PWEN */
6075		[28] = RCAR_GP_PIN(5, 23),	/* USB2_OVC */
6076		[29] = RCAR_GP_PIN(2, 20),	/* ETH_RXD0 */
6077		[30] = RCAR_GP_PIN(2, 21),	/* ETH_RXD1 */
6078		[31] = RCAR_GP_PIN(2, 22),	/* ETH_LINK */
6079	} },
6080	{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6081		[ 0] = RCAR_GP_PIN(2, 23),	/* ETH_REF_CLK */
6082		[ 1] = RCAR_GP_PIN(2, 24),	/* ETH_MDIO */
6083		[ 2] = RCAR_GP_PIN(2, 25),	/* ETH_TXD1 */
6084		[ 3] = RCAR_GP_PIN(2, 26),	/* ETH_TX_EN */
6085		[ 4] = RCAR_GP_PIN(2, 27),	/* ETH_MAGIC */
6086		[ 5] = RCAR_GP_PIN(2, 28),	/* ETH_TXD0 */
6087		[ 6] = RCAR_GP_PIN(2, 29),	/* ETH_MDC */
6088		[ 7] = RCAR_GP_PIN(5, 29),	/* PWM0 */
6089		[ 8] = RCAR_GP_PIN(5, 30),	/* PWM1 */
6090		[ 9] = RCAR_GP_PIN(5, 31),	/* PWM2 */
6091		[10] = SH_PFC_PIN_NONE,
6092		[11] = SH_PFC_PIN_NONE,
6093		[12] = SH_PFC_PIN_NONE,
6094		[13] = SH_PFC_PIN_NONE,
6095		[14] = SH_PFC_PIN_NONE,
6096		[15] = SH_PFC_PIN_NONE,
6097		[16] = SH_PFC_PIN_NONE,
6098		[17] = SH_PFC_PIN_NONE,
6099		[18] = SH_PFC_PIN_NONE,
6100		[19] = SH_PFC_PIN_NONE,
6101		[20] = SH_PFC_PIN_NONE,
6102		[21] = SH_PFC_PIN_NONE,
6103		[22] = SH_PFC_PIN_NONE,
6104		[23] = SH_PFC_PIN_NONE,
6105		[24] = SH_PFC_PIN_NONE,
6106		[25] = SH_PFC_PIN_NONE,
6107		[26] = SH_PFC_PIN_NONE,
6108		[27] = SH_PFC_PIN_NONE,
6109		[28] = SH_PFC_PIN_NONE,
6110		[29] = SH_PFC_PIN_NONE,
6111		[30] = SH_PFC_PIN_NONE,
6112		[31] = SH_PFC_PIN_NONE,
6113	} },
6114	{ /* sentinel */ }
6115};
6116
6117static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
6118{
6119	/* Initialize TDSEL on old revisions */
6120	if ((renesas_get_cpu_rev_integer() == 1) &&
6121	    (renesas_get_cpu_rev_fraction() == 0))
6122		sh_pfc_write(pfc, 0xe6060088, 0x00155554);
6123
6124	return 0;
6125}
6126
6127static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
6128	.init = r8a7790_pinmux_soc_init,
6129	.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
6130	.get_bias = rcar_pinmux_get_bias,
6131	.set_bias = rcar_pinmux_set_bias,
6132};
6133
6134#ifdef CONFIG_PINCTRL_PFC_R8A7742
6135const struct sh_pfc_soc_info r8a7742_pinmux_info = {
6136	.name = "r8a77420_pfc",
6137	.ops = &r8a7790_pfc_ops,
6138	.unlock_reg = 0xe6060000, /* PMMR */
6139
6140	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6141
6142	.pins = pinmux_pins,
6143	.nr_pins = ARRAY_SIZE(pinmux_pins),
6144	.groups = pinmux_groups.common,
6145	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
6146	.functions = pinmux_functions.common,
6147	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
6148
6149	.cfg_regs = pinmux_config_regs,
6150	.bias_regs = pinmux_bias_regs,
6151
6152	.pinmux_data = pinmux_data,
6153	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6154};
6155#endif
6156
6157#ifdef CONFIG_PINCTRL_PFC_R8A7790
6158const struct sh_pfc_soc_info r8a7790_pinmux_info = {
6159	.name = "r8a77900_pfc",
6160	.ops = &r8a7790_pfc_ops,
6161	.unlock_reg = 0xe6060000, /* PMMR */
6162
6163	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6164
6165	.pins = pinmux_pins,
6166	.nr_pins = ARRAY_SIZE(pinmux_pins),
6167	.groups = pinmux_groups.common,
6168	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6169		ARRAY_SIZE(pinmux_groups.automotive),
6170	.functions = pinmux_functions.common,
6171	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6172		ARRAY_SIZE(pinmux_functions.automotive),
6173
6174	.cfg_regs = pinmux_config_regs,
6175	.bias_regs = pinmux_bias_regs,
6176
6177	.pinmux_data = pinmux_data,
6178	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6179};
6180#endif
6181