Searched refs:div (Results 1 - 25 of 30) sorted by relevance

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/seL4-refos-master/libs/libmuslc/src/stdlib/
H A Ddiv.c3 div_t div(int num, int den) function
/seL4-refos-master/libs/libplatsupport/src/mach/exynos/clock/
H A Dexynos_5422_clock.h22 volatile uint32_t div[64]; /* 0x500 */ member in struct:clk_regs
H A Dexynos_common_clock.h22 volatile uint32_t div[64]; /* 0x500 */ member in struct:clk_regs
/seL4-refos-master/projects/util_libs/libplatsupport/src/mach/exynos/clock/
H A Dexynos_5422_clock.h22 volatile uint32_t div[64]; /* 0x500 */ member in struct:clk_regs
H A Dexynos_common_clock.h22 volatile uint32_t div[64]; /* 0x500 */ member in struct:clk_regs
/seL4-refos-master/libs/libplatsupport/src/mach/exynos/
H A Dclock.c23 uint32_t div; local
29 div = exynos_cmu_get_div(clk_regs, clkid, 1);
30 return fin / (div + 1);
37 uint32_t div; local
51 div = fin / hz;
52 if (div > MASK(DIV_VAL_BITS)) {
54 div = MASK(CLK_DIV_BITS);
57 exynos_cmu_set_div(clk_regs, clkid, 1, div);
H A Dclock.h206 return clkbf_get(&regs[c]->div[r], o * CLK_DIV_BITS, CLK_DIV_BITS * span);
210 exynos_cmu_set_div(clk_regs_io_t** regs, int clkid, int span, int div) argument
214 clkbf_set(&regs[c]->div[r], o * CLK_DIV_BITS, CLK_DIV_BITS * span, --div);
H A Dpwm.c89 uint32_t div = 0; /* Not implemented */ local
92 uint32_t cnt = ticks / (prescale + 1) / (BIT(div));
94 assert(prescale <= 0xff); /* if this fails, we need to implement div */
95 assert(div <= 0xf);
100 pwm->pwm_map->tcfg1 &= T4_DIVISOR(div);
104 pwm->pwm_map->tcfg1 &= T0_DIVISOR(div);
/seL4-refos-master/projects/util_libs/libplatsupport/src/mach/exynos/
H A Dclock.c23 uint32_t div; local
29 div = exynos_cmu_get_div(clk_regs, clkid, 1);
30 return fin / (div + 1);
37 uint32_t div; local
51 div = fin / hz;
52 if (div > MASK(DIV_VAL_BITS)) {
54 div = MASK(CLK_DIV_BITS);
57 exynos_cmu_set_div(clk_regs, clkid, 1, div);
H A Dclock.h206 return clkbf_get(&regs[c]->div[r], o * CLK_DIV_BITS, CLK_DIV_BITS * span);
210 exynos_cmu_set_div(clk_regs_io_t** regs, int clkid, int span, int div) argument
214 clkbf_set(&regs[c]->div[r], o * CLK_DIV_BITS, CLK_DIV_BITS * span, --div);
H A Dpwm.c89 uint32_t div = 0; /* Not implemented */ local
92 uint32_t cnt = ticks / (prescale + 1) / (BIT(div));
94 assert(prescale <= 0xff); /* if this fails, we need to implement div */
95 assert(div <= 0xf);
100 pwm->pwm_map->tcfg1 &= T4_DIVISOR(div);
104 pwm->pwm_map->tcfg1 &= T0_DIVISOR(div);
/seL4-refos-master/libs/libplatsupport/src/plat/imx6/
H A Dclock.c197 uint32_t div; local
199 div = clk_regs.alg->pll_arm.val;
200 div &= PLL_ARM_DIV_MASK;
202 fout = fin * div / 2;
209 uint32_t div; local
214 div = 2 * hz / fin;
215 div = INRANGE(54, div, 108);
220 v |= div;
254 uint32_t div; local
277 uint32_t div, fin; local
493 uint32_t div = (pll_usb->val & PLL_USB_DIV_MASK) ? 22 : 20; local
550 uint32_t div; local
569 uint32_t div = (fin / hz) + 1; local
[all...]
H A Di2c.c40 uint16_t div; member in struct:imx6_i2c_regs
105 _i2c_prescale_decode(int div) argument
115 this_error = _i2c_div_map[i] - div;
151 int div = _i2c_div_map[dev->regs->div]; local
152 return fin / div;
160 uint32_t div = fin / hz; local
161 assert((div > 22 && div <= 3840) || !"Parent calibration not implemented");
162 dev->regs->div
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/imx6/
H A Dclock.c197 uint32_t div; local
199 div = clk_regs.alg->pll_arm.val;
200 div &= PLL_ARM_DIV_MASK;
202 fout = fin * div / 2;
209 uint32_t div; local
214 div = 2 * hz / fin;
215 div = INRANGE(54, div, 108);
220 v |= div;
254 uint32_t div; local
277 uint32_t div, fin; local
493 uint32_t div = (pll_usb->val & PLL_USB_DIV_MASK) ? 22 : 20; local
550 uint32_t div; local
569 uint32_t div = (fin / hz) + 1; local
[all...]
H A Di2c.c40 uint16_t div; member in struct:imx6_i2c_regs
105 _i2c_prescale_decode(int div) argument
115 this_error = _i2c_div_map[i] - div;
151 int div = _i2c_div_map[dev->regs->div]; local
152 return fin / div;
160 uint32_t div = fin / hz; local
161 assert((div > 22 && div <= 3840) || !"Parent calibration not implemented");
162 dev->regs->div
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/hifive/
H A Duart.c41 uint32_t div; member in struct:uart
120 if (regs->div != UART_BAUD_DIVISOR) {
122 ZF_LOGW("Warning: However an incorrect divisor is set: %d, expected %d", regs->div, UART_BAUD_DIVISOR);
/seL4-refos-master/libs/libplatsupport/src/plat/hifive/
H A Duart.c41 uint32_t div; member in struct:uart
120 if (regs->div != UART_BAUD_DIVISOR) {
122 ZF_LOGW("Warning: However an incorrect divisor is set: %d, expected %d", regs->div, UART_BAUD_DIVISOR);
/seL4-refos-master/libs/libplatsupport/src/plat/exynos4/
H A Dclock.c187 assert(!"Unknown clock id for div");
196 static struct clock sclkapll_clk = { CLK_OPS(SCLKAPLL , div, CLKID_SCLKAPLL) };
197 static struct clock divcore_clk = { CLK_OPS(DIVCORE , div, CLKID_DIVCORE) };
198 static struct clock arm_clk = { CLK_OPS(DIVCORE2 , div, CLKID_DIVCORE2) };
199 static struct clock corem0_clk = { CLK_OPS(ACLK_COREM0, div, CLKID_ACLK_COREM0) };
200 static struct clock corem1_clk = { CLK_OPS(ACLK_COREM1, div, CLKID_ACLK_COREM1) };
201 static struct clock cores_clk = { CLK_OPS(ACLK_CORES , div, CLKID_ACLK_CORES) };
202 static struct clock periphclk_clk = { CLK_OPS(PERIPHCLK , div, CLKID_PERIPHCLK) };
203 static struct clock atclk_clk = { CLK_OPS(ATCLK , div, CLKID_ATCLK) };
204 static struct clock pclk_dbg_clk = { CLK_OPS(PCLK_DBG , div, CLKID_PCLK_DB
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos4/
H A Dclock.c187 assert(!"Unknown clock id for div");
196 static struct clock sclkapll_clk = { CLK_OPS(SCLKAPLL , div, CLKID_SCLKAPLL) };
197 static struct clock divcore_clk = { CLK_OPS(DIVCORE , div, CLKID_DIVCORE) };
198 static struct clock arm_clk = { CLK_OPS(DIVCORE2 , div, CLKID_DIVCORE2) };
199 static struct clock corem0_clk = { CLK_OPS(ACLK_COREM0, div, CLKID_ACLK_COREM0) };
200 static struct clock corem1_clk = { CLK_OPS(ACLK_COREM1, div, CLKID_ACLK_COREM1) };
201 static struct clock cores_clk = { CLK_OPS(ACLK_CORES , div, CLKID_ACLK_CORES) };
202 static struct clock periphclk_clk = { CLK_OPS(PERIPHCLK , div, CLKID_PERIPHCLK) };
203 static struct clock atclk_clk = { CLK_OPS(ATCLK , div, CLKID_ATCLK) };
204 static struct clock pclk_dbg_clk = { CLK_OPS(PCLK_DBG , div, CLKID_PCLK_DB
[all...]
/seL4-refos-master/libs/libplatsupport/src/plat/exynos5/
H A Dclock.c132 /* The SPI div register is a special case as we have 2 dividers, one of which
235 int div; local
239 div = exynos_cmu_get_div(_clk_regs, clkid, 1);
241 return fin / (div + 1);
249 int div; local
251 div = fin / hz;
255 exynos_cmu_set_div(_clk_regs, clkid, 1, div);
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos5/
H A Dclock.c132 /* The SPI div register is a special case as we have 2 dividers, one of which
235 int div; local
239 div = exynos_cmu_get_div(_clk_regs, clkid, 1);
241 return fin / (div + 1);
249 int div; local
251 div = fin / hz;
255 exynos_cmu_set_div(_clk_regs, clkid, 1, div);
/seL4-refos-master/libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c189 #define CLK_DIVISOR(div, x) ((x) * BIT(CLK_DIVISOR##div##_SHIFT))
190 #define CLK_DIVISOR_MASK(div) CLK_DIVISOR(div, CLK_DIVISOR_MAX)
191 #define CLK_SET_DIVISOR(div, reg, val) \
194 v = reg & ~(CLK_DIVISOR_MASK(div)); \
195 reg = v | CLK_DIVISOR(div, val); \
197 #define CLK_GET_DIVISOR(div, reg) \
198 ((reg & CLK_DIVISOR_MASK(div)) >> CLK_DIVISOR##div##_SHIF
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c189 #define CLK_DIVISOR(div, x) ((x) * BIT(CLK_DIVISOR##div##_SHIFT))
190 #define CLK_DIVISOR_MASK(div) CLK_DIVISOR(div, CLK_DIVISOR_MAX)
191 #define CLK_SET_DIVISOR(div, reg, val) \
194 v = reg & ~(CLK_DIVISOR_MASK(div)); \
195 reg = v | CLK_DIVISOR(div, val); \
197 #define CLK_GET_DIVISOR(div, reg) \
198 ((reg & CLK_DIVISOR_MASK(div)) >> CLK_DIVISOR##div##_SHIF
[all...]
/seL4-refos-master/libs/libplatsupport/src/plat/apq8064/
H A Dtimer.c356 int div; local
363 div = 4;
364 regs->mtch = (fin_hz * ns) / (div * 1000 * 1000 * 1000);
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/apq8064/
H A Dtimer.c356 int div; local
363 div = 4;
364 regs->mtch = (fin_hz * ns) / (div * 1000 * 1000 * 1000);

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