History log of /seL4-refos-master/projects/util_libs/libplatsupport/src/mach/exynos/clock.h
Revision Date Author Comments
# a0359d73 03-Dec-2018 Adam Felizzi <Adam.Felizzi@data61.csiro.au>

platsupport: Refactored exynos pll_get_freq

Updated the implementation of _pll_get_freq. This differs based
on the exynos SoC, Exynos5422 in particular. The implemenation
of get_freq has been moved out into different source files. These
source files are conditionally compiled in depending on the
target SoC.


# e8a18cd9 03-Dec-2018 Adam Felizzi <Adam.Felizzi@data61.csiro.au>

platsupport: Refactored Exynos5422 clk address map

The clock controller address map for the exynos5422 differs from
the other exynos platforms that are supported. Moved out the
definition of clk_regs into its own header. This header is
conditionally included based on the exynos soc.


# aff6136b 03-Dec-2018 Adam Felizzi <Adam.Felizzi@data61.csiro.au>

platsupport: Moved exynos clock defs into header

Moved PLL and DIV definitions into internal clock header. This
change has no effect other than tidying up the clock clode.


# ce2b7457 25-Nov-2018 Adam Felizzi <Adam.Felizzi@data61.csiro.au>

platsupport: Updated clock settings on exynos5422

The clock controller on the exynos5422 has a different
configuration compared to previous exynos54XX platforms the
library currently supports. In particilar the PLL CMUs have been
updated according to the exynos5422 specification. This allows
enables the user to properly set and get PLL frequency values.


# 5761b927 28-Sep-2017 Anna Lyons <Anna.Lyons@data61.csiro.au>

pragma once and for all


# 398af6af 13-Jul-2017 Anna Lyons <Anna.Lyons@data61.csiro.au>

Fix whitespace

- remove trailing whitespace
- remove duplicate blank lines
- remove blank lines at end of file


# a7130f9f 04-Jun-2017 Anna Lyons <Anna.Lyons@data61.csiro.au>

fix licenses