Searched refs:clk_sys (Results 1 - 25 of 25) sorted by relevance

/seL4-refos-master/libs/libplatsupport/src/plat/fvp/
H A Dclock_mux.c18 clock_sys_init(ps_io_ops_t* io_ops, clock_sys_t* clk_sys) argument
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/fvp/
H A Dclock_mux.c18 clock_sys_init(ps_io_ops_t* io_ops, clock_sys_t* clk_sys) argument
/seL4-refos-master/libs/libplatsupport/src/plat/apq8064/
H A Dclock.c126 static int apq8064_clock_sys_init_common(clock_sys_t* clk_sys) argument
128 clk_sys->gate_enable = &apq8064_gate_enable;
129 clk_sys->get_clock = &ps_get_clock;
134 clock_sys_init(ps_io_ops_t* io_ops, clock_sys_t* clk_sys) argument
141 clk_sys->priv = d;
148 clock_sys_t* clk_sys)
163 clk_sys->priv = d;
164 return apq8064_clock_sys_init_common(clk_sys);
146 apq8064_clock_sys_init(void* clk_ctl_base0, void* clk_ctl_base1, void* clk_ctl_base2, void* clk_ctl_base3, clock_sys_t* clk_sys) argument
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/apq8064/
H A Dclock.c126 static int apq8064_clock_sys_init_common(clock_sys_t* clk_sys) argument
128 clk_sys->gate_enable = &apq8064_gate_enable;
129 clk_sys->get_clock = &ps_get_clock;
134 clock_sys_init(ps_io_ops_t* io_ops, clock_sys_t* clk_sys) argument
141 clk_sys->priv = d;
148 clock_sys_t* clk_sys)
163 clk_sys->priv = d;
164 return apq8064_clock_sys_init_common(clk_sys);
146 apq8064_clock_sys_init(void* clk_ctl_base0, void* clk_ctl_base1, void* clk_ctl_base2, void* clk_ctl_base3, clock_sys_t* clk_sys) argument
/seL4-refos-master/libs/libplatsupport/src/plat/bcm2837/
H A Dspt.c198 clock_sys_t clk_sys; local
199 clock_sys_init_default(&clk_sys);
200 clk = clk_get_clock(&clk_sys, CLK_SP804);
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/bcm2837/
H A Dspt.c198 clock_sys_t clk_sys; local
199 clock_sys_init_default(&clk_sys);
200 clk = clk_get_clock(&clk_sys, CLK_SP804);
/seL4-refos-master/libs/libplatsupport/arch_include/arm/platsupport/
H A Ddma330.h49 * @param[in] clk_sys A handle to the clock subsytem for initialisation
53 int dma330_init_base(enum dma330_id id, void* dma330_base, clock_sys_t* clk_sys,
H A Dclock.h62 clock_sys_t *clk_sys; member in struct:clock
84 * @param[out] clock_sys On success, clk_sys will contain a handle
96 * @param[out] clock_sys On success, clk_sys will contain a handle
/seL4-refos-master/projects/util_libs/libplatsupport/arch_include/arm/platsupport/
H A Ddma330.h49 * @param[in] clk_sys A handle to the clock subsytem for initialisation
53 int dma330_init_base(enum dma330_id id, void* dma330_base, clock_sys_t* clk_sys,
H A Dclock.h62 clock_sys_t *clk_sys; member in struct:clock
84 * @param[out] clock_sys On success, clk_sys will contain a handle
96 * @param[out] clock_sys On success, clk_sys will contain a handle
/seL4-refos-master/libs/libplatsupport/plat_include/apq8064/platsupport/plat/
H A Dclock.h67 clock_sys_t* clk_sys);
/seL4-refos-master/libs/libplatsupport/src/arch/arm/
H A Dclock.h46 return clk->clk_sys;
H A Dclock.c69 clk->clk_sys = clock_sys;
113 clk->clk_sys = sys;
H A Ddma330.c481 dma330_init_base(enum dma330_id id, void* dma330_base, clock_sys_t* clk_sys, dma330_t* dma330) argument
487 assert(clk_sys);
/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/apq8064/platsupport/plat/
H A Dclock.h67 clock_sys_t* clk_sys);
/seL4-refos-master/projects/util_libs/libplatsupport/src/arch/arm/
H A Dclock.h46 return clk->clk_sys;
H A Dclock.c69 clk->clk_sys = clock_sys;
113 clk->clk_sys = sys;
H A Ddma330.c481 dma330_init_base(enum dma330_id id, void* dma330_base, clock_sys_t* clk_sys, dma330_t* dma330) argument
487 assert(clk_sys);
/seL4-refos-master/libs/libplatsupport/src/plat/imx6/
H A Di2c.c137 clk_t* parent = clk_get_clock(clk->clk_sys, CLK_PERCLK);
142 clk_gate_enable(clk->clk_sys, dev->clk_gate, CLKGATE_ON);
527 dev->clock.clk_sys = &io_ops->clock_sys;
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/imx6/
H A Di2c.c137 clk_t* parent = clk_get_clock(clk->clk_sys, CLK_PERCLK);
142 clk_gate_enable(clk->clk_sys, dev->clk_gate, CLKGATE_ON);
527 dev->clock.clk_sys = &io_ops->clock_sys;
/seL4-refos-master/projects/util_libs/libethdrivers/src/plat/imx6/
H A Denet.c542 clock_sys_t *clk_sys = malloc(sizeof(clock_sys_t)); local
543 clock_sys_init(io_ops, clk_sys);
544 enet_clk_ptr = clk_get_clock(clk_sys, CLK_ENET);
/seL4-refos-master/libs/libplatsupport/src/plat/exynos5/
H A Dclock.c217 parent = clk_get_clock(clk->clk_sys, clk_src_peri_blk[src]);
276 parent = clk_get_clock(clk->clk_sys, clk_src_peri_blk[src]);
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos5/
H A Dclock.c217 parent = clk_get_clock(clk->clk_sys, clk_src_peri_blk[src]);
276 parent = clk_get_clock(clk->clk_sys, clk_src_peri_blk[src]);
/seL4-refos-master/libs/libplatsupport/src/mach/exynos/
H A Dclock.h103 return clk_sys_get_clk_regs(clk->clk_sys);
/seL4-refos-master/projects/util_libs/libplatsupport/src/mach/exynos/
H A Dclock.h103 return clk_sys_get_clk_regs(clk->clk_sys);

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