1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#pragma once 14 15#define PXO_HZ 27000000UL 16#define CXO_HZ 19200000UL 17#define WCNXO_HZ 48000000UL /* WLAN */ 18#define SLPXO_HZ 32768UL 19 20#define TCXO_HZ 19200000UL /* Alias: TXCO (typo in docs) */ 21 22#define APQ8064_CLK_CTL0_PADDR 0x00900000 23#define APQ8064_CLK_CTL1_PADDR 0x00901000 24#define APQ8064_CLK_CTL2_PADDR 0x00902000 25#define APQ8064_CLK_CTL3_PADDR 0x00903000 26 27#define APQ8064_CLK_CTL_SIZE 0x1000 28#define APQ8064_CLK_CTL0_SIZE APQ8064_CLK_CTL_SIZE 29#define APQ8064_CLK_CTL1_SIZE APQ8064_CLK_CTL_SIZE 30#define APQ8064_CLK_CTL2_SIZE APQ8064_CLK_CTL_SIZE 31#define APQ8064_CLK_CTL3_SIZE APQ8064_CLK_CTL_SIZE 32 33enum clk_id { 34 CLK_MASTER, 35 CLK_PXO, 36 CLK_TCXO, 37 CLK_WCNXO, 38 CLK_SLPXO, 39#if 0 40 PLL0 GPLL0 PXO 800MHz 41 PLL1 MMPLL0 PXO 1332MHz 42 PLL2 MMPLL1 PXO 800MHz 43 PLL3 QDSPLL PXO 1200MHz 44 PLL4 LPAPLL PXO 393.2160MHz (491.52 ver2) 45 PLL5 MPLL0 CXO 288MHz 46 PLL8 SPPLL PXO 384MHz 47 PLL9 SCPLL0 PXO 2000MHz 48 PLL10 SCPLL1 PXO 2000MHz 49 PLL11 EBI1PLL PXO 1066MHz 50 PLL12 SCL2PLL PXO 1700MHz 51 PLL13 WCNPLL WCNXO (CXO used if WCNXO absent) 960MHz 52 PLL14 SP2PLL PXO 480MHz 53 PLL15 MMPLL3 PXO 975MHz 54 PLL16 SCPLL2 PXO 2000MHz 55 PLL17 SCPLL3 PXO 2000MHz 56 57#endif 58 NCLOCKS 59}; 60 61enum clock_gate { 62 NCLKGATES, 63}; 64 65int apq_clock_sys_init(void* clk_ctl_base0, void* clk_ctl_base1, 66 void* clk_ctl_base2, void* clk_ctl_base3, 67 clock_sys_t* clk_sys); 68 69