Searched refs:pll_settings (Results 1 - 11 of 11) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_clock_source.c180 * @pll_settings: Pointer to PLL settings
193 struct pll_settings *pll_settings,
206 pll_settings->adjusted_pix_clk_100hz,
225 pll_settings->adjusted_pix_clk_100hz)
227 pll_settings->adjusted_pix_clk_100hz
228 : pll_settings->adjusted_pix_clk_100hz -
233 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
234 pll_settings->reference_divider = ref_divider;
235 pll_settings
191 calc_fb_divider_checking_tolerance( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t ref_divider, uint32_t post_divider, uint32_t tolerance) argument
247 calc_pll_dividers_in_range( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t min_ref_divider, uint32_t max_ref_divider, uint32_t min_post_divider, uint32_t max_post_divider, uint32_t err_tolerance) argument
289 calculate_pixel_clock_pll_dividers( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings) argument
392 pll_adjust_pix_clk( struct dce110_clk_src *clk_src, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) argument
471 dce110_get_pix_clk_dividers_helper( struct dce110_clk_src *clk_src, struct pll_settings *pll_settings, struct pixel_clk_params *pix_clk_params) argument
533 dce112_get_pix_clk_dividers_helper( struct dce110_clk_src *clk_src, struct pll_settings *pll_settings, struct pixel_clk_params *pix_clk_params) argument
564 dce110_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) argument
597 dce112_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) argument
645 calculate_ss( const struct pll_settings *pll_settings, const struct spread_spectrum_data *ss_data, struct delta_sigma_data *ds_data) argument
710 enable_spread_spectrum( struct dce110_clk_src *clk_src, enum amd_signal_type signal, struct pll_settings *pll_settings) argument
840 dce110_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) argument
914 dce112_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) argument
961 dcn31_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) argument
1167 dcn20_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) argument
1213 dcn3_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) argument
1251 dcn3_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) argument
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/
H A Dclock_source.h106 struct pll_settings { struct
167 struct pll_settings *);
171 struct pll_settings *);
H A Dcore_types.h376 struct pll_settings pll_settings; member in struct:pipe_ctx
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_hwseq.c462 &pipe_ctx->pll_settings);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c1360 pipe_ctx->pll_settings.feedback_divider;
1370 pipe_ctx->pll_settings.ss_percentage;
1441 &pipe_ctx->pll_settings)) {
3084 &pipes[i].pll_settings);
H A Ddce110_resource.c923 &pipe_ctx->pll_settings);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_resource.c1044 &pipe_ctx->pll_settings);
H A Ddcn10_hw_sequencer.c928 &pipe_ctx->pll_settings)) {
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c1310 &pipe_ctx->pll_settings);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1283 &pipe_ctx->pll_settings);
H A Ddcn20_hwseq.c728 &pipe_ctx->pll_settings)) {

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