1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27#include "dm_services.h" 28#include "dm_helpers.h" 29#include "core_types.h" 30#include "resource.h" 31#include "dccg.h" 32#include "dce/dce_hwseq.h" 33#include "dcn30/dcn30_cm_common.h" 34#include "reg_helper.h" 35#include "abm.h" 36#include "hubp.h" 37#include "dchubbub.h" 38#include "timing_generator.h" 39#include "opp.h" 40#include "ipp.h" 41#include "mpc.h" 42#include "mcif_wb.h" 43#include "dc_dmub_srv.h" 44#include "link_hwss.h" 45#include "dpcd_defs.h" 46#include "dcn32_hwseq.h" 47#include "clk_mgr.h" 48#include "dsc.h" 49#include "dcn20/dcn20_optc.h" 50#include "dce/dmub_hw_lock_mgr.h" 51#include "dcn32_resource.h" 52#include "link.h" 53 54#define DC_LOGGER_INIT(logger) 55 56#define CTX \ 57 hws->ctx 58#define REG(reg)\ 59 hws->regs->reg 60#define DC_LOGGER \ 61 dc->ctx->logger 62 63 64#undef FN 65#define FN(reg_name, field_name) \ 66 hws->shifts->field_name, hws->masks->field_name 67 68void dcn32_dsc_pg_control( 69 struct dce_hwseq *hws, 70 unsigned int dsc_inst, 71 bool power_on) 72{ 73 uint32_t power_gate = power_on ? 0 : 1; 74 uint32_t pwr_status = power_on ? 0 : 2; 75 uint32_t org_ip_request_cntl = 0; 76 77 if (hws->ctx->dc->debug.disable_dsc_power_gate) 78 return; 79 80 if (!hws->ctx->dc->debug.enable_double_buffered_dsc_pg_support) 81 return; 82 83 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 84 if (org_ip_request_cntl == 0) 85 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 86 87 switch (dsc_inst) { 88 case 0: /* DSC0 */ 89 REG_UPDATE(DOMAIN16_PG_CONFIG, 90 DOMAIN_POWER_GATE, power_gate); 91 92 REG_WAIT(DOMAIN16_PG_STATUS, 93 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 94 1, 1000); 95 break; 96 case 1: /* DSC1 */ 97 REG_UPDATE(DOMAIN17_PG_CONFIG, 98 DOMAIN_POWER_GATE, power_gate); 99 100 REG_WAIT(DOMAIN17_PG_STATUS, 101 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 102 1, 1000); 103 break; 104 case 2: /* DSC2 */ 105 REG_UPDATE(DOMAIN18_PG_CONFIG, 106 DOMAIN_POWER_GATE, power_gate); 107 108 REG_WAIT(DOMAIN18_PG_STATUS, 109 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 110 1, 1000); 111 break; 112 case 3: /* DSC3 */ 113 REG_UPDATE(DOMAIN19_PG_CONFIG, 114 DOMAIN_POWER_GATE, power_gate); 115 116 REG_WAIT(DOMAIN19_PG_STATUS, 117 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 118 1, 1000); 119 break; 120 default: 121 BREAK_TO_DEBUGGER(); 122 break; 123 } 124 125 if (org_ip_request_cntl == 0) 126 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 127} 128 129 130void dcn32_enable_power_gating_plane( 131 struct dce_hwseq *hws, 132 bool enable) 133{ 134 bool force_on = true; /* disable power gating */ 135 uint32_t org_ip_request_cntl = 0; 136 137 if (enable) 138 force_on = false; 139 140 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 141 if (org_ip_request_cntl == 0) 142 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 143 144 /* DCHUBP0/1/2/3 */ 145 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 146 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 147 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 148 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 149 150 /* DCS0/1/2/3 */ 151 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 152 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 153 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 154 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 155 156 if (org_ip_request_cntl == 0) 157 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 158} 159 160void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 161{ 162 uint32_t power_gate = power_on ? 0 : 1; 163 uint32_t pwr_status = power_on ? 0 : 2; 164 165 if (hws->ctx->dc->debug.disable_hubp_power_gate) 166 return; 167 168 if (REG(DOMAIN0_PG_CONFIG) == 0) 169 return; 170 171 switch (hubp_inst) { 172 case 0: 173 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 174 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 175 break; 176 case 1: 177 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 178 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 179 break; 180 case 2: 181 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 182 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 183 break; 184 case 3: 185 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 186 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 187 break; 188 default: 189 BREAK_TO_DEBUGGER(); 190 break; 191 } 192} 193 194static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) 195{ 196 int i; 197 198 /* First, check no-memory-request case */ 199 for (i = 0; i < dc->current_state->stream_count; i++) { 200 if ((dc->current_state->stream_status[i].plane_count) && 201 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)) 202 /* Fail eligibility on a visible stream */ 203 break; 204 } 205 206 if (i == dc->current_state->stream_count) 207 return true; 208 209 return false; 210} 211 212 213/* This function loops through every surface that needs to be cached in CAB for SS, 214 * and calculates the total number of ways required to store all surfaces (primary, 215 * meta, cursor). 216 */ 217static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) 218{ 219 int i; 220 uint32_t num_ways = 0; 221 uint32_t mall_ss_size_bytes = 0; 222 223 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; 224 // TODO add additional logic for PSR active stream exclusion optimization 225 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes; 226 227 // Include cursor size for CAB allocation 228 for (i = 0; i < dc->res_pool->pipe_count; i++) { 229 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; 230 231 if (!pipe->stream || !pipe->plane_state) 232 continue; 233 234 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false); 235 } 236 237 // Convert number of cache lines required to number of ways 238 if (dc->debug.force_mall_ss_num_ways > 0) { 239 num_ways = dc->debug.force_mall_ss_num_ways; 240 } else { 241 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes); 242 } 243 244 return num_ways; 245} 246 247bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 248{ 249 union dmub_rb_cmd cmd; 250 uint8_t i; 251 uint32_t ways; 252 int j; 253 bool mall_ss_unsupported = false; 254 struct dc_plane_state *plane = NULL; 255 256 if (!dc->ctx->dmub_srv) 257 return false; 258 259 for (i = 0; i < dc->current_state->stream_count; i++) { 260 /* MALL SS messaging is not supported with PSR at this time */ 261 if (dc->current_state->streams[i] != NULL && 262 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) 263 return false; 264 } 265 266 if (enable) { 267 if (dc->current_state) { 268 269 /* 1. Check no memory request case for CAB. 270 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message 271 */ 272 if (dcn32_check_no_memory_request_for_cab(dc)) { 273 /* Enable no-memory-requests case */ 274 memset(&cmd, 0, sizeof(cmd)); 275 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 276 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ; 277 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 278 279 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 280 281 return true; 282 } 283 284 /* 2. Check if all surfaces can fit in CAB. 285 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message 286 * and configure HUBP's to fetch from MALL 287 */ 288 ways = dcn32_calculate_cab_allocation(dc, dc->current_state); 289 290 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo, 291 * or TMZ surface, don't try to enter MALL. 292 */ 293 for (i = 0; i < dc->current_state->stream_count; i++) { 294 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { 295 plane = dc->current_state->stream_status[i].plane_states[j]; 296 297 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO || 298 plane->address.tmz_surface) { 299 mall_ss_unsupported = true; 300 break; 301 } 302 } 303 if (mall_ss_unsupported) 304 break; 305 } 306 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) { 307 memset(&cmd, 0, sizeof(cmd)); 308 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 309 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB; 310 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header); 311 cmd.cab.cab_alloc_ways = (uint8_t)ways; 312 313 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 314 315 return true; 316 } 317 318 } 319 return false; 320 } 321 322 /* Disable CAB */ 323 memset(&cmd, 0, sizeof(cmd)); 324 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS; 325 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION; 326 cmd.cab.header.payload_bytes = 327 sizeof(cmd.cab) - sizeof(cmd.cab.header); 328 329 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 330 331 return true; 332} 333 334/* Send DMCUB message with SubVP pipe info 335 * - For each pipe in context, populate payload with required SubVP information 336 * if the pipe is using SubVP for MCLK switch 337 * - This function must be called while the DMUB HW lock is acquired by driver 338 */ 339void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context) 340{ 341 int i; 342 bool enable_subvp = false; 343 344 if (!dc->ctx || !dc->ctx->dmub_srv) 345 return; 346 347 for (i = 0; i < dc->res_pool->pipe_count; i++) { 348 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 349 350 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && 351 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { 352 // There is at least 1 SubVP pipe, so enable SubVP 353 enable_subvp = true; 354 break; 355 } 356 } 357 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp); 358} 359 360/* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and: 361 * 1. Any full update for any SubVP main pipe 362 * 2. Any immediate flip for any SubVP pipe 363 * 3. Any flip for DRR pipe 364 * 4. If SubVP was previously in use (i.e. in old context) 365 */ 366void dcn32_subvp_pipe_control_lock(struct dc *dc, 367 struct dc_state *context, 368 bool lock, 369 bool should_lock_all_pipes, 370 struct pipe_ctx *top_pipe_to_program, 371 bool subvp_prev_use) 372{ 373 unsigned int i = 0; 374 bool subvp_immediate_flip = false; 375 bool subvp_in_use = false; 376 struct pipe_ctx *pipe; 377 378 for (i = 0; i < dc->res_pool->pipe_count; i++) { 379 pipe = &context->res_ctx.pipe_ctx[i]; 380 381 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 382 subvp_in_use = true; 383 break; 384 } 385 } 386 387 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) { 388 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN && 389 top_pipe_to_program->plane_state->flip_immediate) 390 subvp_immediate_flip = true; 391 } 392 393 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 394 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) { 395 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 396 397 if (!lock) { 398 for (i = 0; i < dc->res_pool->pipe_count; i++) { 399 pipe = &context->res_ctx.pipe_ctx[i]; 400 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 401 should_lock_all_pipes) 402 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); 403 } 404 } 405 406 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 407 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 408 hw_lock_cmd.bits.lock = lock; 409 hw_lock_cmd.bits.should_release = !lock; 410 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 411 } 412} 413 414void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params) 415{ 416 struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc; 417 bool lock = params->subvp_pipe_control_lock_fast_params.lock; 418 struct pipe_ctx *pipe_ctx = params->subvp_pipe_control_lock_fast_params.pipe_ctx; 419 bool subvp_immediate_flip = false; 420 421 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->plane_state) { 422 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN && 423 pipe_ctx->plane_state->flip_immediate) 424 subvp_immediate_flip = true; 425 } 426 427 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared. 428 if (subvp_immediate_flip) { 429 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 430 431 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 432 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 433 hw_lock_cmd.bits.lock = lock; 434 hw_lock_cmd.bits.should_release = !lock; 435 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 436 } 437} 438 439bool dcn32_set_mpc_shaper_3dlut( 440 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 441{ 442 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 443 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 444 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 445 bool result = false; 446 447 const struct pwl_params *shaper_lut = NULL; 448 //get the shaper lut params 449 if (stream->func_shaper) { 450 if (stream->func_shaper->type == TF_TYPE_HWPWL) 451 shaper_lut = &stream->func_shaper->pwl; 452 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 453 cm_helper_translate_curve_to_hw_format(stream->ctx, 454 stream->func_shaper, 455 &dpp_base->shaper_params, true); 456 shaper_lut = &dpp_base->shaper_params; 457 } 458 } 459 460 if (stream->lut3d_func && 461 stream->lut3d_func->state.bits.initialized == 1) { 462 463 result = mpc->funcs->program_3dlut(mpc, 464 &stream->lut3d_func->lut_3d, 465 mpcc_id); 466 467 result = mpc->funcs->program_shaper(mpc, 468 shaper_lut, 469 mpcc_id); 470 } 471 472 return result; 473} 474 475bool dcn32_set_mcm_luts( 476 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 477{ 478 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 479 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 480 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 481 bool result = true; 482 struct pwl_params *lut_params = NULL; 483 484 // 1D LUT 485 if (plane_state->blend_tf) { 486 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 487 lut_params = &plane_state->blend_tf->pwl; 488 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 489 cm3_helper_translate_curve_to_hw_format(plane_state->blend_tf, 490 &dpp_base->regamma_params, false); 491 lut_params = &dpp_base->regamma_params; 492 } 493 } 494 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); 495 496 // Shaper 497 if (plane_state->in_shaper_func) { 498 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 499 lut_params = &plane_state->in_shaper_func->pwl; 500 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 501 // TODO: dpp_base replace 502 ASSERT(false); 503 cm3_helper_translate_curve_to_hw_format(plane_state->in_shaper_func, 504 &dpp_base->shaper_params, true); 505 lut_params = &dpp_base->shaper_params; 506 } 507 } 508 509 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); 510 511 // 3D 512 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1) 513 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); 514 else 515 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); 516 517 return result; 518} 519 520bool dcn32_set_input_transfer_func(struct dc *dc, 521 struct pipe_ctx *pipe_ctx, 522 const struct dc_plane_state *plane_state) 523{ 524 struct dce_hwseq *hws = dc->hwseq; 525 struct mpc *mpc = dc->res_pool->mpc; 526 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 527 528 enum dc_transfer_func_predefined tf; 529 bool result = true; 530 struct pwl_params *params = NULL; 531 532 if (mpc == NULL || plane_state == NULL) 533 return false; 534 535 tf = TRANSFER_FUNCTION_UNITY; 536 537 if (plane_state->in_transfer_func && 538 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 539 tf = plane_state->in_transfer_func->tf; 540 541 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 542 543 if (plane_state->in_transfer_func) { 544 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 545 params = &plane_state->in_transfer_func->pwl; 546 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 547 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 548 &dpp_base->degamma_params, false)) 549 params = &dpp_base->degamma_params; 550 } 551 552 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 553 554 if (pipe_ctx->stream_res.opp && 555 pipe_ctx->stream_res.opp->ctx && 556 hws->funcs.set_mcm_luts) 557 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state); 558 559 return result; 560} 561 562bool dcn32_set_output_transfer_func(struct dc *dc, 563 struct pipe_ctx *pipe_ctx, 564 const struct dc_stream_state *stream) 565{ 566 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 567 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 568 struct pwl_params *params = NULL; 569 bool ret = false; 570 571 /* program OGAM or 3DLUT only for the top pipe*/ 572 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) { 573 /*program shaper and 3dlut in MPC*/ 574 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream); 575 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 576 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 577 params = &stream->out_transfer_func->pwl; 578 else if (pipe_ctx->stream->out_transfer_func->type == 579 TF_TYPE_DISTRIBUTED_POINTS && 580 cm3_helper_translate_curve_to_hw_format( 581 stream->out_transfer_func, 582 &mpc->blender_params, false)) 583 params = &mpc->blender_params; 584 /* there are no ROM LUTs in OUTGAM */ 585 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 586 BREAK_TO_DEBUGGER(); 587 } 588 } 589 590 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 591 return ret; 592} 593 594/* Program P-State force value according to if pipe is using SubVP / FPO or not: 595 * 1. Reset P-State force on all pipes first 596 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB) 597 */ 598void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context) 599{ 600 int i; 601 602 /* Unforce p-state for each pipe if it is not FPO or SubVP. 603 * For FPO and SubVP, if it's already forced disallow, leave 604 * it as disallow. 605 */ 606 for (i = 0; i < dc->res_pool->pipe_count; i++) { 607 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 608 struct hubp *hubp = pipe->plane_res.hubp; 609 610 if (!pipe->stream || !(pipe->stream->mall_stream_config.type == SUBVP_MAIN || 611 pipe->stream->fpo_in_use)) { 612 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 613 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 614 } 615 616 /* Today only FPO uses cursor P-State force. Only clear cursor P-State force 617 * if it's not FPO. 618 */ 619 if (!pipe->stream || !pipe->stream->fpo_in_use) { 620 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 621 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false); 622 } 623 } 624 625 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false. 626 */ 627 for (i = 0; i < dc->res_pool->pipe_count; i++) { 628 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 629 struct hubp *hubp = pipe->plane_res.hubp; 630 631 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 632 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 633 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 634 } 635 636 if (pipe->stream && pipe->stream->fpo_in_use) { 637 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 638 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 639 /* For now only force cursor p-state disallow for FPO 640 * Needs to be added for subvp once FW side gets updated 641 */ 642 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 643 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true); 644 } 645 } 646} 647 648/* Update MALL_SEL register based on if pipe / plane 649 * is a phantom pipe, main pipe, and if using MALL 650 * for SS. 651 */ 652void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 653{ 654 int i; 655 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context); 656 bool cache_cursor = false; 657 658 for (i = 0; i < dc->res_pool->pipe_count; i++) { 659 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 660 struct hubp *hubp = pipe->plane_res.hubp; 661 662 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { 663 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; 664 665 switch (hubp->curs_attr.color_format) { 666 case CURSOR_MODE_MONO: 667 cursor_size /= 2; 668 break; 669 case CURSOR_MODE_COLOR_1BIT_AND: 670 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 671 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 672 cursor_size *= 4; 673 break; 674 675 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 676 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 677 default: 678 cursor_size *= 8; 679 break; 680 } 681 682 if (cursor_size > 16384) 683 cache_cursor = true; 684 685 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 686 hubp->funcs->hubp_update_mall_sel(hubp, 1, false); 687 } else { 688 // MALL not supported with Stereo3D 689 hubp->funcs->hubp_update_mall_sel(hubp, 690 num_ways <= dc->caps.cache_num_ways && 691 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 692 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && 693 !pipe->plane_state->address.tmz_surface ? 2 : 0, 694 cache_cursor); 695 } 696 } 697 } 698} 699 700/* Program the sub-viewport pipe configuration after the main / phantom pipes 701 * have been programmed in hardware. 702 * 1. Update force P-State for all the main pipes (disallow P-state) 703 * 2. Update MALL_SEL register 704 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes 705 */ 706void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context) 707{ 708 int i; 709 struct dce_hwseq *hws = dc->hwseq; 710 711 // Don't force p-state disallow -- can't block dummy p-state 712 713 // Update MALL_SEL register for each pipe 714 if (hws && hws->funcs.update_mall_sel) 715 hws->funcs.update_mall_sel(dc, context); 716 717 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes 718 for (i = 0; i < dc->res_pool->pipe_count; i++) { 719 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 720 struct hubp *hubp = pipe->plane_res.hubp; 721 722 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { 723 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases 724 * - need to investigate single pipe MPO + SubVP case to 725 * see if CURSOR_REQ_MODE will be back to 1 for SubVP 726 * when it should be 0 for MPO 727 */ 728 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 729 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true); 730 } 731 } 732 } 733} 734 735static void dcn32_initialize_min_clocks(struct dc *dc) 736{ 737 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; 738 739 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; 740 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; 741 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; 742 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; 743 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; 744 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; 745 clocks->fclk_p_state_change_support = true; 746 clocks->p_state_change_support = true; 747 if (dc->debug.disable_boot_optimizations) { 748 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; 749 } else { 750 /* Even though DPG_EN = 1 for the connected display, it still requires the 751 * correct timing so we cannot set DISPCLK to min freq or it could cause 752 * audio corruption. Read current DISPCLK from DENTIST and request the same 753 * freq to ensure that the timing is valid and unchanged. 754 */ 755 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); 756 } 757 758 dc->clk_mgr->funcs->update_clocks( 759 dc->clk_mgr, 760 dc->current_state, 761 true); 762} 763 764void dcn32_init_hw(struct dc *dc) 765{ 766 struct abm **abms = dc->res_pool->multiple_abms; 767 struct dce_hwseq *hws = dc->hwseq; 768 struct dc_bios *dcb = dc->ctx->dc_bios; 769 struct resource_pool *res_pool = dc->res_pool; 770 int i; 771 int edp_num; 772 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 773 774 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 775 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 776 777 // Initialize the dccg 778 if (res_pool->dccg->funcs->dccg_init) 779 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 780 781 if (!dcb->funcs->is_accelerated_mode(dcb)) { 782 hws->funcs.bios_golden_init(dc); 783 hws->funcs.disable_vga(dc->hwseq); 784 } 785 786 // Set default OPTC memory power states 787 if (dc->debug.enable_mem_low_power.bits.optc) { 788 // Shutdown when unassigned and light sleep in VBLANK 789 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 790 } 791 792 if (dc->debug.enable_mem_low_power.bits.vga) { 793 // Power down VGA memory 794 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 795 } 796 797 if (dc->ctx->dc_bios->fw_info_valid) { 798 res_pool->ref_clocks.xtalin_clock_inKhz = 799 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 800 801 if (res_pool->dccg && res_pool->hubbub) { 802 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 803 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 804 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 805 806 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 807 res_pool->ref_clocks.dccg_ref_clock_inKhz, 808 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 809 } else { 810 // Not all ASICs have DCCG sw component 811 res_pool->ref_clocks.dccg_ref_clock_inKhz = 812 res_pool->ref_clocks.xtalin_clock_inKhz; 813 res_pool->ref_clocks.dchub_ref_clock_inKhz = 814 res_pool->ref_clocks.xtalin_clock_inKhz; 815 } 816 } else 817 ASSERT_CRITICAL(false); 818 819 for (i = 0; i < dc->link_count; i++) { 820 /* Power up AND update implementation according to the 821 * required signal (which may be different from the 822 * default signal on connector). 823 */ 824 struct dc_link *link = dc->links[i]; 825 826 link->link_enc->funcs->hw_init(link->link_enc); 827 828 /* Check for enabled DIG to identify enabled display */ 829 if (link->link_enc->funcs->is_dig_enabled && 830 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 831 link->link_status.link_active = true; 832 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 833 if (link->link_enc->funcs->fec_is_active && 834 link->link_enc->funcs->fec_is_active(link->link_enc)) 835 link->fec_state = dc_link_fec_enabled; 836 } 837 } 838 839 /* enable_power_gating_plane before dsc_pg_control because 840 * FORCEON = 1 with hw default value on bootup, resume from s3 841 */ 842 if (hws->funcs.enable_power_gating_plane) 843 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 844 845 /* we want to turn off all dp displays before doing detection */ 846 dc->link_srv->blank_all_dp_displays(dc); 847 848 /* If taking control over from VBIOS, we may want to optimize our first 849 * mode set, so we need to skip powering down pipes until we know which 850 * pipes we want to use. 851 * Otherwise, if taking control is not possible, we need to power 852 * everything down. 853 */ 854 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 855 /* Disable boot optimizations means power down everything including PHY, DIG, 856 * and OTG (i.e. the boot is not optimized because we do a full power down). 857 */ 858 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations) 859 dc->hwss.enable_accelerated_mode(dc, dc->current_state); 860 else 861 hws->funcs.init_pipes(dc, dc->current_state); 862 863 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 864 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 865 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 866 867 dcn32_initialize_min_clocks(dc); 868 869 /* On HW init, allow idle optimizations after pipes have been turned off. 870 * 871 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state 872 * is reset (i.e. not in idle at the time hw init is called), but software state 873 * still has idle_optimizations = true, so we must disable idle optimizations first 874 * (i.e. set false), then re-enable (set true). 875 */ 876 dc_allow_idle_optimizations(dc, false); 877 dc_allow_idle_optimizations(dc, true); 878 } 879 880 /* In headless boot cases, DIG may be turned 881 * on which causes HW/SW discrepancies. 882 * To avoid this, power down hardware on boot 883 * if DIG is turned on and seamless boot not enabled 884 */ 885 if (!dc->config.seamless_boot_edp_requested) { 886 struct dc_link *edp_links[MAX_NUM_EDP]; 887 struct dc_link *edp_link; 888 889 dc_get_edp_links(dc, edp_links, &edp_num); 890 if (edp_num) { 891 for (i = 0; i < edp_num; i++) { 892 edp_link = edp_links[i]; 893 if (edp_link->link_enc->funcs->is_dig_enabled && 894 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 895 dc->hwss.edp_backlight_control && 896 dc->hwss.power_down && 897 dc->hwss.edp_power_control) { 898 dc->hwss.edp_backlight_control(edp_link, false); 899 dc->hwss.power_down(dc); 900 dc->hwss.edp_power_control(edp_link, false); 901 } 902 } 903 } else { 904 for (i = 0; i < dc->link_count; i++) { 905 struct dc_link *link = dc->links[i]; 906 907 if (link->link_enc->funcs->is_dig_enabled && 908 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 909 dc->hwss.power_down) { 910 dc->hwss.power_down(dc); 911 break; 912 } 913 914 } 915 } 916 } 917 918 for (i = 0; i < res_pool->audio_count; i++) { 919 struct audio *audio = res_pool->audios[i]; 920 921 audio->funcs->hw_init(audio); 922 } 923 924 for (i = 0; i < dc->link_count; i++) { 925 struct dc_link *link = dc->links[i]; 926 927 if (link->panel_cntl) 928 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 929 } 930 931 for (i = 0; i < dc->res_pool->pipe_count; i++) { 932 if (abms[i] != NULL && abms[i]->funcs != NULL) 933 abms[i]->funcs->abm_init(abms[i], backlight); 934 } 935 936 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 937 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 938 939 if (!dc->debug.disable_clock_gate) { 940 /* enable all DCN clock gating */ 941 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 942 943 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 944 945 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 946 } 947 948 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 949 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 950 951 if (dc->clk_mgr->funcs->notify_wm_ranges) 952 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 953 954 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) 955 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 956 957 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 958 dc->res_pool->hubbub->funcs->force_pstate_change_control( 959 dc->res_pool->hubbub, false, false); 960 961 if (dc->res_pool->hubbub->funcs->init_crb) 962 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 963 964 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0) 965 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc); 966 967 // Get DMCUB capabilities 968 if (dc->ctx->dmub_srv) { 969 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); 970 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 971 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support; 972 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable; 973 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; 974 } 975} 976 977static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 978 int opp_cnt) 979{ 980 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 981 int flow_ctrl_cnt; 982 983 if (opp_cnt >= 2) 984 hblank_halved = true; 985 986 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 987 stream->timing.h_border_left - 988 stream->timing.h_border_right; 989 990 if (hblank_halved) 991 flow_ctrl_cnt /= 2; 992 993 /* ODM combine 4:1 case */ 994 if (opp_cnt == 4) 995 flow_ctrl_cnt /= 2; 996 997 return flow_ctrl_cnt; 998} 999 1000static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 1001{ 1002 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1003 struct dc_stream_state *stream = pipe_ctx->stream; 1004 struct pipe_ctx *odm_pipe; 1005 int opp_cnt = 1; 1006 1007 ASSERT(dsc); 1008 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1009 opp_cnt++; 1010 1011 if (enable) { 1012 struct dsc_config dsc_cfg; 1013 struct dsc_optc_config dsc_optc_cfg; 1014 enum optc_dsc_mode optc_dsc_mode; 1015 1016 /* Enable DSC hw block */ 1017 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1018 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 1019 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1020 dsc_cfg.color_depth = stream->timing.display_color_depth; 1021 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1022 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1023 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1024 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1025 1026 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 1027 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 1028 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1029 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 1030 1031 ASSERT(odm_dsc); 1032 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 1033 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 1034 } 1035 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 1036 dsc_cfg.pic_width *= opp_cnt; 1037 1038 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 1039 1040 /* Enable DSC in OPTC */ 1041 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 1042 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 1043 optc_dsc_mode, 1044 dsc_optc_cfg.bytes_per_pixel, 1045 dsc_optc_cfg.slice_width); 1046 } else { 1047 /* disable DSC in OPTC */ 1048 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 1049 pipe_ctx->stream_res.tg, 1050 OPTC_DSC_DISABLED, 0, 0); 1051 1052 /* disable DSC block */ 1053 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); 1054 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1055 ASSERT(odm_pipe->stream_res.dsc); 1056 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 1057 } 1058 } 1059} 1060 1061/* 1062* Given any pipe_ctx, return the total ODM combine factor, and optionally return 1063* the OPPids which are used 1064* */ 1065static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) 1066{ 1067 unsigned int opp_count = 1; 1068 struct pipe_ctx *odm_pipe; 1069 1070 /* First get to the top pipe */ 1071 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe) 1072 ; 1073 1074 /* First pipe is always used */ 1075 if (opp_instances) 1076 opp_instances[0] = odm_pipe->stream_res.opp->inst; 1077 1078 /* Find and count odm pipes, if any */ 1079 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1080 if (opp_instances) 1081 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst; 1082 opp_count++; 1083 } 1084 1085 return opp_count; 1086} 1087 1088void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1089{ 1090 struct pipe_ctx *odm_pipe; 1091 int opp_cnt = 0; 1092 int opp_inst[MAX_PIPES] = {0}; 1093 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing)); 1094 struct mpc_dwb_flow_control flow_control; 1095 struct mpc *mpc = dc->res_pool->mpc; 1096 int i; 1097 1098 opp_cnt = get_odm_config(pipe_ctx, opp_inst); 1099 1100 if (opp_cnt > 1) 1101 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1102 pipe_ctx->stream_res.tg, 1103 opp_inst, opp_cnt, 1104 &pipe_ctx->stream->timing); 1105 else 1106 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1107 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1108 1109 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 1110 flow_control.flow_ctrl_mode = 0; 1111 flow_control.flow_ctrl_cnt0 = 0x80; 1112 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt); 1113 if (mpc->funcs->set_out_rate_control) { 1114 for (i = 0; i < opp_cnt; ++i) { 1115 mpc->funcs->set_out_rate_control( 1116 mpc, opp_inst[i], 1117 true, 1118 rate_control_2x_pclk, 1119 &flow_control); 1120 } 1121 } 1122 1123 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1124 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 1125 odm_pipe->stream_res.opp, 1126 true); 1127 } 1128 1129 if (pipe_ctx->stream_res.dsc) { 1130 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 1131 1132 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 1133 1134 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 1135 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe && 1136 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { 1137 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc; 1138 /* disconnect DSC block from stream */ 1139 dsc->funcs->dsc_disconnect(dsc); 1140 } 1141 } 1142} 1143 1144unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div) 1145{ 1146 struct dc_stream_state *stream = pipe_ctx->stream; 1147 unsigned int odm_combine_factor = 0; 1148 bool two_pix_per_container = false; 1149 1150 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); 1151 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1152 1153 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1154 *k1_div = PIXEL_RATE_DIV_BY_1; 1155 *k2_div = PIXEL_RATE_DIV_BY_1; 1156 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) { 1157 *k1_div = PIXEL_RATE_DIV_BY_1; 1158 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1159 *k2_div = PIXEL_RATE_DIV_BY_2; 1160 else 1161 *k2_div = PIXEL_RATE_DIV_BY_4; 1162 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) { 1163 if (two_pix_per_container) { 1164 *k1_div = PIXEL_RATE_DIV_BY_1; 1165 *k2_div = PIXEL_RATE_DIV_BY_2; 1166 } else { 1167 *k1_div = PIXEL_RATE_DIV_BY_1; 1168 *k2_div = PIXEL_RATE_DIV_BY_4; 1169 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1170 *k2_div = PIXEL_RATE_DIV_BY_2; 1171 } 1172 } 1173 1174 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) 1175 ASSERT(false); 1176 1177 return odm_combine_factor; 1178} 1179 1180void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 1181{ 1182 uint32_t pix_per_cycle = 1; 1183 uint32_t odm_combine_factor = 1; 1184 1185 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) 1186 return; 1187 1188 odm_combine_factor = get_odm_config(pipe_ctx, NULL); 1189 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 1190 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1191 pix_per_cycle = 2; 1192 1193 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) 1194 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, 1195 pix_per_cycle); 1196} 1197 1198void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context) 1199{ 1200 unsigned int i; 1201 struct pipe_ctx *pipe = NULL; 1202 bool otg_disabled[MAX_PIPES] = {false}; 1203 1204 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1205 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1206 1207 if (!resource_is_pipe_type(pipe, OTG_MASTER)) 1208 continue; 1209 1210 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) 1211 && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1212 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); 1213 reset_sync_context_for_pipe(dc, context, i); 1214 otg_disabled[i] = true; 1215 } 1216 } 1217 1218 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); 1219 1220 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1221 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1222 1223 if (otg_disabled[i]) 1224 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 1225 } 1226} 1227 1228void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, 1229 struct dc_link_settings *link_settings) 1230{ 1231 struct encoder_unblank_param params = {0}; 1232 struct dc_stream_state *stream = pipe_ctx->stream; 1233 struct dc_link *link = stream->link; 1234 struct dce_hwseq *hws = link->dc->hwseq; 1235 struct pipe_ctx *odm_pipe; 1236 uint32_t pix_per_cycle = 1; 1237 1238 params.opp_cnt = 1; 1239 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1240 params.opp_cnt++; 1241 1242 /* only 3 items below are used by unblank */ 1243 params.timing = pipe_ctx->stream->timing; 1244 1245 params.link_settings.link_rate = link_settings->link_rate; 1246 1247 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1248 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1249 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 1250 pipe_ctx->stream_res.hpo_dp_stream_enc, 1251 pipe_ctx->stream_res.tg->inst); 1252 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1253 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1 1254 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 1255 params.timing.pix_clk_100hz /= 2; 1256 pix_per_cycle = 2; 1257 } 1258 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1259 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1); 1260 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1261 } 1262 1263 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 1264 hws->funcs.edp_backlight_control(link, true); 1265} 1266 1267bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) 1268{ 1269 struct dc *dc = pipe_ctx->stream->ctx->dc; 1270 1271 if (!is_h_timing_divisible_by_2(pipe_ctx->stream)) 1272 return false; 1273 1274 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && 1275 dc->debug.enable_dp_dig_pixel_rate_div_policy) 1276 return true; 1277 return false; 1278} 1279 1280static void apply_symclk_on_tx_off_wa(struct dc_link *link) 1281{ 1282 /* There are use cases where SYMCLK is referenced by OTG. For instance 1283 * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 1284 * However current link interface will power off PHY when disabling link 1285 * output. This will turn off SYMCLK generated by PHY. The workaround is 1286 * to identify such case where SYMCLK is still in use by OTG when we 1287 * power off PHY. When this is detected, we will temporarily power PHY 1288 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 1289 * program_pix_clk interface. When OTG is disabled, we will then power 1290 * off PHY by calling disable link output again. 1291 * 1292 * In future dcn generations, we plan to rework transmitter control 1293 * interface so that we could have an option to set SYMCLK ON TX OFF 1294 * state in one step without this workaround 1295 */ 1296 1297 struct dc *dc = link->ctx->dc; 1298 struct pipe_ctx *pipe_ctx = NULL; 1299 uint8_t i; 1300 1301 if (link->phy_state.symclk_ref_cnts.otg > 0) { 1302 for (i = 0; i < MAX_PIPES; i++) { 1303 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1304 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) { 1305 pipe_ctx->clock_source->funcs->program_pix_clk( 1306 pipe_ctx->clock_source, 1307 &pipe_ctx->stream_res.pix_clk_params, 1308 dc->link_srv->dp_get_encoding_format( 1309 &pipe_ctx->link_config.dp_link_settings), 1310 &pipe_ctx->pll_settings); 1311 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1312 break; 1313 } 1314 } 1315 } 1316} 1317 1318void dcn32_disable_link_output(struct dc_link *link, 1319 const struct link_resource *link_res, 1320 enum amd_signal_type signal) 1321{ 1322 struct dc *dc = link->ctx->dc; 1323 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1324 struct dmcu *dmcu = dc->res_pool->dmcu; 1325 1326 if (signal == SIGNAL_TYPE_EDP && 1327 link->dc->hwss.edp_backlight_control) 1328 link->dc->hwss.edp_backlight_control(link, false); 1329 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1330 dmcu->funcs->lock_phy(dmcu); 1331 1332 link_hwss->disable_link_output(link, link_res, signal); 1333 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1334 1335 if (signal == SIGNAL_TYPE_EDP && 1336 link->dc->hwss.edp_backlight_control) 1337 link->dc->hwss.edp_power_control(link, false); 1338 else if (dmcu != NULL && dmcu->funcs->lock_phy) 1339 dmcu->funcs->unlock_phy(dmcu); 1340 1341 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1342 1343 apply_symclk_on_tx_off_wa(link); 1344} 1345 1346/* For SubVP the main pipe can have a viewport position change 1347 * without a full update. In this case we must also update the 1348 * viewport positions for the phantom pipe accordingly. 1349 */ 1350void dcn32_update_phantom_vp_position(struct dc *dc, 1351 struct dc_state *context, 1352 struct pipe_ctx *phantom_pipe) 1353{ 1354 uint32_t i; 1355 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state; 1356 1357 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1358 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1359 1360 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN && 1361 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) { 1362 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) { 1363 1364 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x; 1365 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y; 1366 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x; 1367 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x; 1368 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y; 1369 1370 phantom_pipe->plane_state->update_flags.bits.position_change = 1; 1371 resource_build_scaling_params(phantom_pipe); 1372 return; 1373 } 1374 } 1375 } 1376} 1377 1378/* Treat the phantom pipe as if it needs to be fully enabled. 1379 * If the pipe was previously in use but not phantom, it would 1380 * have been disabled earlier in the sequence so we need to run 1381 * the full enable sequence. 1382 */ 1383void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe) 1384{ 1385 phantom_pipe->update_flags.raw = 0; 1386 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1387 if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) { 1388 phantom_pipe->update_flags.bits.enable = 1; 1389 phantom_pipe->update_flags.bits.mpcc = 1; 1390 phantom_pipe->update_flags.bits.dppclk = 1; 1391 phantom_pipe->update_flags.bits.hubp_interdependent = 1; 1392 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1393 phantom_pipe->update_flags.bits.gamut_remap = 1; 1394 phantom_pipe->update_flags.bits.scaler = 1; 1395 phantom_pipe->update_flags.bits.viewport = 1; 1396 phantom_pipe->update_flags.bits.det_size = 1; 1397 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) { 1398 phantom_pipe->update_flags.bits.odm = 1; 1399 phantom_pipe->update_flags.bits.global_sync = 1; 1400 } 1401 } 1402 } 1403} 1404 1405bool dcn32_dsc_pg_status( 1406 struct dce_hwseq *hws, 1407 unsigned int dsc_inst) 1408{ 1409 uint32_t pwr_status = 0; 1410 1411 switch (dsc_inst) { 1412 case 0: /* DSC0 */ 1413 REG_GET(DOMAIN16_PG_STATUS, 1414 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1415 break; 1416 case 1: /* DSC1 */ 1417 1418 REG_GET(DOMAIN17_PG_STATUS, 1419 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1420 break; 1421 case 2: /* DSC2 */ 1422 REG_GET(DOMAIN18_PG_STATUS, 1423 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1424 break; 1425 case 3: /* DSC3 */ 1426 REG_GET(DOMAIN19_PG_STATUS, 1427 DOMAIN_PGFSM_PWR_STATUS, &pwr_status); 1428 break; 1429 default: 1430 BREAK_TO_DEBUGGER(); 1431 break; 1432 } 1433 1434 return pwr_status == 0; 1435} 1436 1437void dcn32_update_dsc_pg(struct dc *dc, 1438 struct dc_state *context, 1439 bool safe_to_disable) 1440{ 1441 struct dce_hwseq *hws = dc->hwseq; 1442 int i; 1443 1444 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 1445 struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; 1446 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); 1447 1448 if (context->res_ctx.is_dsc_acquired[i]) { 1449 if (!is_dsc_ungated) { 1450 hws->funcs.dsc_pg_control(hws, dsc->inst, true); 1451 } 1452 } else if (safe_to_disable) { 1453 if (is_dsc_ungated) { 1454 hws->funcs.dsc_pg_control(hws, dsc->inst, false); 1455 } 1456 } 1457 } 1458} 1459 1460void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context) 1461{ 1462 unsigned int i; 1463 1464 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1465 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1466 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1467 1468 /* If an active, non-phantom pipe is being transitioned into a phantom 1469 * pipe, wait for the double buffer update to complete first before we do 1470 * ANY phantom pipe programming. 1471 */ 1472 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && 1473 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1474 old_pipe->stream_res.tg->funcs->wait_for_state( 1475 old_pipe->stream_res.tg, 1476 CRTC_STATE_VBLANK); 1477 old_pipe->stream_res.tg->funcs->wait_for_state( 1478 old_pipe->stream_res.tg, 1479 CRTC_STATE_VACTIVE); 1480 } 1481 } 1482 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1483 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 1484 1485 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1486 // If old context or new context has phantom pipes, apply 1487 // the phantom timings now. We can't change the phantom 1488 // pipe configuration safely without driver acquiring 1489 // the DMCUB lock first. 1490 dc->hwss.apply_ctx_to_hw(dc, context); 1491 break; 1492 } 1493 } 1494} 1495 1496/* Blank pixel data during initialization */ 1497void dcn32_init_blank( 1498 struct dc *dc, 1499 struct timing_generator *tg) 1500{ 1501 struct dce_hwseq *hws = dc->hwseq; 1502 enum dc_color_space color_space; 1503 struct tg_color black_color = {0}; 1504 struct output_pixel_processor *opp = NULL; 1505 struct output_pixel_processor *bottom_opp = NULL; 1506 uint32_t num_opps, opp_id_src0, opp_id_src1; 1507 uint32_t otg_active_width, otg_active_height; 1508 uint32_t i; 1509 1510 /* program opp dpg blank color */ 1511 color_space = COLOR_SPACE_SRGB; 1512 color_space_to_black_color(dc, color_space, &black_color); 1513 1514 /* get the OTG active size */ 1515 tg->funcs->get_otg_active_size(tg, 1516 &otg_active_width, 1517 &otg_active_height); 1518 1519 /* get the OPTC source */ 1520 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 1521 1522 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 1523 ASSERT(false); 1524 return; 1525 } 1526 1527 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1528 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { 1529 opp = dc->res_pool->opps[i]; 1530 break; 1531 } 1532 } 1533 1534 if (num_opps == 2) { 1535 otg_active_width = otg_active_width / 2; 1536 1537 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 1538 ASSERT(false); 1539 return; 1540 } 1541 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1542 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) { 1543 bottom_opp = dc->res_pool->opps[i]; 1544 break; 1545 } 1546 } 1547 } 1548 1549 if (opp && opp->funcs->opp_set_disp_pattern_generator) 1550 opp->funcs->opp_set_disp_pattern_generator( 1551 opp, 1552 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1553 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1554 COLOR_DEPTH_UNDEFINED, 1555 &black_color, 1556 otg_active_width, 1557 otg_active_height, 1558 0); 1559 1560 if (num_opps == 2) { 1561 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) { 1562 bottom_opp->funcs->opp_set_disp_pattern_generator( 1563 bottom_opp, 1564 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1565 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1566 COLOR_DEPTH_UNDEFINED, 1567 &black_color, 1568 otg_active_width, 1569 otg_active_height, 1570 0); 1571 hws->funcs.wait_for_blank_complete(bottom_opp); 1572 } 1573 } 1574 1575 if (opp) 1576 hws->funcs.wait_for_blank_complete(opp); 1577} 1578 1579void dcn32_blank_phantom(struct dc *dc, 1580 struct timing_generator *tg, 1581 int width, 1582 int height) 1583{ 1584 struct dce_hwseq *hws = dc->hwseq; 1585 enum dc_color_space color_space; 1586 struct tg_color black_color = {0}; 1587 struct output_pixel_processor *opp = NULL; 1588 uint32_t num_opps, opp_id_src0, opp_id_src1; 1589 uint32_t otg_active_width, otg_active_height; 1590 uint32_t i; 1591 1592 /* program opp dpg blank color */ 1593 color_space = COLOR_SPACE_SRGB; 1594 color_space_to_black_color(dc, color_space, &black_color); 1595 1596 otg_active_width = width; 1597 otg_active_height = height; 1598 1599 /* get the OPTC source */ 1600 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 1601 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); 1602 1603 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 1604 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { 1605 opp = dc->res_pool->opps[i]; 1606 break; 1607 } 1608 } 1609 1610 if (opp && opp->funcs->opp_set_disp_pattern_generator) 1611 opp->funcs->opp_set_disp_pattern_generator( 1612 opp, 1613 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 1614 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1615 COLOR_DEPTH_UNDEFINED, 1616 &black_color, 1617 otg_active_width, 1618 otg_active_height, 1619 0); 1620 1621 if (tg->funcs->is_tg_enabled(tg)) 1622 hws->funcs.wait_for_blank_complete(opp); 1623} 1624 1625bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, 1626 const struct dc_state *cur_ctx, 1627 const struct dc_state *new_ctx) 1628{ 1629 int i; 1630 const struct pipe_ctx *cur_pipe, *new_pipe; 1631 bool is_seamless = true; 1632 1633 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1634 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i]; 1635 new_pipe = &new_ctx->res_ctx.pipe_ctx[i]; 1636 1637 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) || 1638 resource_is_pipe_type(new_pipe, FREE_PIPE)) 1639 /* adding or removing free pipes is always seamless */ 1640 continue; 1641 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) { 1642 if (resource_is_pipe_type(new_pipe, OTG_MASTER)) 1643 if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id) 1644 /* OTG master with the same stream is seamless */ 1645 continue; 1646 } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) { 1647 if (resource_is_pipe_type(new_pipe, OPP_HEAD)) { 1648 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg) 1649 /* 1650 * OPP heads sharing the same timing 1651 * generator is seamless 1652 */ 1653 continue; 1654 } 1655 } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) { 1656 if (resource_is_pipe_type(new_pipe, DPP_PIPE)) { 1657 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp) 1658 /* 1659 * DPP pipes sharing the same OPP head is 1660 * seamless 1661 */ 1662 continue; 1663 } 1664 } 1665 1666 /* 1667 * This pipe's transition doesn't fall under any seamless 1668 * conditions 1669 */ 1670 is_seamless = false; 1671 break; 1672 } 1673 1674 return is_seamless; 1675} 1676