dc/dce/dce_clock_source.c

180  * @pll_settings:	Pointer to PLL settings
193 		struct pll_settings *pll_settings,
206 			pll_settings->adjusted_pix_clk_100hz,
225 					pll_settings->adjusted_pix_clk_100hz)
227 					pll_settings->adjusted_pix_clk_100hz
228 			: pll_settings->adjusted_pix_clk_100hz -
233 		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
234 		pll_settings->reference_divider = ref_divider;
235 		pll_settings->feedback_divider = feedback_divider;
236 		pll_settings->fract_feedback_divider = fract_feedback_divider;
237 		pll_settings->pix_clk_post_divider = post_divider;
238 		pll_settings->calculated_pix_clk_100hz =
240 		pll_settings->vco_freq =
249 		struct pll_settings *pll_settings,
262 	tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
277 					pll_settings,
291 		struct pll_settings *pll_settings)
299 	if (pll_settings->adjusted_pix_clk_100hz == 0) {
306 	if (pll_settings->pix_clk_post_divider) {
307 		min_post_divider = pll_settings->pix_clk_post_divider;
308 		max_post_divider = pll_settings->pix_clk_post_divider;
311 		if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
314 					pll_settings->adjusted_pix_clk_100hz;
316 					pll_settings->adjusted_pix_clk_100hz) <
322 		if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
325 					pll_settings->adjusted_pix_clk_100hz;
330  * pll_settings->referenceDivider is not zero.
334 	if (pll_settings->reference_divider) {
335 		min_ref_divider = pll_settings->reference_divider;
336 		max_ref_divider = pll_settings->reference_divider;
379 			pll_settings,
395 		struct pll_settings *pll_settings)
446 		pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
447 		pll_settings->adjusted_pix_clk_100hz =
449 		pll_settings->reference_divider =
451 		pll_settings->pix_clk_post_divider =
473 		struct pll_settings *pll_settings,
484 	pll_settings->use_external_clk = (field > 1);
495 					pll_settings->adjusted_pix_clk_100hz / 10);
498 			pll_settings->ss_percentage = ss_data->percentage;
502 	if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
507 		pll_settings->actual_pix_clk_100hz =
509 		pll_settings->adjusted_pix_clk_100hz =
513 			pll_settings->adjusted_pix_clk_100hz = 1000000;
522 					pll_settings);
528 					pll_settings);
535 		struct pll_settings *pll_settings,
559 	pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
560 	pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
561 	pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
567 		struct pll_settings *pll_settings)
573 	if (pix_clk_params == NULL || pll_settings == NULL
580 	memset(pll_settings, 0, sizeof(*pll_settings));
584 		pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
585 		pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
586 		pll_settings->actual_pix_clk_100hz =
592 			pll_settings, pix_clk_params);
600 		struct pll_settings *pll_settings)
605 	if (pix_clk_params == NULL || pll_settings == NULL
612 	memset(pll_settings, 0, sizeof(*pll_settings));
616 		pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
617 		pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
618 		pll_settings->actual_pix_clk_100hz =
624 			pll_settings, pix_clk_params);
646 		const struct pll_settings *pll_settings,
663 	if (pll_settings == NULL)
671 		pll_settings->fract_feedback_divider, 1000000);
672 	fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
694 		pll_settings->reference_freq * 1000,
695 		pll_settings->reference_divider * ss_data->modulation_freq_hz);
712 		enum amd_signal_type signal, struct pll_settings *pll_settings)
721 			pll_settings->calculated_pix_clk_100hz / 10);
726 	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
727 		if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
844 		struct pll_settings *pll_settings)
861 	bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
865 	bp_pc_params.reference_divider = pll_settings->reference_divider;
866 	bp_pc_params.feedback_divider = pll_settings->feedback_divider;
868 			pll_settings->fract_feedback_divider;
870 			pll_settings->pix_clk_post_divider;
872 					pll_settings->use_external_clk;
902 							pll_settings))
918 		struct pll_settings *pll_settings)
935 	bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
941 						pll_settings->use_external_clk;
943 						!pll_settings->use_external_clk;
965 		struct pll_settings *pll_settings)
982 			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1007 		bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
1035 							pll_settings->use_external_clk;
1037 							!pll_settings->use_external_clk;
1171 		struct pll_settings *pll_settings)
1176 	dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1217 		struct pll_settings *pll_settings)
1233 			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1246 		dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1254 		struct pll_settings *pll_settings)
1260 	if (pix_clk_params == NULL || pll_settings == NULL
1267 	memset(pll_settings, 0, sizeof(*pll_settings));
1284 	pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1285 	pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1286 	pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;