1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef _CORE_TYPES_H_ 27#define _CORE_TYPES_H_ 28 29#include "dc.h" 30#include "dce_calcs.h" 31#include "dcn_calcs.h" 32#include "ddc_service_types.h" 33#include "dc_bios_types.h" 34#include "mem_input.h" 35#include "hubp.h" 36#include "mpc.h" 37#include "dwb.h" 38#include "mcif_wb.h" 39#include "panel_cntl.h" 40#include "dmub/inc/dmub_cmd.h" 41 42#define MAX_CLOCK_SOURCES 7 43#define MAX_SVP_PHANTOM_STREAMS 2 44#define MAX_SVP_PHANTOM_PLANES 2 45 46void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 47 uint32_t controller_id); 48 49#include "grph_object_id.h" 50#include "link_encoder.h" 51#include "stream_encoder.h" 52#include "clock_source.h" 53#include <hw/audio.h> 54#include "dm_pp_smu.h" 55#include "dm_cp_psp.h" 56#include "link_hwss.h" 57 58/********** DAL Core*********************/ 59#include "transform.h" 60#include "dpp.h" 61 62struct resource_pool; 63struct dc_state; 64struct resource_context; 65struct clk_bw_params; 66 67struct resource_funcs { 68 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 69 void (*destroy)(struct resource_pool **pool); 70 void (*link_init)(struct dc_link *link); 71 struct panel_cntl*(*panel_cntl_create)( 72 const struct panel_cntl_init_data *panel_cntl_init_data); 73 struct link_encoder *(*link_enc_create)( 74 struct dc_context *ctx, 75 const struct encoder_init_data *init); 76 /* Create a minimal link encoder object with no dc_link object 77 * associated with it. */ 78 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 79 80 bool (*validate_bandwidth)( 81 struct dc *dc, 82 struct dc_state *context, 83 bool fast_validate); 84 void (*calculate_wm_and_dlg)( 85 struct dc *dc, struct dc_state *context, 86 display_e2e_pipe_params_st *pipes, 87 int pipe_cnt, 88 int vlevel); 89 void (*update_soc_for_wm_a)( 90 struct dc *dc, struct dc_state *context); 91 92 /** 93 * @populate_dml_pipes - Populate pipe data struct 94 * 95 * Returns: 96 * Total of pipes available in the specific ASIC. 97 */ 98 int (*populate_dml_pipes)( 99 struct dc *dc, 100 struct dc_state *context, 101 display_e2e_pipe_params_st *pipes, 102 bool fast_validate); 103 104 /* 105 * Algorithm for assigning available link encoders to links. 106 * 107 * Update link_enc_assignments table and link_enc_avail list accordingly in 108 * struct resource_context. 109 */ 110 void (*link_encs_assign)( 111 struct dc *dc, 112 struct dc_state *state, 113 struct dc_stream_state *streams[], 114 uint8_t stream_count); 115 /* 116 * Unassign a link encoder from a stream. 117 * 118 * Update link_enc_assignments table and link_enc_avail list accordingly in 119 * struct resource_context. 120 */ 121 void (*link_enc_unassign)( 122 struct dc_state *state, 123 struct dc_stream_state *stream); 124 125 enum dc_status (*validate_global)( 126 struct dc *dc, 127 struct dc_state *context); 128 129 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 130 const struct dc_state *cur_ctx, 131 struct dc_state *new_ctx, 132 const struct resource_pool *pool, 133 const struct pipe_ctx *opp_head_pipe); 134 135 enum dc_status (*validate_plane)( 136 const struct dc_plane_state *plane_state, 137 struct dc_caps *caps); 138 139 enum dc_status (*add_stream_to_ctx)( 140 struct dc *dc, 141 struct dc_state *new_ctx, 142 struct dc_stream_state *dc_stream); 143 144 enum dc_status (*remove_stream_from_ctx)( 145 struct dc *dc, 146 struct dc_state *new_ctx, 147 struct dc_stream_state *stream); 148 enum dc_status (*patch_unknown_plane_state)( 149 struct dc_plane_state *plane_state); 150 151 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 152 struct resource_context *res_ctx, 153 const struct resource_pool *pool, 154 struct dc_stream_state *stream); 155 void (*populate_dml_writeback_from_context)( 156 struct dc *dc, 157 struct resource_context *res_ctx, 158 display_e2e_pipe_params_st *pipes); 159 160 void (*set_mcif_arb_params)( 161 struct dc *dc, 162 struct dc_state *context, 163 display_e2e_pipe_params_st *pipes, 164 int pipe_cnt); 165 void (*update_bw_bounding_box)( 166 struct dc *dc, 167 struct clk_bw_params *bw_params); 168 bool (*acquire_post_bldn_3dlut)( 169 struct resource_context *res_ctx, 170 const struct resource_pool *pool, 171 int mpcc_id, 172 struct dc_3dlut **lut, 173 struct dc_transfer_func **shaper); 174 175 bool (*release_post_bldn_3dlut)( 176 struct resource_context *res_ctx, 177 const struct resource_pool *pool, 178 struct dc_3dlut **lut, 179 struct dc_transfer_func **shaper); 180 181 enum dc_status (*add_dsc_to_stream_resource)( 182 struct dc *dc, struct dc_state *state, 183 struct dc_stream_state *stream); 184 185 void (*add_phantom_pipes)( 186 struct dc *dc, 187 struct dc_state *context, 188 display_e2e_pipe_params_st *pipes, 189 unsigned int pipe_cnt, 190 unsigned int index); 191 192 bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context, bool fast_update); 193 void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context); 194 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 195 void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 196 void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 197}; 198 199struct audio_support{ 200 bool dp_audio; 201 bool hdmi_audio_on_dongle; 202 bool hdmi_audio_native; 203}; 204 205#define NO_UNDERLAY_PIPE -1 206 207struct resource_pool { 208 struct mem_input *mis[MAX_PIPES]; 209 struct hubp *hubps[MAX_PIPES]; 210 struct input_pixel_processor *ipps[MAX_PIPES]; 211 struct transform *transforms[MAX_PIPES]; 212 struct dpp *dpps[MAX_PIPES]; 213 struct output_pixel_processor *opps[MAX_PIPES]; 214 struct timing_generator *timing_generators[MAX_PIPES]; 215 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 216 struct hubbub *hubbub; 217 struct mpc *mpc; 218 struct pp_smu_funcs *pp_smu; 219 struct dce_aux *engines[MAX_PIPES]; 220 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 221 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 222 bool i2c_hw_buffer_in_use; 223 224 struct dwbc *dwbc[MAX_DWB_PIPES]; 225 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 226 struct { 227 unsigned int gsl_0:1; 228 unsigned int gsl_1:1; 229 unsigned int gsl_2:1; 230 } gsl_groups; 231 232 struct display_stream_compressor *dscs[MAX_PIPES]; 233 234 unsigned int pipe_count; 235 unsigned int underlay_pipe_index; 236 unsigned int stream_enc_count; 237 238 /* An array for accessing the link encoder objects that have been created. 239 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 240 */ 241 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 242 /* Number of DIG link encoder objects created - i.e. number of valid 243 * entries in link_encoders array. 244 */ 245 unsigned int dig_link_enc_count; 246 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 247 unsigned int usb4_dpia_count; 248 249 unsigned int hpo_dp_stream_enc_count; 250 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 251 unsigned int hpo_dp_link_enc_count; 252 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 253 struct dc_3dlut *mpc_lut[MAX_PIPES]; 254 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 255 256 struct { 257 unsigned int xtalin_clock_inKhz; 258 unsigned int dccg_ref_clock_inKhz; 259 unsigned int dchub_ref_clock_inKhz; 260 } ref_clocks; 261 unsigned int timing_generator_count; 262 unsigned int mpcc_count; 263 264 unsigned int writeback_pipe_count; 265 /* 266 * reserved clock source for DP 267 */ 268 struct clock_source *dp_clock_source; 269 270 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 271 unsigned int clk_src_count; 272 273 struct audio *audios[MAX_AUDIOS]; 274 unsigned int audio_count; 275 struct audio_support audio_support; 276 277 struct dccg *dccg; 278 struct irq_service *irqs; 279 280 struct abm *abm; 281 struct dmcu *dmcu; 282 struct dmub_psr *psr; 283 284 struct dmub_replay *replay; 285 286 struct abm *multiple_abms[MAX_PIPES]; 287 288 const struct resource_funcs *funcs; 289 const struct resource_caps *res_cap; 290 291 struct ddc_service *oem_device; 292}; 293 294struct dcn_fe_bandwidth { 295 int dppclk_khz; 296 297}; 298 299struct stream_resource { 300 struct output_pixel_processor *opp; 301 struct display_stream_compressor *dsc; 302 struct timing_generator *tg; 303 struct stream_encoder *stream_enc; 304 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 305 struct audio *audio; 306 307 struct pixel_clk_params pix_clk_params; 308 struct encoder_info_frame encoder_info_frame; 309 310 struct abm *abm; 311 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 312 * otherwise it's using group number 'gsl_group-1' 313 */ 314 uint8_t gsl_group; 315}; 316 317struct plane_resource { 318 struct scaler_data scl_data; 319 struct hubp *hubp; 320 struct mem_input *mi; 321 struct input_pixel_processor *ipp; 322 struct transform *xfm; 323 struct dpp *dpp; 324 uint8_t mpcc_inst; 325 326 struct dcn_fe_bandwidth bw; 327}; 328 329#define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 330#define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 331 332/* all mappable hardware resources used to enable a link */ 333struct link_resource { 334 struct hpo_dp_link_encoder *hpo_dp_link_enc; 335}; 336 337struct link_config { 338 struct dc_link_settings dp_link_settings; 339}; 340union pipe_update_flags { 341 struct { 342 uint32_t enable : 1; 343 uint32_t disable : 1; 344 uint32_t odm : 1; 345 uint32_t global_sync : 1; 346 uint32_t opp_changed : 1; 347 uint32_t tg_changed : 1; 348 uint32_t mpcc : 1; 349 uint32_t dppclk : 1; 350 uint32_t hubp_interdependent : 1; 351 uint32_t hubp_rq_dlg_ttu : 1; 352 uint32_t gamut_remap : 1; 353 uint32_t scaler : 1; 354 uint32_t viewport : 1; 355 uint32_t plane_changed : 1; 356 uint32_t det_size : 1; 357 uint32_t unbounded_req : 1; 358 } bits; 359 uint32_t raw; 360}; 361 362struct pipe_ctx { 363 struct dc_plane_state *plane_state; 364 struct dc_stream_state *stream; 365 366 struct plane_resource plane_res; 367 368 /** 369 * @stream_res: Reference to DCN resource components such OPP and DSC. 370 */ 371 struct stream_resource stream_res; 372 struct link_resource link_res; 373 374 struct clock_source *clock_source; 375 376 struct pll_settings pll_settings; 377 378 /** 379 * @link_config: 380 * 381 * link config records software decision for what link config should be 382 * enabled given current link capability and stream during hw resource 383 * mapping. This is to decouple the dependency on link capability during 384 * dc commit or update. 385 */ 386 struct link_config link_config; 387 388 uint8_t pipe_idx; 389 uint8_t pipe_idx_syncd; 390 391 struct pipe_ctx *top_pipe; 392 struct pipe_ctx *bottom_pipe; 393 struct pipe_ctx *next_odm_pipe; 394 struct pipe_ctx *prev_odm_pipe; 395 396 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 397 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 398 struct _vcs_dpi_display_rq_regs_st rq_regs; 399 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 400 struct _vcs_dpi_display_rq_params_st dml_rq_param; 401 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 402 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 403 int det_buffer_size_kb; 404 bool unbounded_req; 405 unsigned int surface_size_in_mall_bytes; 406 407 struct dwbc *dwbc; 408 struct mcif_wb *mcif_wb; 409 union pipe_update_flags update_flags; 410 struct tg_color visual_confirm_color; 411 bool has_vactive_margin; 412}; 413 414/* Data used for dynamic link encoder assignment. 415 * Tracks current and future assignments; available link encoders; 416 * and mode of operation (whether to use current or future assignments). 417 */ 418struct link_enc_cfg_context { 419 enum link_enc_cfg_mode mode; 420 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 421 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 422 struct link_enc_assignment transient_assignments[MAX_PIPES]; 423}; 424 425struct resource_context { 426 struct pipe_ctx pipe_ctx[MAX_PIPES]; 427 bool is_stream_enc_acquired[MAX_PIPES * 2]; 428 bool is_audio_acquired[MAX_PIPES]; 429 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 430 uint8_t dp_clock_source_ref_count; 431 bool is_dsc_acquired[MAX_PIPES]; 432 struct link_enc_cfg_context link_enc_cfg_ctx; 433 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 434 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 435 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 436 bool is_mpc_3dlut_acquired[MAX_PIPES]; 437}; 438 439struct dce_bw_output { 440 bool cpuc_state_change_enable; 441 bool cpup_state_change_enable; 442 bool stutter_mode_enable; 443 bool nbp_state_change_enable; 444 bool all_displays_in_sync; 445 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 446 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 447 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 448 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 449 int sclk_khz; 450 int sclk_deep_sleep_khz; 451 int yclk_khz; 452 int dispclk_khz; 453 int blackout_recovery_time_us; 454}; 455 456struct dcn_bw_writeback { 457 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 458}; 459 460struct dcn_bw_output { 461 struct dc_clocks clk; 462 struct dcn_watermark_set watermarks; 463 struct dcn_bw_writeback bw_writeback; 464 int compbuf_size_kb; 465 unsigned int mall_ss_size_bytes; 466 unsigned int mall_ss_psr_active_size_bytes; 467 unsigned int mall_subvp_size_bytes; 468 unsigned int legacy_svp_drr_stream_index; 469 bool legacy_svp_drr_stream_index_valid; 470}; 471 472union bw_output { 473 struct dcn_bw_output dcn; 474 struct dce_bw_output dce; 475}; 476 477struct bw_context { 478 union bw_output bw; 479 struct display_mode_lib dml; 480}; 481 482struct dc_dmub_cmd { 483 union dmub_rb_cmd dmub_cmd; 484 enum dm_dmub_wait_type wait_type; 485}; 486 487/** 488 * struct dc_state - The full description of a state requested by users 489 */ 490struct dc_state { 491 /** 492 * @streams: Stream state properties 493 */ 494 struct dc_stream_state *streams[MAX_PIPES]; 495 496 /** 497 * @stream_status: Planes status on a given stream 498 */ 499 struct dc_stream_status stream_status[MAX_PIPES]; 500 501 /** 502 * @stream_count: Total of streams in use 503 */ 504 uint8_t stream_count; 505 uint8_t stream_mask; 506 507 /** 508 * @res_ctx: Persistent state of resources 509 */ 510 struct resource_context res_ctx; 511 512 /** 513 * @pp_display_cfg: PowerPlay clocks and settings 514 * Note: this is a big struct, do *not* put on stack! 515 */ 516 struct dm_pp_display_configuration pp_display_cfg; 517 518 /** 519 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 520 * Note: this is a big struct, do *not* put on stack! 521 */ 522 struct dcn_bw_internal_vars dcn_bw_vars; 523 524 struct clk_mgr *clk_mgr; 525 526 /** 527 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 528 * 529 * Each context must have its own instance of VBA, and in order to 530 * initialize and obtain IP and SOC, the base DML instance from DC is 531 * initially copied into every context. 532 */ 533 struct bw_context bw_ctx; 534 535 struct block_sequence block_sequence[50]; 536 unsigned int block_sequence_steps; 537 struct dc_dmub_cmd dc_dmub_cmd[10]; 538 unsigned int dmub_cmd_count; 539 540 /** 541 * @refcount: refcount reference 542 * 543 * Notice that dc_state is used around the code to capture the current 544 * context, so we need to pass it everywhere. That's why we want to use 545 * kref in this struct. 546 */ 547 struct kref refcount; 548 549 struct { 550 unsigned int stutter_period_us; 551 } perf_params; 552}; 553 554struct replay_context { 555 /* ddc line */ 556 enum channel_id aux_inst; 557 /* Transmitter id */ 558 enum transmitter digbe_inst; 559 /* Engine Id is used for Dig Be source select */ 560 enum engine_id digfe_inst; 561 /* Controller Id used for Dig Fe source select */ 562 enum controller_id controllerId; 563 unsigned int line_time_in_ns; 564}; 565 566enum dc_replay_enable { 567 DC_REPLAY_DISABLE = 0, 568 DC_REPLAY_ENABLE = 1, 569}; 570 571struct dc_bounding_box_max_clk { 572 int max_dcfclk_mhz; 573 int max_dispclk_mhz; 574 int max_dppclk_mhz; 575 int max_phyclk_mhz; 576}; 577 578#endif /* _CORE_TYPES_H_ */ 579