1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dm_services.h" 27#include "dc.h" 28#include "dc_bios_types.h" 29#include "core_types.h" 30#include "core_status.h" 31#include "resource.h" 32#include "dm_helpers.h" 33#include "dce110_timing_generator.h" 34#include "dce/dce_hwseq.h" 35#include "gpio_service_interface.h" 36 37#include "dce110_compressor.h" 38 39#include "bios/bios_parser_helper.h" 40#include "timing_generator.h" 41#include "mem_input.h" 42#include "opp.h" 43#include "ipp.h" 44#include "transform.h" 45#include "stream_encoder.h" 46#include "link_encoder.h" 47#include "link_enc_cfg.h" 48#include "link_hwss.h" 49#include "link.h" 50#include "dccg.h" 51#include "clock_source.h" 52#include "clk_mgr.h" 53#include "abm.h" 54#include <hw/audio.h> 55#include "reg_helper.h" 56#include "panel_cntl.h" 57#include "dpcd_defs.h" 58/* include DCE11 register header files */ 59#include "dce/dce_11_0_d.h" 60#include "dce/dce_11_0_sh_mask.h" 61#include "custom_float.h" 62 63#include "atomfirmware.h" 64 65#include "dcn10/dcn10_hw_sequencer.h" 66 67#include "dce110_hw_sequencer.h" 68 69#define GAMMA_HW_POINTS_NUM 256 70 71/* 72 * All values are in milliseconds; 73 * For eDP, after power-up/power/down, 74 * 300/500 msec max. delay from LCDVCC to black video generation 75 */ 76#define PANEL_POWER_UP_TIMEOUT 300 77#define PANEL_POWER_DOWN_TIMEOUT 500 78#define HPD_CHECK_INTERVAL 10 79#define OLED_POST_T7_DELAY 100 80#define OLED_PRE_T11_DELAY 150 81 82#define CTX \ 83 hws->ctx 84 85#define DC_LOGGER_INIT() 86 87#define REG(reg)\ 88 hws->regs->reg 89 90#undef FN 91#define FN(reg_name, field_name) \ 92 hws->shifts->field_name, hws->masks->field_name 93 94struct dce110_hw_seq_reg_offsets { 95 uint32_t crtc; 96}; 97 98static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 99{ 100 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 101}, 102{ 103 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 104}, 105{ 106 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 107}, 108{ 109 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 110} 111}; 112 113#define HW_REG_BLND(reg, id)\ 114 (reg + reg_offsets[id].blnd) 115 116#define HW_REG_CRTC(reg, id)\ 117 (reg + reg_offsets[id].crtc) 118 119#define MAX_WATERMARK 0xFFFF 120#define SAFE_NBP_MARK 0x7FFF 121 122/******************************************************************************* 123 * Private definitions 124 ******************************************************************************/ 125/***************************PIPE_CONTROL***********************************/ 126static void dce110_init_pte(struct dc_context *ctx) 127{ 128 uint32_t addr; 129 uint32_t value = 0; 130 uint32_t chunk_int = 0; 131 uint32_t chunk_mul = 0; 132 133 addr = mmUNP_DVMM_PTE_CONTROL; 134 value = dm_read_reg(ctx, addr); 135 136 set_reg_field_value( 137 value, 138 0, 139 DVMM_PTE_CONTROL, 140 DVMM_USE_SINGLE_PTE); 141 142 set_reg_field_value( 143 value, 144 1, 145 DVMM_PTE_CONTROL, 146 DVMM_PTE_BUFFER_MODE0); 147 148 set_reg_field_value( 149 value, 150 1, 151 DVMM_PTE_CONTROL, 152 DVMM_PTE_BUFFER_MODE1); 153 154 dm_write_reg(ctx, addr, value); 155 156 addr = mmDVMM_PTE_REQ; 157 value = dm_read_reg(ctx, addr); 158 159 chunk_int = get_reg_field_value( 160 value, 161 DVMM_PTE_REQ, 162 HFLIP_PTEREQ_PER_CHUNK_INT); 163 164 chunk_mul = get_reg_field_value( 165 value, 166 DVMM_PTE_REQ, 167 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 168 169 if (chunk_int != 0x4 || chunk_mul != 0x4) { 170 171 set_reg_field_value( 172 value, 173 255, 174 DVMM_PTE_REQ, 175 MAX_PTEREQ_TO_ISSUE); 176 177 set_reg_field_value( 178 value, 179 4, 180 DVMM_PTE_REQ, 181 HFLIP_PTEREQ_PER_CHUNK_INT); 182 183 set_reg_field_value( 184 value, 185 4, 186 DVMM_PTE_REQ, 187 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 188 189 dm_write_reg(ctx, addr, value); 190 } 191} 192/**************************************************************************/ 193 194static void enable_display_pipe_clock_gating( 195 struct dc_context *ctx, 196 bool clock_gating) 197{ 198 /*TODO*/ 199} 200 201static bool dce110_enable_display_power_gating( 202 struct dc *dc, 203 uint8_t controller_id, 204 struct dc_bios *dcb, 205 enum pipe_gating_control power_gating) 206{ 207 enum bp_result bp_result = BP_RESULT_OK; 208 enum bp_pipe_control_action cntl; 209 struct dc_context *ctx = dc->ctx; 210 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 211 212 if (power_gating == PIPE_GATING_CONTROL_INIT) 213 cntl = ASIC_PIPE_INIT; 214 else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 215 cntl = ASIC_PIPE_ENABLE; 216 else 217 cntl = ASIC_PIPE_DISABLE; 218 219 if (controller_id == underlay_idx) 220 controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 221 222 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { 223 224 bp_result = dcb->funcs->enable_disp_power_gating( 225 dcb, controller_id + 1, cntl); 226 227 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 228 * by default when command table is called 229 * 230 * Bios parser accepts controller_id = 6 as indicative of 231 * underlay pipe in dce110. But we do not support more 232 * than 3. 233 */ 234 if (controller_id < CONTROLLER_ID_MAX - 1) 235 dm_write_reg(ctx, 236 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 237 0); 238 } 239 240 if (power_gating != PIPE_GATING_CONTROL_ENABLE) 241 dce110_init_pte(ctx); 242 243 if (bp_result == BP_RESULT_OK) 244 return true; 245 else 246 return false; 247} 248 249static void build_prescale_params(struct ipp_prescale_params *prescale_params, 250 const struct dc_plane_state *plane_state) 251{ 252 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 253 254 switch (plane_state->format) { 255 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 256 prescale_params->scale = 0x2082; 257 break; 258 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 259 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 260 prescale_params->scale = 0x2020; 261 break; 262 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 263 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 264 prescale_params->scale = 0x2008; 265 break; 266 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 267 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 268 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 269 prescale_params->scale = 0x2000; 270 break; 271 default: 272 ASSERT(false); 273 break; 274 } 275} 276 277static bool 278dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 279 const struct dc_plane_state *plane_state) 280{ 281 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 282 const struct dc_transfer_func *tf = NULL; 283 struct ipp_prescale_params prescale_params = { 0 }; 284 bool result = true; 285 286 if (ipp == NULL) 287 return false; 288 289 if (plane_state->in_transfer_func) 290 tf = plane_state->in_transfer_func; 291 292 build_prescale_params(&prescale_params, plane_state); 293 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 294 295 if (plane_state->gamma_correction && 296 !plane_state->gamma_correction->is_identity && 297 dce_use_lut(plane_state->format)) 298 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 299 300 if (tf == NULL) { 301 /* Default case if no input transfer function specified */ 302 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 303 } else if (tf->type == TF_TYPE_PREDEFINED) { 304 switch (tf->tf) { 305 case TRANSFER_FUNCTION_SRGB: 306 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 307 break; 308 case TRANSFER_FUNCTION_BT709: 309 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 310 break; 311 case TRANSFER_FUNCTION_LINEAR: 312 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 313 break; 314 case TRANSFER_FUNCTION_PQ: 315 default: 316 result = false; 317 break; 318 } 319 } else if (tf->type == TF_TYPE_BYPASS) { 320 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 321 } else { 322 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 323 result = false; 324 } 325 326 return result; 327} 328 329static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 330 struct curve_points *arr_points, 331 uint32_t hw_points_num) 332{ 333 struct custom_float_format fmt; 334 335 struct pwl_result_data *rgb = rgb_resulted; 336 337 uint32_t i = 0; 338 339 fmt.exponenta_bits = 6; 340 fmt.mantissa_bits = 12; 341 fmt.sign = true; 342 343 if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 344 &arr_points[0].custom_float_x)) { 345 BREAK_TO_DEBUGGER(); 346 return false; 347 } 348 349 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 350 &arr_points[0].custom_float_offset)) { 351 BREAK_TO_DEBUGGER(); 352 return false; 353 } 354 355 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 356 &arr_points[0].custom_float_slope)) { 357 BREAK_TO_DEBUGGER(); 358 return false; 359 } 360 361 fmt.mantissa_bits = 10; 362 fmt.sign = false; 363 364 if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 365 &arr_points[1].custom_float_x)) { 366 BREAK_TO_DEBUGGER(); 367 return false; 368 } 369 370 if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 371 &arr_points[1].custom_float_y)) { 372 BREAK_TO_DEBUGGER(); 373 return false; 374 } 375 376 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 377 &arr_points[1].custom_float_slope)) { 378 BREAK_TO_DEBUGGER(); 379 return false; 380 } 381 382 fmt.mantissa_bits = 12; 383 fmt.sign = true; 384 385 while (i != hw_points_num) { 386 if (!convert_to_custom_float_format(rgb->red, &fmt, 387 &rgb->red_reg)) { 388 BREAK_TO_DEBUGGER(); 389 return false; 390 } 391 392 if (!convert_to_custom_float_format(rgb->green, &fmt, 393 &rgb->green_reg)) { 394 BREAK_TO_DEBUGGER(); 395 return false; 396 } 397 398 if (!convert_to_custom_float_format(rgb->blue, &fmt, 399 &rgb->blue_reg)) { 400 BREAK_TO_DEBUGGER(); 401 return false; 402 } 403 404 if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 405 &rgb->delta_red_reg)) { 406 BREAK_TO_DEBUGGER(); 407 return false; 408 } 409 410 if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 411 &rgb->delta_green_reg)) { 412 BREAK_TO_DEBUGGER(); 413 return false; 414 } 415 416 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 417 &rgb->delta_blue_reg)) { 418 BREAK_TO_DEBUGGER(); 419 return false; 420 } 421 422 ++rgb; 423 ++i; 424 } 425 426 return true; 427} 428 429#define MAX_LOW_POINT 25 430#define NUMBER_REGIONS 16 431#define NUMBER_SW_SEGMENTS 16 432 433static bool 434dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 435 struct pwl_params *regamma_params) 436{ 437 struct curve_points *arr_points; 438 struct pwl_result_data *rgb_resulted; 439 struct pwl_result_data *rgb; 440 struct pwl_result_data *rgb_plus_1; 441 struct fixed31_32 y_r; 442 struct fixed31_32 y_g; 443 struct fixed31_32 y_b; 444 struct fixed31_32 y1_min; 445 struct fixed31_32 y3_max; 446 447 int32_t region_start, region_end; 448 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 449 450 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 451 return false; 452 453 arr_points = regamma_params->arr_points; 454 rgb_resulted = regamma_params->rgb_resulted; 455 hw_points = 0; 456 457 memset(regamma_params, 0, sizeof(struct pwl_params)); 458 459 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 460 /* 16 segments 461 * segments are from 2^-11 to 2^5 462 */ 463 region_start = -11; 464 region_end = region_start + NUMBER_REGIONS; 465 466 for (i = 0; i < NUMBER_REGIONS; i++) 467 seg_distr[i] = 4; 468 469 } else { 470 /* 10 segments 471 * segment is from 2^-10 to 2^1 472 * We include an extra segment for range [2^0, 2^1). This is to 473 * ensure that colors with normalized values of 1 don't miss the 474 * LUT. 475 */ 476 region_start = -10; 477 region_end = 1; 478 479 seg_distr[0] = 4; 480 seg_distr[1] = 4; 481 seg_distr[2] = 4; 482 seg_distr[3] = 4; 483 seg_distr[4] = 4; 484 seg_distr[5] = 4; 485 seg_distr[6] = 4; 486 seg_distr[7] = 4; 487 seg_distr[8] = 4; 488 seg_distr[9] = 4; 489 seg_distr[10] = 0; 490 seg_distr[11] = -1; 491 seg_distr[12] = -1; 492 seg_distr[13] = -1; 493 seg_distr[14] = -1; 494 seg_distr[15] = -1; 495 } 496 497 for (k = 0; k < 16; k++) { 498 if (seg_distr[k] != -1) 499 hw_points += (1 << seg_distr[k]); 500 } 501 502 j = 0; 503 for (k = 0; k < (region_end - region_start); k++) { 504 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 505 start_index = (region_start + k + MAX_LOW_POINT) * 506 NUMBER_SW_SEGMENTS; 507 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 508 i += increment) { 509 if (j == hw_points - 1) 510 break; 511 rgb_resulted[j].red = output_tf->tf_pts.red[i]; 512 rgb_resulted[j].green = output_tf->tf_pts.green[i]; 513 rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 514 j++; 515 } 516 } 517 518 /* last point */ 519 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 520 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 521 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 522 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 523 524 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 525 dc_fixpt_from_int(region_start)); 526 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 527 dc_fixpt_from_int(region_end)); 528 529 y_r = rgb_resulted[0].red; 530 y_g = rgb_resulted[0].green; 531 y_b = rgb_resulted[0].blue; 532 533 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 534 535 arr_points[0].y = y1_min; 536 arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 537 arr_points[0].x); 538 539 y_r = rgb_resulted[hw_points - 1].red; 540 y_g = rgb_resulted[hw_points - 1].green; 541 y_b = rgb_resulted[hw_points - 1].blue; 542 543 /* see comment above, m_arrPoints[1].y should be the Y value for the 544 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 545 */ 546 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 547 548 arr_points[1].y = y3_max; 549 550 arr_points[1].slope = dc_fixpt_zero; 551 552 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 553 /* for PQ, we want to have a straight line from last HW X point, 554 * and the slope to be such that we hit 1.0 at 10000 nits. 555 */ 556 const struct fixed31_32 end_value = dc_fixpt_from_int(125); 557 558 arr_points[1].slope = dc_fixpt_div( 559 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 560 dc_fixpt_sub(end_value, arr_points[1].x)); 561 } 562 563 regamma_params->hw_points_num = hw_points; 564 565 k = 0; 566 for (i = 1; i < 16; i++) { 567 if (seg_distr[k] != -1) { 568 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 569 regamma_params->arr_curve_points[i].offset = 570 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 571 } 572 k++; 573 } 574 575 if (seg_distr[k] != -1) 576 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 577 578 rgb = rgb_resulted; 579 rgb_plus_1 = rgb_resulted + 1; 580 581 i = 1; 582 583 while (i != hw_points + 1) { 584 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 585 rgb_plus_1->red = rgb->red; 586 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 587 rgb_plus_1->green = rgb->green; 588 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 589 rgb_plus_1->blue = rgb->blue; 590 591 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 592 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 593 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 594 595 ++rgb_plus_1; 596 ++rgb; 597 ++i; 598 } 599 600 convert_to_custom_float(rgb_resulted, arr_points, hw_points); 601 602 return true; 603} 604 605static bool 606dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 607 const struct dc_stream_state *stream) 608{ 609 struct transform *xfm = pipe_ctx->plane_res.xfm; 610 611 xfm->funcs->opp_power_on_regamma_lut(xfm, true); 612 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 613 614 if (stream->out_transfer_func && 615 stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 616 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 617 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 618 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 619 &xfm->regamma_params)) { 620 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 622 } else { 623 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 624 } 625 626 xfm->funcs->opp_power_on_regamma_lut(xfm, false); 627 628 return true; 629} 630 631void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 632{ 633 bool is_hdmi_tmds; 634 bool is_dp; 635 636 ASSERT(pipe_ctx->stream); 637 638 if (pipe_ctx->stream_res.stream_enc == NULL) 639 return; /* this is not root pipe */ 640 641 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 642 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 643 644 if (!is_hdmi_tmds && !is_dp) 645 return; 646 647 if (is_hdmi_tmds) 648 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 649 pipe_ctx->stream_res.stream_enc, 650 &pipe_ctx->stream_res.encoder_info_frame); 651 else { 652 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 653 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 654 pipe_ctx->stream_res.stream_enc, 655 &pipe_ctx->stream_res.encoder_info_frame); 656 657 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 658 pipe_ctx->stream_res.stream_enc, 659 &pipe_ctx->stream_res.encoder_info_frame); 660 } 661} 662 663void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 664{ 665 enum dc_lane_count lane_count = 666 pipe_ctx->stream->link->cur_link_settings.lane_count; 667 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 668 struct dc_link *link = pipe_ctx->stream->link; 669 const struct dc *dc = link->dc; 670 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 671 uint32_t active_total_with_borders; 672 uint32_t early_control = 0; 673 struct timing_generator *tg = pipe_ctx->stream_res.tg; 674 675 link_hwss->setup_stream_encoder(pipe_ctx); 676 677 dc->hwss.update_info_frame(pipe_ctx); 678 679 /* enable early control to avoid corruption on DP monitor*/ 680 active_total_with_borders = 681 timing->h_addressable 682 + timing->h_border_left 683 + timing->h_border_right; 684 685 if (lane_count != 0) 686 early_control = active_total_with_borders % lane_count; 687 688 if (early_control == 0) 689 early_control = lane_count; 690 691 tg->funcs->set_early_control(tg, early_control); 692} 693 694static enum bp_result link_transmitter_control( 695 struct dc_bios *bios, 696 struct bp_transmitter_control *cntl) 697{ 698 enum bp_result result; 699 700 result = bios->funcs->transmitter_control(bios, cntl); 701 702 return result; 703} 704 705/* 706 * @brief 707 * eDP only. 708 */ 709void dce110_edp_wait_for_hpd_ready( 710 struct dc_link *link, 711 bool power_up) 712{ 713 struct dc_context *ctx = link->ctx; 714 struct graphics_object_id connector = link->link_enc->connector; 715 struct gpio *hpd; 716 bool edp_hpd_high = false; 717 uint32_t time_elapsed = 0; 718 uint32_t timeout = power_up ? 719 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 720 721 if (dal_graphics_object_id_get_connector_id(connector) 722 != CONNECTOR_ID_EDP) { 723 BREAK_TO_DEBUGGER(); 724 return; 725 } 726 727 if (!power_up) 728 /* 729 * From KV, we will not HPD low after turning off VCC - 730 * instead, we will check the SW timer in power_up(). 731 */ 732 return; 733 734 /* 735 * When we power on/off the eDP panel, 736 * we need to wait until SENSE bit is high/low. 737 */ 738 739 /* obtain HPD */ 740 /* TODO what to do with this? */ 741 hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 742 743 if (!hpd) { 744 BREAK_TO_DEBUGGER(); 745 return; 746 } 747 748 if (link != NULL) { 749 if (link->panel_config.pps.extra_t3_ms > 0) { 750 int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms; 751 752 drm_msleep(extra_t3_in_ms); 753 } 754 } 755 756 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 757 758 /* wait until timeout or panel detected */ 759 760 do { 761 uint32_t detected = 0; 762 763 dal_gpio_get_value(hpd, &detected); 764 765 if (!(detected ^ power_up)) { 766 edp_hpd_high = true; 767 break; 768 } 769 770 drm_msleep(HPD_CHECK_INTERVAL); 771 772 time_elapsed += HPD_CHECK_INTERVAL; 773 } while (time_elapsed < timeout); 774 775 dal_gpio_close(hpd); 776 777 dal_gpio_destroy_irq(&hpd); 778 779 /* ensure that the panel is detected */ 780 if (!edp_hpd_high) 781 DC_LOG_DC("%s: wait timed out!\n", __func__); 782} 783 784void dce110_edp_power_control( 785 struct dc_link *link, 786 bool power_up) 787{ 788 struct dc_context *ctx = link->ctx; 789 struct bp_transmitter_control cntl = { 0 }; 790 enum bp_result bp_result; 791 uint8_t pwrseq_instance; 792 793 794 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 795 != CONNECTOR_ID_EDP) { 796 BREAK_TO_DEBUGGER(); 797 return; 798 } 799 800 if (!link->panel_cntl) 801 return; 802 if (power_up != 803 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 804 805 unsigned long long current_ts = dm_get_timestamp(ctx); 806 unsigned long long time_since_edp_poweroff_ms = 807 div64_u64(dm_get_elapse_time_in_ns( 808 ctx, 809 current_ts, 810 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 811 unsigned long long time_since_edp_poweron_ms = 812 div64_u64(dm_get_elapse_time_in_ns( 813 ctx, 814 current_ts, 815 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000); 816 DC_LOG_HW_RESUME_S3( 817 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 818 __func__, 819 power_up, 820 current_ts, 821 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link), 822 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link), 823 time_since_edp_poweroff_ms, 824 time_since_edp_poweron_ms); 825 826 /* Send VBIOS command to prompt eDP panel power */ 827 if (power_up) { 828 /* edp requires a min of 500ms from LCDVDD off to on */ 829 unsigned long long remaining_min_edp_poweroff_time_ms = 500; 830 831 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 832 if (link->local_sink != NULL) 833 remaining_min_edp_poweroff_time_ms += 834 link->panel_config.pps.extra_t12_ms; 835 836 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 837 if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) { 838 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 839 remaining_min_edp_poweroff_time_ms = 840 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 841 else 842 remaining_min_edp_poweroff_time_ms = 0; 843 } 844 845 if (remaining_min_edp_poweroff_time_ms) { 846 DC_LOG_HW_RESUME_S3( 847 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 848 __func__, remaining_min_edp_poweroff_time_ms); 849 drm_msleep(remaining_min_edp_poweroff_time_ms); 850 DC_LOG_HW_RESUME_S3( 851 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 852 __func__, remaining_min_edp_poweroff_time_ms); 853 dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 854 __func__, remaining_min_edp_poweroff_time_ms); 855 } else { 856 DC_LOG_HW_RESUME_S3( 857 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 858 __func__, remaining_min_edp_poweroff_time_ms); 859 } 860 } 861 862 DC_LOG_HW_RESUME_S3( 863 "%s: BEGIN: Panel Power action: %s\n", 864 __func__, (power_up ? "On":"Off")); 865 866 cntl.action = power_up ? 867 TRANSMITTER_CONTROL_POWER_ON : 868 TRANSMITTER_CONTROL_POWER_OFF; 869 cntl.transmitter = link->link_enc->transmitter; 870 cntl.connector_obj_id = link->link_enc->connector; 871 cntl.coherent = false; 872 cntl.lanes_number = LANE_COUNT_FOUR; 873 cntl.hpd_sel = link->link_enc->hpd_source; 874 pwrseq_instance = link->panel_cntl->pwrseq_inst; 875 876 if (ctx->dc->ctx->dmub_srv && 877 ctx->dc->debug.dmub_command_table) { 878 879 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) { 880 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 881 LVTMA_CONTROL_POWER_ON, 882 pwrseq_instance, link->link_powered_externally); 883 } else { 884 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 885 LVTMA_CONTROL_POWER_OFF, 886 pwrseq_instance, link->link_powered_externally); 887 } 888 } 889 890 bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 891 892 DC_LOG_HW_RESUME_S3( 893 "%s: END: Panel Power action: %s bp_result=%u\n", 894 __func__, (power_up ? "On":"Off"), 895 bp_result); 896 897 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up); 898 899 DC_LOG_HW_RESUME_S3( 900 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 901 __func__, 902 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link), 903 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)); 904 905 if (bp_result != BP_RESULT_OK) 906 DC_LOG_ERROR( 907 "%s: Panel Power bp_result: %d\n", 908 __func__, bp_result); 909 } else { 910 DC_LOG_HW_RESUME_S3( 911 "%s: Skipping Panel Power action: %s\n", 912 __func__, (power_up ? "On":"Off")); 913 } 914} 915 916void dce110_edp_wait_for_T12( 917 struct dc_link *link) 918{ 919 struct dc_context *ctx = link->ctx; 920 921 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 922 != CONNECTOR_ID_EDP) { 923 BREAK_TO_DEBUGGER(); 924 return; 925 } 926 927 if (!link->panel_cntl) 928 return; 929 930 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 931 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) { 932 unsigned int t12_duration = 500; // Default T12 as per spec 933 unsigned long long current_ts = dm_get_timestamp(ctx); 934 unsigned long long time_since_edp_poweroff_ms = 935 div64_u64(dm_get_elapse_time_in_ns( 936 ctx, 937 current_ts, 938 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 939 940 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12 941 942 if (time_since_edp_poweroff_ms < t12_duration) 943 drm_msleep(t12_duration - time_since_edp_poweroff_ms); 944 } 945} 946/*todo: cloned in stream enc, fix*/ 947/* 948 * @brief 949 * eDP only. Control the backlight of the eDP panel 950 */ 951void dce110_edp_backlight_control( 952 struct dc_link *link, 953 bool enable) 954{ 955 struct dc_context *ctx = link->ctx; 956 struct bp_transmitter_control cntl = { 0 }; 957 uint8_t pwrseq_instance; 958 unsigned int pre_T11_delay = OLED_PRE_T11_DELAY; 959 unsigned int post_T7_delay = OLED_POST_T7_DELAY; 960 961 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 962 != CONNECTOR_ID_EDP) { 963 BREAK_TO_DEBUGGER(); 964 return; 965 } 966 967 if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled || 968 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 969 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { 970 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 971 972 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 973 DC_LOG_HW_RESUME_S3( 974 "%s: panel already powered up/off. Do nothing.\n", 975 __func__); 976 return; 977 } 978 } 979 980 /* Send VBIOS command to control eDP panel backlight */ 981 982 DC_LOG_HW_RESUME_S3( 983 "%s: backlight action: %s\n", 984 __func__, (enable ? "On":"Off")); 985 986 cntl.action = enable ? 987 TRANSMITTER_CONTROL_BACKLIGHT_ON : 988 TRANSMITTER_CONTROL_BACKLIGHT_OFF; 989 990 /*cntl.engine_id = ctx->engine;*/ 991 cntl.transmitter = link->link_enc->transmitter; 992 cntl.connector_obj_id = link->link_enc->connector; 993 /*todo: unhardcode*/ 994 cntl.lanes_number = LANE_COUNT_FOUR; 995 cntl.hpd_sel = link->link_enc->hpd_source; 996 cntl.signal = SIGNAL_TYPE_EDP; 997 998 /* For eDP, the following delays might need to be considered 999 * after link training completed: 1000 * idle period - min. accounts for required BS-Idle pattern, 1001 * max. allows for source frame synchronization); 1002 * 50 msec max. delay from valid video data from source 1003 * to video on dislpay or backlight enable. 1004 * 1005 * Disable the delay for now. 1006 * Enable it in the future if necessary. 1007 */ 1008 /* dc_service_sleep_in_milliseconds(50); */ 1009 /*edp 1.2*/ 1010 pwrseq_instance = link->panel_cntl->pwrseq_inst; 1011 1012 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1013 if (!link->dc->config.edp_no_power_sequencing) 1014 /* 1015 * Sometimes, DP receiver chip power-controlled externally by an 1016 * Embedded Controller could be treated and used as eDP, 1017 * if it drives mobile display. In this case, 1018 * we shouldn't be doing power-sequencing, hence we can skip 1019 * waiting for T7-ready. 1020 */ 1021 ctx->dc->link_srv->edp_receiver_ready_T7(link); 1022 else 1023 DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1024 } 1025 1026 /* Setting link_powered_externally will bypass delays in the backlight 1027 * as they are not required if the link is being powered by a different 1028 * source. 1029 */ 1030 if (ctx->dc->ctx->dmub_srv && 1031 ctx->dc->debug.dmub_command_table) { 1032 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 1033 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1034 LVTMA_CONTROL_LCD_BLON, 1035 pwrseq_instance, link->link_powered_externally); 1036 else 1037 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1038 LVTMA_CONTROL_LCD_BLOFF, 1039 pwrseq_instance, link->link_powered_externally); 1040 } 1041 1042 link_transmitter_control(ctx->dc_bios, &cntl); 1043 1044 if (enable && link->dpcd_sink_ext_caps.bits.oled) { 1045 post_T7_delay += link->panel_config.pps.extra_post_t7_ms; 1046 drm_msleep(post_T7_delay); 1047 } 1048 1049 if (link->dpcd_sink_ext_caps.bits.oled || 1050 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 1051 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 1052 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable); 1053 1054 /*edp 1.2*/ 1055 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1056 if (!link->dc->config.edp_no_power_sequencing) 1057 /* 1058 * Sometimes, DP receiver chip power-controlled externally by an 1059 * Embedded Controller could be treated and used as eDP, 1060 * if it drives mobile display. In this case, 1061 * we shouldn't be doing power-sequencing, hence we can skip 1062 * waiting for T9-ready. 1063 */ 1064 ctx->dc->link_srv->edp_add_delay_for_T9(link); 1065 else 1066 DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1067 } 1068 1069 if (!enable && link->dpcd_sink_ext_caps.bits.oled) { 1070 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms; 1071 drm_msleep(pre_T11_delay); 1072 } 1073} 1074 1075void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 1076{ 1077 /* notify audio driver for audio modes of monitor */ 1078 struct dc *dc; 1079 struct clk_mgr *clk_mgr; 1080 unsigned int i, num_audio = 1; 1081 const struct link_hwss *link_hwss; 1082 1083 if (!pipe_ctx->stream) 1084 return; 1085 1086 dc = pipe_ctx->stream->ctx->dc; 1087 clk_mgr = dc->clk_mgr; 1088 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); 1089 1090 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 1091 return; 1092 1093 if (pipe_ctx->stream_res.audio) { 1094 for (i = 0; i < MAX_PIPES; i++) { 1095 /*current_state not updated yet*/ 1096 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 1097 num_audio++; 1098 } 1099 1100 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 1101 1102 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 1103 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1104 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1105 1106 link_hwss->enable_audio_packet(pipe_ctx); 1107 1108 if (pipe_ctx->stream_res.audio) 1109 pipe_ctx->stream_res.audio->enabled = true; 1110 } 1111} 1112 1113void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 1114{ 1115 struct dc *dc; 1116 struct clk_mgr *clk_mgr; 1117 const struct link_hwss *link_hwss; 1118 1119 if (!pipe_ctx || !pipe_ctx->stream) 1120 return; 1121 1122 dc = pipe_ctx->stream->ctx->dc; 1123 clk_mgr = dc->clk_mgr; 1124 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); 1125 1126 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 1127 return; 1128 1129 link_hwss->disable_audio_packet(pipe_ctx); 1130 1131 if (pipe_ctx->stream_res.audio) { 1132 pipe_ctx->stream_res.audio->enabled = false; 1133 1134 if (clk_mgr->funcs->enable_pme_wa) 1135 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1136 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1137 1138 /* TODO: notify audio driver for if audio modes list changed 1139 * add audio mode list change flag */ 1140 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 1141 * stream->stream_engine_id); 1142 */ 1143 } 1144} 1145 1146void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 1147{ 1148 struct dc_stream_state *stream = pipe_ctx->stream; 1149 struct dc_link *link = stream->link; 1150 struct dc *dc = pipe_ctx->stream->ctx->dc; 1151 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1152 struct dccg *dccg = dc->res_pool->dccg; 1153 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1154 struct dtbclk_dto_params dto_params = {0}; 1155 int dp_hpo_inst; 1156 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 1157 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 1158 1159 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 1160 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 1161 pipe_ctx->stream_res.stream_enc); 1162 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1163 pipe_ctx->stream_res.stream_enc); 1164 } 1165 1166 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1167 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( 1168 pipe_ctx->stream_res.hpo_dp_stream_enc); 1169 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1170 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 1171 pipe_ctx->stream_res.stream_enc); 1172 1173 dc->hwss.disable_audio_stream(pipe_ctx); 1174 1175 link_hwss->reset_stream_encoder(pipe_ctx); 1176 1177 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1178 dto_params.otg_inst = tg->inst; 1179 dto_params.timing = &pipe_ctx->stream->timing; 1180 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 1181 if (dccg) { 1182 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 1183 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); 1184 if (dccg && dccg->funcs->set_dtbclk_dto) 1185 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1186 } 1187 } else if (dccg && dccg->funcs->disable_symclk_se) { 1188 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, 1189 link_enc->transmitter - TRANSMITTER_UNIPHY_A); 1190 } 1191 1192 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1193 /* TODO: This looks like a bug to me as we are disabling HPO IO when 1194 * we are just disabling a single HPO stream. Shouldn't we disable HPO 1195 * HW control only when HPOs for all streams are disabled? 1196 */ 1197 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control) 1198 pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control( 1199 pipe_ctx->stream->ctx->dc->hwseq, false); 1200 } 1201} 1202 1203void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 1204 struct dc_link_settings *link_settings) 1205{ 1206 struct encoder_unblank_param params = { { 0 } }; 1207 struct dc_stream_state *stream = pipe_ctx->stream; 1208 struct dc_link *link = stream->link; 1209 struct dce_hwseq *hws = link->dc->hwseq; 1210 1211 /* only 3 items below are used by unblank */ 1212 params.timing = pipe_ctx->stream->timing; 1213 params.link_settings.link_rate = link_settings->link_rate; 1214 1215 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1216 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1217 1218 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1219 hws->funcs.edp_backlight_control(link, true); 1220 } 1221} 1222 1223void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 1224{ 1225 struct dc_stream_state *stream = pipe_ctx->stream; 1226 struct dc_link *link = stream->link; 1227 struct dce_hwseq *hws = link->dc->hwseq; 1228 1229 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1230 if (!link->skip_implict_edp_power_control) 1231 hws->funcs.edp_backlight_control(link, false); 1232 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1233 } 1234 1235 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1236 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1237 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( 1238 pipe_ctx->stream_res.hpo_dp_stream_enc); 1239 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1240 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); 1241 1242 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1243 /* 1244 * After output is idle pattern some sinks need time to recognize the stream 1245 * has changed or they enter protection state and hang. 1246 */ 1247 drm_msleep(60); 1248 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 1249 if (!link->dc->config.edp_no_power_sequencing) { 1250 /* 1251 * Sometimes, DP receiver chip power-controlled externally by an 1252 * Embedded Controller could be treated and used as eDP, 1253 * if it drives mobile display. In this case, 1254 * we shouldn't be doing power-sequencing, hence we can skip 1255 * waiting for T9-ready. 1256 */ 1257 link->dc->link_srv->edp_receiver_ready_T9(link); 1258 } 1259 } 1260 } 1261 1262} 1263 1264 1265void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 1266{ 1267 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 1268 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 1269} 1270 1271static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 1272{ 1273 switch (crtc_id) { 1274 case CONTROLLER_ID_D0: 1275 return DTO_SOURCE_ID0; 1276 case CONTROLLER_ID_D1: 1277 return DTO_SOURCE_ID1; 1278 case CONTROLLER_ID_D2: 1279 return DTO_SOURCE_ID2; 1280 case CONTROLLER_ID_D3: 1281 return DTO_SOURCE_ID3; 1282 case CONTROLLER_ID_D4: 1283 return DTO_SOURCE_ID4; 1284 case CONTROLLER_ID_D5: 1285 return DTO_SOURCE_ID5; 1286 default: 1287 return DTO_SOURCE_UNKNOWN; 1288 } 1289} 1290 1291static void build_audio_output( 1292 struct dc_state *state, 1293 const struct pipe_ctx *pipe_ctx, 1294 struct audio_output *audio_output) 1295{ 1296 const struct dc_stream_state *stream = pipe_ctx->stream; 1297 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 1298 1299 audio_output->signal = pipe_ctx->stream->signal; 1300 1301 /* audio_crtc_info */ 1302 1303 audio_output->crtc_info.h_total = 1304 stream->timing.h_total; 1305 1306 /* 1307 * Audio packets are sent during actual CRTC blank physical signal, we 1308 * need to specify actual active signal portion 1309 */ 1310 audio_output->crtc_info.h_active = 1311 stream->timing.h_addressable 1312 + stream->timing.h_border_left 1313 + stream->timing.h_border_right; 1314 1315 audio_output->crtc_info.v_active = 1316 stream->timing.v_addressable 1317 + stream->timing.v_border_top 1318 + stream->timing.v_border_bottom; 1319 1320 audio_output->crtc_info.pixel_repetition = 1; 1321 1322 audio_output->crtc_info.interlaced = 1323 stream->timing.flags.INTERLACE; 1324 1325 audio_output->crtc_info.refresh_rate = 1326 (stream->timing.pix_clk_100hz*100)/ 1327 (stream->timing.h_total*stream->timing.v_total); 1328 1329 audio_output->crtc_info.color_depth = 1330 stream->timing.display_color_depth; 1331 1332 audio_output->crtc_info.requested_pixel_clock_100Hz = 1333 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1334 1335 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1336 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1337 1338/*for HDMI, audio ACR is with deep color ratio factor*/ 1339 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 1340 audio_output->crtc_info.requested_pixel_clock_100Hz == 1341 (stream->timing.pix_clk_100hz)) { 1342 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1343 audio_output->crtc_info.requested_pixel_clock_100Hz = 1344 audio_output->crtc_info.requested_pixel_clock_100Hz/2; 1345 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1346 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 1347 1348 } 1349 } 1350 1351 if (state->clk_mgr && 1352 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1353 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 1354 audio_output->pll_info.dp_dto_source_clock_in_khz = 1355 state->clk_mgr->funcs->get_dp_ref_clk_frequency( 1356 state->clk_mgr); 1357 } 1358 1359 audio_output->pll_info.feed_back_divider = 1360 pipe_ctx->pll_settings.feedback_divider; 1361 1362 audio_output->pll_info.dto_source = 1363 translate_to_dto_source( 1364 pipe_ctx->stream_res.tg->inst + 1); 1365 1366 /* TODO hard code to enable for now. Need get from stream */ 1367 audio_output->pll_info.ss_enabled = true; 1368 1369 audio_output->pll_info.ss_percentage = 1370 pipe_ctx->pll_settings.ss_percentage; 1371} 1372 1373static void program_scaler(const struct dc *dc, 1374 const struct pipe_ctx *pipe_ctx) 1375{ 1376 struct tg_color color = {0}; 1377 1378 /* TOFPGA */ 1379 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1380 return; 1381 1382 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 1383 get_surface_visual_confirm_color(pipe_ctx, &color); 1384 else 1385 color_space_to_black_color(dc, 1386 pipe_ctx->stream->output_color_space, 1387 &color); 1388 1389 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 1390 pipe_ctx->plane_res.xfm, 1391 pipe_ctx->plane_res.scl_data.lb_params.depth, 1392 &pipe_ctx->stream->bit_depth_params); 1393 1394 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 1395 /* 1396 * The way 420 is packed, 2 channels carry Y component, 1 channel 1397 * alternate between Cb and Cr, so both channels need the pixel 1398 * value for Y 1399 */ 1400 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1401 color.color_r_cr = color.color_g_y; 1402 1403 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 1404 pipe_ctx->stream_res.tg, 1405 &color); 1406 } 1407 1408 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 1409 &pipe_ctx->plane_res.scl_data); 1410} 1411 1412static enum dc_status dce110_enable_stream_timing( 1413 struct pipe_ctx *pipe_ctx, 1414 struct dc_state *context, 1415 struct dc *dc) 1416{ 1417 struct dc_stream_state *stream = pipe_ctx->stream; 1418 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1419 pipe_ctx[pipe_ctx->pipe_idx]; 1420 struct tg_color black_color = {0}; 1421 1422 if (!pipe_ctx_old->stream) { 1423 1424 /* program blank color */ 1425 color_space_to_black_color(dc, 1426 stream->output_color_space, &black_color); 1427 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1428 pipe_ctx->stream_res.tg, 1429 &black_color); 1430 1431 /* 1432 * Must blank CRTC after disabling power gating and before any 1433 * programming, otherwise CRTC will be hung in bad state 1434 */ 1435 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 1436 1437 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1438 pipe_ctx->clock_source, 1439 &pipe_ctx->stream_res.pix_clk_params, 1440 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1441 &pipe_ctx->pll_settings)) { 1442 BREAK_TO_DEBUGGER(); 1443 return DC_ERROR_UNEXPECTED; 1444 } 1445 1446 if (dc_is_hdmi_tmds_signal(stream->signal)) { 1447 stream->link->phy_state.symclk_ref_cnts.otg = 1; 1448 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 1449 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1450 else 1451 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 1452 } 1453 1454 pipe_ctx->stream_res.tg->funcs->program_timing( 1455 pipe_ctx->stream_res.tg, 1456 &stream->timing, 1457 0, 1458 0, 1459 0, 1460 0, 1461 pipe_ctx->stream->signal, 1462 true); 1463 } 1464 1465 if (!pipe_ctx_old->stream) { 1466 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 1467 pipe_ctx->stream_res.tg)) { 1468 BREAK_TO_DEBUGGER(); 1469 return DC_ERROR_UNEXPECTED; 1470 } 1471 } 1472 1473 return DC_OK; 1474} 1475 1476static enum dc_status apply_single_controller_ctx_to_hw( 1477 struct pipe_ctx *pipe_ctx, 1478 struct dc_state *context, 1479 struct dc *dc) 1480{ 1481 struct dc_stream_state *stream = pipe_ctx->stream; 1482 struct dc_link *link = stream->link; 1483 struct drr_params params = {0}; 1484 unsigned int event_triggers = 0; 1485 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1486 struct dce_hwseq *hws = dc->hwseq; 1487 const struct link_hwss *link_hwss = get_link_hwss( 1488 link, &pipe_ctx->link_res); 1489 1490 1491 if (hws->funcs.disable_stream_gating) { 1492 hws->funcs.disable_stream_gating(dc, pipe_ctx); 1493 } 1494 1495 if (pipe_ctx->stream_res.audio != NULL) { 1496 struct audio_output audio_output; 1497 1498 build_audio_output(context, pipe_ctx, &audio_output); 1499 1500 link_hwss->setup_audio_output(pipe_ctx, &audio_output, 1501 pipe_ctx->stream_res.audio->inst); 1502 1503 pipe_ctx->stream_res.audio->funcs->az_configure( 1504 pipe_ctx->stream_res.audio, 1505 pipe_ctx->stream->signal, 1506 &audio_output.crtc_info, 1507 &pipe_ctx->stream->audio_info); 1508 } 1509 1510 /* make sure no pipes syncd to the pipe being enabled */ 1511 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) 1512 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); 1513 1514 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1515 pipe_ctx->stream_res.opp, 1516 &stream->bit_depth_params, 1517 &stream->clamping); 1518 1519 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1520 pipe_ctx->stream_res.opp, 1521 COLOR_SPACE_YCBCR601, 1522 stream->timing.display_color_depth, 1523 stream->signal); 1524 1525 while (odm_pipe) { 1526 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 1527 odm_pipe->stream_res.opp, 1528 COLOR_SPACE_YCBCR601, 1529 stream->timing.display_color_depth, 1530 stream->signal); 1531 1532 odm_pipe->stream_res.opp->funcs->opp_program_fmt( 1533 odm_pipe->stream_res.opp, 1534 &stream->bit_depth_params, 1535 &stream->clamping); 1536 odm_pipe = odm_pipe->next_odm_pipe; 1537 } 1538 1539 /* DCN3.1 FPGA Workaround 1540 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1541 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1542 * function core_link_enable_stream 1543 */ 1544 if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))) 1545 /* */ 1546 /* Do not touch stream timing on seamless boot optimization. */ 1547 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1548 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1549 1550 if (hws->funcs.setup_vupdate_interrupt) 1551 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1552 1553 params.vertical_total_min = stream->adjust.v_total_min; 1554 params.vertical_total_max = stream->adjust.v_total_max; 1555 if (pipe_ctx->stream_res.tg->funcs->set_drr) 1556 pipe_ctx->stream_res.tg->funcs->set_drr( 1557 pipe_ctx->stream_res.tg, ¶ms); 1558 1559 // DRR should set trigger event to monitor surface update event 1560 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 1561 event_triggers = 0x80; 1562 /* Event triggers and num frames initialized for DRR, but can be 1563 * later updated for PSR use. Note DRR trigger events are generated 1564 * regardless of whether num frames met. 1565 */ 1566 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 1567 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1568 pipe_ctx->stream_res.tg, event_triggers, 2); 1569 1570 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1571 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1572 pipe_ctx->stream_res.stream_enc, 1573 pipe_ctx->stream_res.tg->inst); 1574 1575 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1576 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); 1577 1578 if (!stream->dpms_off) 1579 dc->link_srv->set_dpms_on(context, pipe_ctx); 1580 1581 /* DCN3.1 FPGA Workaround 1582 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1583 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1584 * function core_link_enable_stream 1585 */ 1586 if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1587 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1588 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1589 } 1590 1591 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 1592 1593 /* Phantom and main stream share the same link (because the stream 1594 * is constructed with the same sink). Make sure not to override 1595 * and link programming on the main. 1596 */ 1597 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1598 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 1599 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false; 1600 } 1601 return DC_OK; 1602} 1603 1604/******************************************************************************/ 1605 1606static void power_down_encoders(struct dc *dc) 1607{ 1608 int i; 1609 1610 for (i = 0; i < dc->link_count; i++) { 1611 enum amd_signal_type signal = dc->links[i]->connector_signal; 1612 1613 dc->link_srv->blank_dp_stream(dc->links[i], false); 1614 1615 if (signal != SIGNAL_TYPE_EDP) 1616 signal = SIGNAL_TYPE_NONE; 1617 1618 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY) 1619 dc->links[i]->link_enc->funcs->disable_output( 1620 dc->links[i]->link_enc, signal); 1621 1622 dc->links[i]->link_status.link_active = false; 1623 memset(&dc->links[i]->cur_link_settings, 0, 1624 sizeof(dc->links[i]->cur_link_settings)); 1625 } 1626} 1627 1628static void power_down_controllers(struct dc *dc) 1629{ 1630 int i; 1631 1632 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1633 dc->res_pool->timing_generators[i]->funcs->disable_crtc( 1634 dc->res_pool->timing_generators[i]); 1635 } 1636} 1637 1638static void power_down_clock_sources(struct dc *dc) 1639{ 1640 int i; 1641 1642 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 1643 dc->res_pool->dp_clock_source) == false) 1644 dm_error("Failed to power down pll! (dp clk src)\n"); 1645 1646 for (i = 0; i < dc->res_pool->clk_src_count; i++) { 1647 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 1648 dc->res_pool->clock_sources[i]) == false) 1649 dm_error("Failed to power down pll! (clk src index=%d)\n", i); 1650 } 1651} 1652 1653static void power_down_all_hw_blocks(struct dc *dc) 1654{ 1655 power_down_encoders(dc); 1656 1657 power_down_controllers(dc); 1658 1659 power_down_clock_sources(dc); 1660 1661 if (dc->fbc_compressor) 1662 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 1663} 1664 1665static void disable_vga_and_power_gate_all_controllers( 1666 struct dc *dc) 1667{ 1668 int i; 1669 struct timing_generator *tg; 1670 struct dc_context *ctx = dc->ctx; 1671 1672 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1673 tg = dc->res_pool->timing_generators[i]; 1674 1675 if (tg->funcs->disable_vga) 1676 tg->funcs->disable_vga(tg); 1677 } 1678 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1679 /* Enable CLOCK gating for each pipe BEFORE controller 1680 * powergating. */ 1681 enable_display_pipe_clock_gating(ctx, 1682 true); 1683 1684 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 1685 dc->hwss.disable_plane(dc, 1686 &dc->current_state->res_ctx.pipe_ctx[i]); 1687 } 1688} 1689 1690 1691static void get_edp_streams(struct dc_state *context, 1692 struct dc_stream_state **edp_streams, 1693 int *edp_stream_num) 1694{ 1695 int i; 1696 1697 *edp_stream_num = 0; 1698 for (i = 0; i < context->stream_count; i++) { 1699 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 1700 edp_streams[*edp_stream_num] = context->streams[i]; 1701 if (++(*edp_stream_num) == MAX_NUM_EDP) 1702 return; 1703 } 1704 } 1705} 1706 1707static void get_edp_links_with_sink( 1708 struct dc *dc, 1709 struct dc_link **edp_links_with_sink, 1710 int *edp_with_sink_num) 1711{ 1712 int i; 1713 1714 /* check if there is an eDP panel not in use */ 1715 *edp_with_sink_num = 0; 1716 for (i = 0; i < dc->link_count; i++) { 1717 if (dc->links[i]->local_sink && 1718 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1719 edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 1720 if (++(*edp_with_sink_num) == MAX_NUM_EDP) 1721 return; 1722 } 1723 } 1724} 1725 1726/* 1727 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 1728 * 1. Power down all DC HW blocks 1729 * 2. Disable VGA engine on all controllers 1730 * 3. Enable power gating for controller 1731 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 1732 */ 1733void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 1734{ 1735 struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 1736 struct dc_link *edp_links[MAX_NUM_EDP]; 1737 struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 1738 struct dc_link *edp_link_with_sink = NULL; 1739 struct dc_link *edp_link = NULL; 1740 struct dce_hwseq *hws = dc->hwseq; 1741 int edp_with_sink_num; 1742 int edp_num; 1743 int edp_stream_num; 1744 int i; 1745 bool can_apply_edp_fast_boot = false; 1746 bool can_apply_seamless_boot = false; 1747 bool keep_edp_vdd_on = false; 1748 DC_LOGGER_INIT(); 1749 1750 1751 get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 1752 dc_get_edp_links(dc, edp_links, &edp_num); 1753 1754 if (hws->funcs.init_pipes) 1755 hws->funcs.init_pipes(dc, context); 1756 1757 get_edp_streams(context, edp_streams, &edp_stream_num); 1758 1759 // Check fastboot support, disable on DCE8 because of blank screens 1760 if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 && 1761 dc->ctx->dce_version != DCE_VERSION_8_1 && 1762 dc->ctx->dce_version != DCE_VERSION_8_3) { 1763 for (i = 0; i < edp_num; i++) { 1764 edp_link = edp_links[i]; 1765 if (edp_link != edp_streams[0]->link) 1766 continue; 1767 // enable fastboot if backend is enabled on eDP 1768 if (edp_link->link_enc->funcs->is_dig_enabled && 1769 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 1770 edp_link->link_status.link_active) { 1771 struct dc_stream_state *edp_stream = edp_streams[0]; 1772 1773 can_apply_edp_fast_boot = dc_validate_boot_timing(dc, 1774 edp_stream->sink, &edp_stream->timing); 1775 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 1776 if (can_apply_edp_fast_boot) 1777 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n"); 1778 1779 break; 1780 } 1781 } 1782 // We are trying to enable eDP, don't power down VDD 1783 if (can_apply_edp_fast_boot) 1784 keep_edp_vdd_on = true; 1785 } 1786 1787 // Check seamless boot support 1788 for (i = 0; i < context->stream_count; i++) { 1789 if (context->streams[i]->apply_seamless_boot_optimization) { 1790 can_apply_seamless_boot = true; 1791 break; 1792 } 1793 } 1794 1795 /* eDP should not have stream in resume from S4 and so even with VBios post 1796 * it should get turned off 1797 */ 1798 if (edp_with_sink_num) 1799 edp_link_with_sink = edp_links_with_sink[0]; 1800 1801 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 1802 if (edp_link_with_sink && !keep_edp_vdd_on) { 1803 /*turn off backlight before DP_blank and encoder powered down*/ 1804 hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1805 } 1806 /*resume from S3, no vbios posting, no need to power down again*/ 1807 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 1808 1809 power_down_all_hw_blocks(dc); 1810 disable_vga_and_power_gate_all_controllers(dc); 1811 if (edp_link_with_sink && !keep_edp_vdd_on) 1812 dc->hwss.edp_power_control(edp_link_with_sink, false); 1813 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 1814 } 1815 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 1816} 1817 1818static uint32_t compute_pstate_blackout_duration( 1819 struct bw_fixed blackout_duration, 1820 const struct dc_stream_state *stream) 1821{ 1822 uint32_t total_dest_line_time_ns; 1823 uint32_t pstate_blackout_duration_ns; 1824 1825 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 1826 1827 total_dest_line_time_ns = 1000000UL * 1828 (stream->timing.h_total * 10) / 1829 stream->timing.pix_clk_100hz + 1830 pstate_blackout_duration_ns; 1831 1832 return total_dest_line_time_ns; 1833} 1834 1835static void dce110_set_displaymarks( 1836 const struct dc *dc, 1837 struct dc_state *context) 1838{ 1839 uint8_t i, num_pipes; 1840 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1841 1842 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 1843 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1844 uint32_t total_dest_line_time_ns; 1845 1846 if (pipe_ctx->stream == NULL) 1847 continue; 1848 1849 total_dest_line_time_ns = compute_pstate_blackout_duration( 1850 dc->bw_vbios->blackout_duration, pipe_ctx->stream); 1851 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 1852 pipe_ctx->plane_res.mi, 1853 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1854 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1855 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1856 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1857 total_dest_line_time_ns); 1858 if (i == underlay_idx) { 1859 num_pipes++; 1860 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1861 pipe_ctx->plane_res.mi, 1862 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1863 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1864 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 1865 total_dest_line_time_ns); 1866 } 1867 num_pipes++; 1868 } 1869} 1870 1871void dce110_set_safe_displaymarks( 1872 struct resource_context *res_ctx, 1873 const struct resource_pool *pool) 1874{ 1875 int i; 1876 int underlay_idx = pool->underlay_pipe_index; 1877 struct dce_watermarks max_marks = { 1878 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 1879 struct dce_watermarks nbp_marks = { 1880 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 1881 struct dce_watermarks min_marks = { 0, 0, 0, 0}; 1882 1883 for (i = 0; i < MAX_PIPES; i++) { 1884 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 1885 continue; 1886 1887 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 1888 res_ctx->pipe_ctx[i].plane_res.mi, 1889 nbp_marks, 1890 max_marks, 1891 min_marks, 1892 max_marks, 1893 MAX_WATERMARK); 1894 1895 if (i == underlay_idx) 1896 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 1897 res_ctx->pipe_ctx[i].plane_res.mi, 1898 nbp_marks, 1899 max_marks, 1900 max_marks, 1901 MAX_WATERMARK); 1902 1903 } 1904} 1905 1906/******************************************************************************* 1907 * Public functions 1908 ******************************************************************************/ 1909 1910static void set_drr(struct pipe_ctx **pipe_ctx, 1911 int num_pipes, struct dc_crtc_timing_adjust adjust) 1912{ 1913 int i = 0; 1914 struct drr_params params = {0}; 1915 // DRR should set trigger event to monitor surface update event 1916 unsigned int event_triggers = 0x80; 1917 // Note DRR trigger events are generated regardless of whether num frames met. 1918 unsigned int num_frames = 2; 1919 1920 params.vertical_total_max = adjust.v_total_max; 1921 params.vertical_total_min = adjust.v_total_min; 1922 1923 /* TODO: If multiple pipes are to be supported, you need 1924 * some GSL stuff. Static screen triggers may be programmed differently 1925 * as well. 1926 */ 1927 for (i = 0; i < num_pipes; i++) { 1928 pipe_ctx[i]->stream_res.tg->funcs->set_drr( 1929 pipe_ctx[i]->stream_res.tg, ¶ms); 1930 1931 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 1932 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 1933 pipe_ctx[i]->stream_res.tg, 1934 event_triggers, num_frames); 1935 } 1936} 1937 1938static void get_position(struct pipe_ctx **pipe_ctx, 1939 int num_pipes, 1940 struct crtc_position *position) 1941{ 1942 int i = 0; 1943 1944 /* TODO: handle pipes > 1 1945 */ 1946 for (i = 0; i < num_pipes; i++) 1947 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 1948} 1949 1950static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 1951 int num_pipes, const struct dc_static_screen_params *params) 1952{ 1953 unsigned int i; 1954 unsigned int triggers = 0; 1955 1956 if (params->triggers.overlay_update) 1957 triggers |= 0x100; 1958 if (params->triggers.surface_update) 1959 triggers |= 0x80; 1960 if (params->triggers.cursor_update) 1961 triggers |= 0x2; 1962 if (params->triggers.force_trigger) 1963 triggers |= 0x1; 1964 1965 if (num_pipes) { 1966 struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 1967 1968 if (dc->fbc_compressor) 1969 triggers |= 0x84; 1970 } 1971 1972 for (i = 0; i < num_pipes; i++) 1973 pipe_ctx[i]->stream_res.tg->funcs-> 1974 set_static_screen_control(pipe_ctx[i]->stream_res.tg, 1975 triggers, params->num_frames); 1976} 1977 1978/* 1979 * Check if FBC can be enabled 1980 */ 1981static bool should_enable_fbc(struct dc *dc, 1982 struct dc_state *context, 1983 uint32_t *pipe_idx) 1984{ 1985 uint32_t i; 1986 struct pipe_ctx *pipe_ctx = NULL; 1987 struct resource_context *res_ctx = &context->res_ctx; 1988 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1989 1990 1991 ASSERT(dc->fbc_compressor); 1992 1993 /* FBC memory should be allocated */ 1994 if (!dc->ctx->fbc_gpu_addr) 1995 return false; 1996 1997 /* Only supports single display */ 1998 if (context->stream_count != 1) 1999 return false; 2000 2001 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2002 if (res_ctx->pipe_ctx[i].stream) { 2003 2004 pipe_ctx = &res_ctx->pipe_ctx[i]; 2005 2006 if (!pipe_ctx) 2007 continue; 2008 2009 /* fbc not applicable on underlay pipe */ 2010 if (pipe_ctx->pipe_idx != underlay_idx) { 2011 *pipe_idx = i; 2012 break; 2013 } 2014 } 2015 } 2016 2017 if (i == dc->res_pool->pipe_count) 2018 return false; 2019 2020 if (!pipe_ctx->stream->link) 2021 return false; 2022 2023 /* Only supports eDP */ 2024 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 2025 return false; 2026 2027 /* PSR should not be enabled */ 2028 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 2029 return false; 2030 2031 /* Replay should not be enabled */ 2032 if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled) 2033 return false; 2034 2035 /* Nothing to compress */ 2036 if (!pipe_ctx->plane_state) 2037 return false; 2038 2039 /* Only for non-linear tiling */ 2040 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 2041 return false; 2042 2043 return true; 2044} 2045 2046/* 2047 * Enable FBC 2048 */ 2049static void enable_fbc( 2050 struct dc *dc, 2051 struct dc_state *context) 2052{ 2053 uint32_t pipe_idx = 0; 2054 2055 if (should_enable_fbc(dc, context, &pipe_idx)) { 2056 /* Program GRPH COMPRESSED ADDRESS and PITCH */ 2057 struct compr_addr_and_pitch_params params = {0, 0, 0}; 2058 struct compressor *compr = dc->fbc_compressor; 2059 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2060 2061 params.source_view_width = pipe_ctx->stream->timing.h_addressable; 2062 params.source_view_height = pipe_ctx->stream->timing.v_addressable; 2063 params.inst = pipe_ctx->stream_res.tg->inst; 2064 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 2065 2066 compr->funcs->surface_address_and_pitch(compr, ¶ms); 2067 compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2068 2069 compr->funcs->enable_fbc(compr, ¶ms); 2070 } 2071} 2072 2073static void dce110_reset_hw_ctx_wrap( 2074 struct dc *dc, 2075 struct dc_state *context) 2076{ 2077 int i; 2078 2079 /* Reset old context */ 2080 /* look up the targets that have been removed since last commit */ 2081 for (i = 0; i < MAX_PIPES; i++) { 2082 struct pipe_ctx *pipe_ctx_old = 2083 &dc->current_state->res_ctx.pipe_ctx[i]; 2084 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2085 2086 /* Note: We need to disable output if clock sources change, 2087 * since bios does optimization and doesn't apply if changing 2088 * PHY when not already disabled. 2089 */ 2090 2091 /* Skip underlay pipe since it will be handled in commit surface*/ 2092 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 2093 continue; 2094 2095 if (!pipe_ctx->stream || 2096 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2097 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2098 2099 /* Disable if new stream is null. O/w, if stream is 2100 * disabled already, no need to disable again. 2101 */ 2102 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 2103 dc->link_srv->set_dpms_off(pipe_ctx_old); 2104 2105 /* free acquired resources*/ 2106 if (pipe_ctx_old->stream_res.audio) { 2107 /*disable az_endpoint*/ 2108 pipe_ctx_old->stream_res.audio->funcs-> 2109 az_disable(pipe_ctx_old->stream_res.audio); 2110 2111 /*free audio*/ 2112 if (dc->caps.dynamic_audio == true) { 2113 /*we have to dynamic arbitrate the audio endpoints*/ 2114 /*we free the resource, need reset is_audio_acquired*/ 2115 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2116 pipe_ctx_old->stream_res.audio, false); 2117 pipe_ctx_old->stream_res.audio = NULL; 2118 } 2119 } 2120 } 2121 2122 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 2123 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 2124 dm_error("DC: failed to blank crtc!\n"); 2125 BREAK_TO_DEBUGGER(); 2126 } 2127 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 2128 if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal)) 2129 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0; 2130 pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2131 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 2132 2133 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2134 dc->res_pool, 2135 old_clk)) 2136 old_clk->funcs->cs_power_down(old_clk); 2137 2138 dc->hwss.disable_plane(dc, pipe_ctx_old); 2139 2140 pipe_ctx_old->stream = NULL; 2141 } 2142 } 2143} 2144 2145static void dce110_setup_audio_dto( 2146 struct dc *dc, 2147 struct dc_state *context) 2148{ 2149 int i; 2150 2151 /* program audio wall clock. use HDMI as clock source if HDMI 2152 * audio active. Otherwise, use DP as clock source 2153 * first, loop to find any HDMI audio, if not, loop find DP audio 2154 */ 2155 /* Setup audio rate clock source */ 2156 /* Issue: 2157 * Audio lag happened on DP monitor when unplug a HDMI monitor 2158 * 2159 * Cause: 2160 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 2161 * is set to either dto0 or dto1, audio should work fine. 2162 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 2163 * set to dto0 will cause audio lag. 2164 * 2165 * Solution: 2166 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 2167 * find first available pipe with audio, setup audio wall DTO per topology 2168 * instead of per pipe. 2169 */ 2170 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2171 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2172 2173 if (pipe_ctx->stream == NULL) 2174 continue; 2175 2176 if (pipe_ctx->top_pipe) 2177 continue; 2178 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 2179 continue; 2180 if (pipe_ctx->stream_res.audio != NULL) { 2181 struct audio_output audio_output; 2182 2183 build_audio_output(context, pipe_ctx, &audio_output); 2184 2185 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 2186 struct dtbclk_dto_params dto_params = {0}; 2187 2188 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 2189 dc->res_pool->dccg, &dto_params); 2190 2191 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2192 pipe_ctx->stream_res.audio, 2193 pipe_ctx->stream->signal, 2194 &audio_output.crtc_info, 2195 &audio_output.pll_info); 2196 } else 2197 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2198 pipe_ctx->stream_res.audio, 2199 pipe_ctx->stream->signal, 2200 &audio_output.crtc_info, 2201 &audio_output.pll_info); 2202 break; 2203 } 2204 } 2205 2206 /* no HDMI audio is found, try DP audio */ 2207 if (i == dc->res_pool->pipe_count) { 2208 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2209 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2210 2211 if (pipe_ctx->stream == NULL) 2212 continue; 2213 2214 if (pipe_ctx->top_pipe) 2215 continue; 2216 2217 if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 2218 continue; 2219 2220 if (pipe_ctx->stream_res.audio != NULL) { 2221 struct audio_output audio_output; 2222 2223 build_audio_output(context, pipe_ctx, &audio_output); 2224 2225 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2226 pipe_ctx->stream_res.audio, 2227 pipe_ctx->stream->signal, 2228 &audio_output.crtc_info, 2229 &audio_output.pll_info); 2230 break; 2231 } 2232 } 2233 } 2234} 2235 2236enum dc_status dce110_apply_ctx_to_hw( 2237 struct dc *dc, 2238 struct dc_state *context) 2239{ 2240 struct dce_hwseq *hws = dc->hwseq; 2241 struct dc_bios *dcb = dc->ctx->dc_bios; 2242 enum dc_status status; 2243 int i; 2244 2245 /* reset syncd pipes from disabled pipes */ 2246 if (dc->config.use_pipe_ctx_sync_logic) 2247 reset_syncd_pipes_from_disabled_pipes(dc, context); 2248 2249 /* Reset old context */ 2250 /* look up the targets that have been removed since last commit */ 2251 hws->funcs.reset_hw_ctx_wrap(dc, context); 2252 2253 /* Skip applying if no targets */ 2254 if (context->stream_count <= 0) 2255 return DC_OK; 2256 2257 /* Apply new context */ 2258 dcb->funcs->set_scratch_critical_state(dcb, true); 2259 2260 /* below is for real asic only */ 2261 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2262 struct pipe_ctx *pipe_ctx_old = 2263 &dc->current_state->res_ctx.pipe_ctx[i]; 2264 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2265 2266 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 2267 continue; 2268 2269 if (pipe_ctx->stream == pipe_ctx_old->stream) { 2270 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 2271 dce_crtc_switch_to_clk_src(dc->hwseq, 2272 pipe_ctx->clock_source, i); 2273 continue; 2274 } 2275 2276 hws->funcs.enable_display_power_gating( 2277 dc, i, dc->ctx->dc_bios, 2278 PIPE_GATING_CONTROL_DISABLE); 2279 } 2280 2281 if (dc->fbc_compressor) 2282 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2283 2284 dce110_setup_audio_dto(dc, context); 2285 2286 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2287 struct pipe_ctx *pipe_ctx_old = 2288 &dc->current_state->res_ctx.pipe_ctx[i]; 2289 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2290 2291 if (pipe_ctx->stream == NULL) 2292 continue; 2293 2294 if (pipe_ctx->stream == pipe_ctx_old->stream && 2295 pipe_ctx->stream->link->link_state_valid) { 2296 continue; 2297 } 2298 2299 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2300 continue; 2301 2302 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2303 continue; 2304 2305 status = apply_single_controller_ctx_to_hw( 2306 pipe_ctx, 2307 context, 2308 dc); 2309 2310 if (DC_OK != status) 2311 return status; 2312 2313#ifdef CONFIG_DRM_AMD_DC_FP 2314 if (hws->funcs.resync_fifo_dccg_dio) 2315 hws->funcs.resync_fifo_dccg_dio(hws, dc, context); 2316#endif 2317 } 2318 2319 if (dc->fbc_compressor) 2320 enable_fbc(dc, dc->current_state); 2321 2322 dcb->funcs->set_scratch_critical_state(dcb, false); 2323 2324 return DC_OK; 2325} 2326 2327/******************************************************************************* 2328 * Front End programming 2329 ******************************************************************************/ 2330static void set_default_colors(struct pipe_ctx *pipe_ctx) 2331{ 2332 struct default_adjustment default_adjust = { 0 }; 2333 2334 default_adjust.force_hw_default = false; 2335 default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 2336 default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 2337 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 2338 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 2339 2340 /* display color depth */ 2341 default_adjust.color_depth = 2342 pipe_ctx->stream->timing.display_color_depth; 2343 2344 /* Lb color depth */ 2345 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 2346 2347 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 2348 pipe_ctx->plane_res.xfm, &default_adjust); 2349} 2350 2351 2352/******************************************************************************* 2353 * In order to turn on/off specific surface we will program 2354 * Blender + CRTC 2355 * 2356 * In case that we have two surfaces and they have a different visibility 2357 * we can't turn off the CRTC since it will turn off the entire display 2358 * 2359 * |----------------------------------------------- | 2360 * |bottom pipe|curr pipe | | | 2361 * |Surface |Surface | Blender | CRCT | 2362 * |visibility |visibility | Configuration| | 2363 * |------------------------------------------------| 2364 * | off | off | CURRENT_PIPE | blank | 2365 * | off | on | CURRENT_PIPE | unblank | 2366 * | on | off | OTHER_PIPE | unblank | 2367 * | on | on | BLENDING | unblank | 2368 * -------------------------------------------------| 2369 * 2370 ******************************************************************************/ 2371static void program_surface_visibility(const struct dc *dc, 2372 struct pipe_ctx *pipe_ctx) 2373{ 2374 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2375 bool blank_target = false; 2376 2377 if (pipe_ctx->bottom_pipe) { 2378 2379 /* For now we are supporting only two pipes */ 2380 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2381 2382 if (pipe_ctx->bottom_pipe->plane_state->visible) { 2383 if (pipe_ctx->plane_state->visible) 2384 blender_mode = BLND_MODE_BLENDING; 2385 else 2386 blender_mode = BLND_MODE_OTHER_PIPE; 2387 2388 } else if (!pipe_ctx->plane_state->visible) 2389 blank_target = true; 2390 2391 } else if (!pipe_ctx->plane_state->visible) 2392 blank_target = true; 2393 2394 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 2395 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2396 2397} 2398 2399static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 2400{ 2401 int i = 0; 2402 struct xfm_grph_csc_adjustment adjust; 2403 memset(&adjust, 0, sizeof(adjust)); 2404 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2405 2406 2407 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2408 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2409 2410 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2411 adjust.temperature_matrix[i] = 2412 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2413 } 2414 2415 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2416} 2417static void update_plane_addr(const struct dc *dc, 2418 struct pipe_ctx *pipe_ctx) 2419{ 2420 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2421 2422 if (plane_state == NULL) 2423 return; 2424 2425 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 2426 pipe_ctx->plane_res.mi, 2427 &plane_state->address, 2428 plane_state->flip_immediate); 2429 2430 plane_state->status.requested_address = plane_state->address; 2431} 2432 2433static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 2434{ 2435 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2436 2437 if (plane_state == NULL) 2438 return; 2439 2440 plane_state->status.is_flip_pending = 2441 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 2442 pipe_ctx->plane_res.mi); 2443 2444 if (plane_state->status.is_flip_pending && !plane_state->visible) 2445 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 2446 2447 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 2448 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2449 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 2450 plane_state->status.is_right_eye =\ 2451 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 2452 } 2453} 2454 2455void dce110_power_down(struct dc *dc) 2456{ 2457 power_down_all_hw_blocks(dc); 2458 disable_vga_and_power_gate_all_controllers(dc); 2459} 2460 2461static bool wait_for_reset_trigger_to_occur( 2462 struct dc_context *dc_ctx, 2463 struct timing_generator *tg) 2464{ 2465 bool rc = false; 2466 2467 /* To avoid endless loop we wait at most 2468 * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 2469 const uint32_t frames_to_wait_on_triggered_reset = 10; 2470 uint32_t i; 2471 2472 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 2473 2474 if (!tg->funcs->is_counter_moving(tg)) { 2475 DC_ERROR("TG counter is not moving!\n"); 2476 break; 2477 } 2478 2479 if (tg->funcs->did_triggered_reset_occur(tg)) { 2480 rc = true; 2481 /* usually occurs at i=1 */ 2482 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 2483 i); 2484 break; 2485 } 2486 2487 /* Wait for one frame. */ 2488 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 2489 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 2490 } 2491 2492 if (false == rc) 2493 DC_ERROR("GSL: Timeout on reset trigger!\n"); 2494 2495 return rc; 2496} 2497 2498/* Enable timing synchronization for a group of Timing Generators. */ 2499static void dce110_enable_timing_synchronization( 2500 struct dc *dc, 2501 int group_index, 2502 int group_size, 2503 struct pipe_ctx *grouped_pipes[]) 2504{ 2505 struct dc_context *dc_ctx = dc->ctx; 2506 struct dcp_gsl_params gsl_params = { 0 }; 2507 int i; 2508 2509 DC_SYNC_INFO("GSL: Setting-up...\n"); 2510 2511 /* Designate a single TG in the group as a master. 2512 * Since HW doesn't care which one, we always assign 2513 * the 1st one in the group. */ 2514 gsl_params.gsl_group = 0; 2515 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 2516 2517 for (i = 0; i < group_size; i++) 2518 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2519 grouped_pipes[i]->stream_res.tg, &gsl_params); 2520 2521 /* Reset slave controllers on master VSync */ 2522 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2523 2524 for (i = 1 /* skip the master */; i < group_size; i++) 2525 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2526 grouped_pipes[i]->stream_res.tg, 2527 gsl_params.gsl_group); 2528 2529 for (i = 1 /* skip the master */; i < group_size; i++) { 2530 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2531 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2532 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2533 grouped_pipes[i]->stream_res.tg); 2534 } 2535 2536 /* GSL Vblank synchronization is a one time sync mechanism, assumption 2537 * is that the sync'ed displays will not drift out of sync over time*/ 2538 DC_SYNC_INFO("GSL: Restoring register states.\n"); 2539 for (i = 0; i < group_size; i++) 2540 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2541 2542 DC_SYNC_INFO("GSL: Set-up complete.\n"); 2543} 2544 2545static void dce110_enable_per_frame_crtc_position_reset( 2546 struct dc *dc, 2547 int group_size, 2548 struct pipe_ctx *grouped_pipes[]) 2549{ 2550 struct dc_context *dc_ctx = dc->ctx; 2551 struct dcp_gsl_params gsl_params = { 0 }; 2552 int i; 2553 2554 gsl_params.gsl_group = 0; 2555 gsl_params.gsl_master = 0; 2556 2557 for (i = 0; i < group_size; i++) 2558 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2559 grouped_pipes[i]->stream_res.tg, &gsl_params); 2560 2561 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2562 2563 for (i = 1; i < group_size; i++) 2564 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2565 grouped_pipes[i]->stream_res.tg, 2566 gsl_params.gsl_master, 2567 &grouped_pipes[i]->stream->triggered_crtc_reset); 2568 2569 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2570 for (i = 1; i < group_size; i++) 2571 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2572 2573 for (i = 0; i < group_size; i++) 2574 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2575 2576} 2577 2578static void init_pipes(struct dc *dc, struct dc_state *context) 2579{ 2580 // Do nothing 2581} 2582 2583static void init_hw(struct dc *dc) 2584{ 2585 int i; 2586 struct dc_bios *bp; 2587 struct transform *xfm; 2588 struct abm *abm; 2589 struct dmcu *dmcu; 2590 struct dce_hwseq *hws = dc->hwseq; 2591 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 2592 2593 bp = dc->ctx->dc_bios; 2594 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2595 xfm = dc->res_pool->transforms[i]; 2596 xfm->funcs->transform_reset(xfm); 2597 2598 hws->funcs.enable_display_power_gating( 2599 dc, i, bp, 2600 PIPE_GATING_CONTROL_INIT); 2601 hws->funcs.enable_display_power_gating( 2602 dc, i, bp, 2603 PIPE_GATING_CONTROL_DISABLE); 2604 hws->funcs.enable_display_pipe_clock_gating( 2605 dc->ctx, 2606 true); 2607 } 2608 2609 dce_clock_gating_power_up(dc->hwseq, false); 2610 /***************************************/ 2611 2612 for (i = 0; i < dc->link_count; i++) { 2613 /****************************************/ 2614 /* Power up AND update implementation according to the 2615 * required signal (which may be different from the 2616 * default signal on connector). */ 2617 struct dc_link *link = dc->links[i]; 2618 2619 link->link_enc->funcs->hw_init(link->link_enc); 2620 } 2621 2622 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2623 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2624 2625 tg->funcs->disable_vga(tg); 2626 2627 /* Blank controller using driver code instead of 2628 * command table. */ 2629 tg->funcs->set_blank(tg, true); 2630 hwss_wait_for_blank_complete(tg); 2631 } 2632 2633 for (i = 0; i < dc->res_pool->audio_count; i++) { 2634 struct audio *audio = dc->res_pool->audios[i]; 2635 audio->funcs->hw_init(audio); 2636 } 2637 2638 for (i = 0; i < dc->link_count; i++) { 2639 struct dc_link *link = dc->links[i]; 2640 2641 if (link->panel_cntl) 2642 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 2643 } 2644 2645 abm = dc->res_pool->abm; 2646 if (abm != NULL) 2647 abm->funcs->abm_init(abm, backlight); 2648 2649 dmcu = dc->res_pool->dmcu; 2650 if (dmcu != NULL && abm != NULL) 2651 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 2652 2653 if (dc->fbc_compressor) 2654 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2655 2656} 2657 2658 2659void dce110_prepare_bandwidth( 2660 struct dc *dc, 2661 struct dc_state *context) 2662{ 2663 struct clk_mgr *dccg = dc->clk_mgr; 2664 2665 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2666 if (dccg) 2667 dccg->funcs->update_clocks( 2668 dccg, 2669 context, 2670 false); 2671} 2672 2673void dce110_optimize_bandwidth( 2674 struct dc *dc, 2675 struct dc_state *context) 2676{ 2677 struct clk_mgr *dccg = dc->clk_mgr; 2678 2679 dce110_set_displaymarks(dc, context); 2680 2681 if (dccg) 2682 dccg->funcs->update_clocks( 2683 dccg, 2684 context, 2685 true); 2686} 2687 2688static void dce110_program_front_end_for_pipe( 2689 struct dc *dc, struct pipe_ctx *pipe_ctx) 2690{ 2691 struct mem_input *mi = pipe_ctx->plane_res.mi; 2692 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2693 struct xfm_grph_csc_adjustment adjust; 2694 struct out_csc_color_matrix tbl_entry; 2695 unsigned int i; 2696 struct dce_hwseq *hws = dc->hwseq; 2697 2698 DC_LOGGER_INIT(); 2699 memset(&tbl_entry, 0, sizeof(tbl_entry)); 2700 2701 memset(&adjust, 0, sizeof(adjust)); 2702 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2703 2704 dce_enable_fe_clock(dc->hwseq, mi->inst, true); 2705 2706 set_default_colors(pipe_ctx); 2707 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2708 == true) { 2709 tbl_entry.color_space = 2710 pipe_ctx->stream->output_color_space; 2711 2712 for (i = 0; i < 12; i++) 2713 tbl_entry.regval[i] = 2714 pipe_ctx->stream->csc_color_matrix.matrix[i]; 2715 2716 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 2717 (pipe_ctx->plane_res.xfm, &tbl_entry); 2718 } 2719 2720 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2721 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2722 2723 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2724 adjust.temperature_matrix[i] = 2725 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2726 } 2727 2728 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2729 2730 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 2731 2732 program_scaler(dc, pipe_ctx); 2733 2734 mi->funcs->mem_input_program_surface_config( 2735 mi, 2736 plane_state->format, 2737 &plane_state->tiling_info, 2738 &plane_state->plane_size, 2739 plane_state->rotation, 2740 NULL, 2741 false); 2742 if (mi->funcs->set_blank) 2743 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 2744 2745 if (dc->config.gpu_vm_support) 2746 mi->funcs->mem_input_program_pte_vm( 2747 pipe_ctx->plane_res.mi, 2748 plane_state->format, 2749 &plane_state->tiling_info, 2750 plane_state->rotation); 2751 2752 /* Moved programming gamma from dc to hwss */ 2753 if (pipe_ctx->plane_state->update_flags.bits.full_update || 2754 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2755 pipe_ctx->plane_state->update_flags.bits.gamma_change) 2756 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2757 2758 if (pipe_ctx->plane_state->update_flags.bits.full_update) 2759 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2760 2761 DC_LOG_SURFACE( 2762 "Pipe:%d %p: addr hi:0x%x, " 2763 "addr low:0x%x, " 2764 "src: %d, %d, %d," 2765 " %d; dst: %d, %d, %d, %d;" 2766 "clip: %d, %d, %d, %d\n", 2767 pipe_ctx->pipe_idx, 2768 (void *) pipe_ctx->plane_state, 2769 pipe_ctx->plane_state->address.grph.addr.high_part, 2770 pipe_ctx->plane_state->address.grph.addr.low_part, 2771 pipe_ctx->plane_state->src_rect.x, 2772 pipe_ctx->plane_state->src_rect.y, 2773 pipe_ctx->plane_state->src_rect.width, 2774 pipe_ctx->plane_state->src_rect.height, 2775 pipe_ctx->plane_state->dst_rect.x, 2776 pipe_ctx->plane_state->dst_rect.y, 2777 pipe_ctx->plane_state->dst_rect.width, 2778 pipe_ctx->plane_state->dst_rect.height, 2779 pipe_ctx->plane_state->clip_rect.x, 2780 pipe_ctx->plane_state->clip_rect.y, 2781 pipe_ctx->plane_state->clip_rect.width, 2782 pipe_ctx->plane_state->clip_rect.height); 2783 2784 DC_LOG_SURFACE( 2785 "Pipe %d: width, height, x, y\n" 2786 "viewport:%d, %d, %d, %d\n" 2787 "recout: %d, %d, %d, %d\n", 2788 pipe_ctx->pipe_idx, 2789 pipe_ctx->plane_res.scl_data.viewport.width, 2790 pipe_ctx->plane_res.scl_data.viewport.height, 2791 pipe_ctx->plane_res.scl_data.viewport.x, 2792 pipe_ctx->plane_res.scl_data.viewport.y, 2793 pipe_ctx->plane_res.scl_data.recout.width, 2794 pipe_ctx->plane_res.scl_data.recout.height, 2795 pipe_ctx->plane_res.scl_data.recout.x, 2796 pipe_ctx->plane_res.scl_data.recout.y); 2797} 2798 2799static void dce110_apply_ctx_for_surface( 2800 struct dc *dc, 2801 const struct dc_stream_state *stream, 2802 int num_planes, 2803 struct dc_state *context) 2804{ 2805 int i; 2806 2807 if (num_planes == 0) 2808 return; 2809 2810 if (dc->fbc_compressor) 2811 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2812 2813 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2814 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2815 2816 if (pipe_ctx->stream != stream) 2817 continue; 2818 2819 /* Need to allocate mem before program front end for Fiji */ 2820 pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 2821 pipe_ctx->plane_res.mi, 2822 pipe_ctx->stream->timing.h_total, 2823 pipe_ctx->stream->timing.v_total, 2824 pipe_ctx->stream->timing.pix_clk_100hz / 10, 2825 context->stream_count); 2826 2827 dce110_program_front_end_for_pipe(dc, pipe_ctx); 2828 2829 dc->hwss.update_plane_addr(dc, pipe_ctx); 2830 2831 program_surface_visibility(dc, pipe_ctx); 2832 2833 } 2834 2835 if (dc->fbc_compressor) 2836 enable_fbc(dc, context); 2837} 2838 2839static void dce110_post_unlock_program_front_end( 2840 struct dc *dc, 2841 struct dc_state *context) 2842{ 2843} 2844 2845static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 2846{ 2847 struct dce_hwseq *hws = dc->hwseq; 2848 int fe_idx = pipe_ctx->plane_res.mi ? 2849 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2850 2851 /* Do not power down fe when stream is active on dce*/ 2852 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 2853 return; 2854 2855 hws->funcs.enable_display_power_gating( 2856 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2857 2858 dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2859 dc->res_pool->transforms[fe_idx]); 2860} 2861 2862static void dce110_wait_for_mpcc_disconnect( 2863 struct dc *dc, 2864 struct resource_pool *res_pool, 2865 struct pipe_ctx *pipe_ctx) 2866{ 2867 /* do nothing*/ 2868} 2869 2870static void program_output_csc(struct dc *dc, 2871 struct pipe_ctx *pipe_ctx, 2872 enum dc_color_space colorspace, 2873 uint16_t *matrix, 2874 int opp_id) 2875{ 2876 int i; 2877 struct out_csc_color_matrix tbl_entry; 2878 2879 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 2880 enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 2881 2882 for (i = 0; i < 12; i++) 2883 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2884 2885 tbl_entry.color_space = color_space; 2886 2887 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 2888 pipe_ctx->plane_res.xfm, &tbl_entry); 2889 } 2890} 2891 2892static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 2893{ 2894 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 2895 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2896 struct mem_input *mi = pipe_ctx->plane_res.mi; 2897 struct dc_cursor_mi_param param = { 2898 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 2899 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 2900 .viewport = pipe_ctx->plane_res.scl_data.viewport, 2901 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 2902 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 2903 .rotation = pipe_ctx->plane_state->rotation, 2904 .mirror = pipe_ctx->plane_state->horizontal_mirror 2905 }; 2906 2907 /** 2908 * If the cursor's source viewport is clipped then we need to 2909 * translate the cursor to appear in the correct position on 2910 * the screen. 2911 * 2912 * This translation isn't affected by scaling so it needs to be 2913 * done *after* we adjust the position for the scale factor. 2914 * 2915 * This is only done by opt-in for now since there are still 2916 * some usecases like tiled display that might enable the 2917 * cursor on both streams while expecting dc to clip it. 2918 */ 2919 if (pos_cpy.translate_by_source) { 2920 pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 2921 pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2922 } 2923 2924 if (pipe_ctx->plane_state->address.type 2925 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 2926 pos_cpy.enable = false; 2927 2928 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 2929 pos_cpy.enable = false; 2930 2931 if (ipp->funcs->ipp_cursor_set_position) 2932 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2933 if (mi->funcs->set_cursor_position) 2934 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 2935} 2936 2937static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 2938{ 2939 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 2940 2941 if (pipe_ctx->plane_res.ipp && 2942 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 2943 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 2944 pipe_ctx->plane_res.ipp, attributes); 2945 2946 if (pipe_ctx->plane_res.mi && 2947 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 2948 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 2949 pipe_ctx->plane_res.mi, attributes); 2950 2951 if (pipe_ctx->plane_res.xfm && 2952 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 2953 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 2954 pipe_ctx->plane_res.xfm, attributes); 2955} 2956 2957bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 2958 uint32_t backlight_pwm_u16_16, 2959 uint32_t frame_ramp) 2960{ 2961 struct dc_link *link = pipe_ctx->stream->link; 2962 struct dc *dc = link->ctx->dc; 2963 struct abm *abm = pipe_ctx->stream_res.abm; 2964 struct panel_cntl *panel_cntl = link->panel_cntl; 2965 struct dmcu *dmcu = dc->res_pool->dmcu; 2966 bool fw_set_brightness = true; 2967 /* DMCU -1 for all controller id values, 2968 * therefore +1 here 2969 */ 2970 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 2971 2972 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 2973 return false; 2974 2975 if (dmcu) 2976 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 2977 2978 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 2979 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 2980 else 2981 abm->funcs->set_backlight_level_pwm( 2982 abm, 2983 backlight_pwm_u16_16, 2984 frame_ramp, 2985 controller_id, 2986 link->panel_cntl->inst); 2987 2988 return true; 2989} 2990 2991void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 2992{ 2993 struct abm *abm = pipe_ctx->stream_res.abm; 2994 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 2995 2996 if (abm) 2997 abm->funcs->set_abm_immediate_disable(abm, 2998 pipe_ctx->stream->link->panel_cntl->inst); 2999 3000 if (panel_cntl) 3001 panel_cntl->funcs->store_backlight_level(panel_cntl); 3002} 3003 3004void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 3005{ 3006 struct abm *abm = pipe_ctx->stream_res.abm; 3007 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 3008 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 3009 3010 if (abm && panel_cntl) 3011 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 3012} 3013 3014void dce110_enable_lvds_link_output(struct dc_link *link, 3015 const struct link_resource *link_res, 3016 enum clock_source_id clock_source, 3017 uint32_t pixel_clock) 3018{ 3019 link->link_enc->funcs->enable_lvds_output( 3020 link->link_enc, 3021 clock_source, 3022 pixel_clock); 3023 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3024} 3025 3026void dce110_enable_tmds_link_output(struct dc_link *link, 3027 const struct link_resource *link_res, 3028 enum amd_signal_type signal, 3029 enum clock_source_id clock_source, 3030 enum dc_color_depth color_depth, 3031 uint32_t pixel_clock) 3032{ 3033 link->link_enc->funcs->enable_tmds_output( 3034 link->link_enc, 3035 clock_source, 3036 color_depth, 3037 signal, 3038 pixel_clock); 3039 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3040} 3041 3042void dce110_enable_dp_link_output( 3043 struct dc_link *link, 3044 const struct link_resource *link_res, 3045 enum amd_signal_type signal, 3046 enum clock_source_id clock_source, 3047 const struct dc_link_settings *link_settings) 3048{ 3049 struct dc *dc = link->ctx->dc; 3050 struct dmcu *dmcu = dc->res_pool->dmcu; 3051 struct pipe_ctx *pipes = 3052 link->dc->current_state->res_ctx.pipe_ctx; 3053 struct clock_source *dp_cs = 3054 link->dc->res_pool->dp_clock_source; 3055 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 3056 unsigned int i; 3057 3058 /* 3059 * Add the logic to extract BOTH power up and power down sequences 3060 * from enable/disable link output and only call edp panel control 3061 * in enable_link_dp and disable_link_dp once. 3062 */ 3063 if (link->connector_signal == SIGNAL_TYPE_EDP) { 3064 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 3065 } 3066 3067 /* If the current pixel clock source is not DTO(happens after 3068 * switching from HDMI passive dongle to DP on the same connector), 3069 * switch the pixel clock source to DTO. 3070 */ 3071 3072 for (i = 0; i < MAX_PIPES; i++) { 3073 if (pipes[i].stream != NULL && 3074 pipes[i].stream->link == link) { 3075 if (pipes[i].clock_source != NULL && 3076 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 3077 pipes[i].clock_source = dp_cs; 3078 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz = 3079 pipes[i].stream->timing.pix_clk_100hz; 3080 pipes[i].clock_source->funcs->program_pix_clk( 3081 pipes[i].clock_source, 3082 &pipes[i].stream_res.pix_clk_params, 3083 dc->link_srv->dp_get_encoding_format(link_settings), 3084 &pipes[i].pll_settings); 3085 } 3086 } 3087 } 3088 3089 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { 3090 if (dc->clk_mgr->funcs->notify_link_rate_change) 3091 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); 3092 } 3093 3094 if (dmcu != NULL && dmcu->funcs->lock_phy) 3095 dmcu->funcs->lock_phy(dmcu); 3096 3097 if (link_hwss->ext.enable_dp_link_output) 3098 link_hwss->ext.enable_dp_link_output(link, link_res, signal, 3099 clock_source, link_settings); 3100 3101 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3102 3103 if (dmcu != NULL && dmcu->funcs->unlock_phy) 3104 dmcu->funcs->unlock_phy(dmcu); 3105 3106 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY); 3107} 3108 3109void dce110_disable_link_output(struct dc_link *link, 3110 const struct link_resource *link_res, 3111 enum amd_signal_type signal) 3112{ 3113 struct dc *dc = link->ctx->dc; 3114 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 3115 struct dmcu *dmcu = dc->res_pool->dmcu; 3116 3117 if (signal == SIGNAL_TYPE_EDP && 3118 link->dc->hwss.edp_backlight_control) 3119 link->dc->hwss.edp_backlight_control(link, false); 3120 else if (dmcu != NULL && dmcu->funcs->lock_phy) 3121 dmcu->funcs->lock_phy(dmcu); 3122 3123 link_hwss->disable_link_output(link, link_res, signal); 3124 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 3125 /* 3126 * Add the logic to extract BOTH power up and power down sequences 3127 * from enable/disable link output and only call edp panel control 3128 * in enable_link_dp and disable_link_dp once. 3129 */ 3130 if (dmcu != NULL && dmcu->funcs->lock_phy) 3131 dmcu->funcs->unlock_phy(dmcu); 3132 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 3133} 3134 3135static const struct hw_sequencer_funcs dce110_funcs = { 3136 .program_gamut_remap = program_gamut_remap, 3137 .program_output_csc = program_output_csc, 3138 .init_hw = init_hw, 3139 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 3140 .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 3141 .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 3142 .update_plane_addr = update_plane_addr, 3143 .update_pending_status = dce110_update_pending_status, 3144 .enable_accelerated_mode = dce110_enable_accelerated_mode, 3145 .enable_timing_synchronization = dce110_enable_timing_synchronization, 3146 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 3147 .update_info_frame = dce110_update_info_frame, 3148 .enable_stream = dce110_enable_stream, 3149 .disable_stream = dce110_disable_stream, 3150 .unblank_stream = dce110_unblank_stream, 3151 .blank_stream = dce110_blank_stream, 3152 .enable_audio_stream = dce110_enable_audio_stream, 3153 .disable_audio_stream = dce110_disable_audio_stream, 3154 .disable_plane = dce110_power_down_fe, 3155 .pipe_control_lock = dce_pipe_control_lock, 3156 .interdependent_update_lock = NULL, 3157 .cursor_lock = dce_pipe_control_lock, 3158 .prepare_bandwidth = dce110_prepare_bandwidth, 3159 .optimize_bandwidth = dce110_optimize_bandwidth, 3160 .set_drr = set_drr, 3161 .get_position = get_position, 3162 .set_static_screen_control = set_static_screen_control, 3163 .setup_stereo = NULL, 3164 .set_avmute = dce110_set_avmute, 3165 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 3166 .edp_backlight_control = dce110_edp_backlight_control, 3167 .edp_power_control = dce110_edp_power_control, 3168 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 3169 .set_cursor_position = dce110_set_cursor_position, 3170 .set_cursor_attribute = dce110_set_cursor_attribute, 3171 .set_backlight_level = dce110_set_backlight_level, 3172 .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 3173 .set_pipe = dce110_set_pipe, 3174 .enable_lvds_link_output = dce110_enable_lvds_link_output, 3175 .enable_tmds_link_output = dce110_enable_tmds_link_output, 3176 .enable_dp_link_output = dce110_enable_dp_link_output, 3177 .disable_link_output = dce110_disable_link_output, 3178}; 3179 3180static const struct hwseq_private_funcs dce110_private_funcs = { 3181 .init_pipes = init_pipes, 3182 .update_plane_addr = update_plane_addr, 3183 .set_input_transfer_func = dce110_set_input_transfer_func, 3184 .set_output_transfer_func = dce110_set_output_transfer_func, 3185 .power_down = dce110_power_down, 3186 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 3187 .enable_display_power_gating = dce110_enable_display_power_gating, 3188 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 3189 .enable_stream_timing = dce110_enable_stream_timing, 3190 .disable_stream_gating = NULL, 3191 .enable_stream_gating = NULL, 3192 .edp_backlight_control = dce110_edp_backlight_control, 3193}; 3194 3195void dce110_hw_sequencer_construct(struct dc *dc) 3196{ 3197 dc->hwss = dce110_funcs; 3198 dc->hwseq->funcs = dce110_private_funcs; 3199} 3200 3201