/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/ |
H A D | dce_clk_mgr.h | 34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base); 36 struct clk_mgr *clk_mgr_base, 51 struct clk_mgr *clk_mgr_base,
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H A D | dce_clk_mgr.c | 129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) argument 131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) argument 157 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); 195 struct clk_mgr *clk_mgr_base, 198 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 230 struct clk_mgr *clk_mgr_base, 233 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 235 struct dc_bios *bp = clk_mgr_base 194 dce_get_required_clocks_state( struct clk_mgr *clk_mgr_base, struct dc_state *context) argument 229 dce_set_clock( struct clk_mgr *clk_mgr_base, int requested_clk_khz) argument 397 dce_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
H A D | dcn30_clk_mgr.c | 108 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) argument 110 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 113 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); 114 clk_mgr_base->clks.p_state_change_support = true; 115 clk_mgr_base->clks.prev_p_state_change_support = true; 118 if (!clk_mgr_base->bw_params) 121 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) 133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, 139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, 144 &clk_mgr_base 192 dcn3_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) argument 323 dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument 355 dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) argument 376 dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) argument 387 dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) argument 396 dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) argument 406 dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) argument 429 dcn3_is_smu_present(struct clk_mgr *clk_mgr_base) argument 454 dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 465 dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) argument [all...] |
H A D | dcn30_clk_mgr.h | 89 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 155 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) argument 157 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; 162 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); 163 clk_mgr_base->clks.p_state_change_support = true; 164 clk_mgr_base->clks.prev_p_state_change_support = true; 165 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; 169 if (!clk_mgr_base->bw_params) 172 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) 183 &clk_mgr_base 437 dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) argument 454 dcn32_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) argument 684 dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument 780 dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument 806 dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) argument 827 dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) argument 838 dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) argument 905 dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 915 dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) argument 921 dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) argument 931 dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) argument [all...] |
H A D | dcn32_clk_mgr.h | 28 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/ |
H A D | dce112_clk_mgr.h | 35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
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H A D | dce112_clk_mgr.c | 70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) argument 72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; 75 struct dc *dc = clk_mgr_base->ctx->dc; 104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && 105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) 191 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, argument 195 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 203 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); 207 if (dm_pp_apply_power_level_change_request(clk_mgr_base [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/ |
H A D | dce120_clk_mgr.c | 84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, argument 88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { 107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); 109 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); 112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { 115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; 117 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); 119 dce11_pplib_apply_display_requirements(clk_mgr_base [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/ |
H A D | dce60_clk_mgr.c | 83 static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) argument 85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, argument 124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 132 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); 136 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) 140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { 141 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); 142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; 144 dce60_pplib_apply_display_requirements(clk_mgr_base [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/ |
H A D | dcn201_clk_mgr.c | 86 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, argument 90 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 92 struct dc *dc = clk_mgr_base->ctx->dc; 103 if (clk_mgr_base->clks.dispclk_khz == 0 || 107 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 112 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) 113 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 119 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) 120 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 123 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/ |
H A D | rv1_clk_mgr.c | 122 * , new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) || 123 * new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) 144 * for new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz, we 146 * for new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz, 148 * new_clocks->dispclk_khz and clk_mgr_base->clks.dispclk_khz, 190 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, argument 194 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 195 struct dc *dc = clk_mgr_base->ctx->dc; 227 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz 228 || new_clocks->phyclk_khz > clk_mgr_base 294 rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument [all...] |
H A D | rv1_clk_mgr_clk.c | 52 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) argument 54 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_clk_mgr.h | 45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
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H A D | dcn31_clk_mgr.c | 113 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) argument 115 struct dc *dc = clk_mgr_base->ctx->dc; 133 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, argument 138 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 140 struct dc *dc = clk_mgr_base->ctx->dc; 155 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 157 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true); 158 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 161 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 163 clk_mgr_base 289 dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 328 dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument 476 dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument 631 dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base) argument 654 dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/ |
H A D | dcn20_clk_mgr.c | 216 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, argument 220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 222 struct dc *dc = clk_mgr_base->ctx->dc; 229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 237 if (clk_mgr_base->clks.dispclk_khz == 0 || 242 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); 269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base 411 dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 425 dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) argument 493 dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) argument [all...] |
H A D | dcn20_clk_mgr.h | 56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.c | 102 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, argument 105 struct dc *dc = clk_mgr_base->ctx->dc; 128 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 135 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, argument 140 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 142 struct dc *dc = clk_mgr_base->ctx->dc; 155 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 157 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 159 clk_mgr_base 250 dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument 398 dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr.c | 86 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) argument 89 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 90 struct dc *dc = clk_mgr_base->ctx->dc; 93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 131 static void rn_update_clocks(struct clk_mgr *clk_mgr_base, argument 135 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 137 struct dc *dc = clk_mgr_base->ctx->dc; 143 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 154 if (clk_mgr_base 284 rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) argument 305 rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument 438 rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 511 rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument 544 rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
H A D | dcn314_clk_mgr.h | 46 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
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H A D | dcn314_clk_mgr.c | 134 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, argument 137 struct dc *dc = clk_mgr_base->ctx->dc; 160 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, argument 165 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 167 struct dc *dc = clk_mgr_base->ctx->dc; 182 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 184 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true); 185 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 188 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 190 clk_mgr_base 317 dcn314_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 343 dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument 491 dcn314_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.c | 100 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) argument 102 struct dc *dc = clk_mgr_base->ctx->dc; 125 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, argument 130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 132 struct dc *dc = clk_mgr_base->ctx->dc; 141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 153 if (clk_mgr_base 246 dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument 436 dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument 584 dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/ |
H A D | dce110_clk_mgr.c | 249 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, argument 253 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 261 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); 265 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) 269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { 270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); 271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; 273 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 95 static void vg_update_clocks(struct clk_mgr *clk_mgr_base, argument 99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 101 struct dc *dc = clk_mgr_base->ctx->dc; 116 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 133 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 142 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) { 143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 144 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base 216 vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base) argument 237 vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument 370 vg_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument 442 vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/ |
H A D | clk_mgr.c | 366 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) argument 368 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 371 switch (clk_mgr_base->ctx->asic_id.chip_family) { 373 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { 375 } else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { 378 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { 384 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev))
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