clk_mgr/dcn21/rn_clk_mgr.c

86 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
89 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
90 	struct dc *dc = clk_mgr_base->ctx->dc;
93 	if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
101 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
131 static void rn_update_clocks(struct clk_mgr *clk_mgr_base,
135 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
137 	struct dc *dc = clk_mgr_base->ctx->dc;
143 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
154 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
162 				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
167 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
170 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
174 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
175 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
176 		rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
180 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
181 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
182 		rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
195 		new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
196 		new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
199 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
200 		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
202 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
206 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
207 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
208 		clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
218 				clk_mgr_base->clks.dppclk_khz,
221 		clk_mgr_base->clks.actual_dppclk_khz =
222 				rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
228 				clk_mgr_base->clks.actual_dppclk_khz,
234 			clk_mgr_base->clks.actual_dppclk_khz =
235 					rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
241 				clk_mgr_base->clks.actual_dppclk_khz,
249 			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
284 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
286 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
306 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
313 	rn_dump_clk_registers_internal(&internal, clk_mgr_base);
438 static void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
440 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
511 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
513 	struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
514 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
518 		build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);
522 			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);
544 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
546 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
556 	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
557 		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
558 		rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);