1/*
2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#include "dccg.h"
28#include "clk_mgr_internal.h"
29#include "dce100/dce_clk_mgr.h"
30#include "dce110/dce110_clk_mgr.h"
31#include "dce60_clk_mgr.h"
32#include "reg_helper.h"
33#include "dmcu.h"
34#include "core_types.h"
35#include "dal_asic_id.h"
36
37/*
38 * Currently the register shifts and masks in this file are used for dce60
39 * which has no DPREFCLK_CNTL register
40 * TODO: remove this when DENTIST_DISPCLK_CNTL
41 * is moved to dccg, where it belongs
42 */
43#include "dce/dce_6_0_d.h"
44#include "dce/dce_6_0_sh_mask.h"
45
46#define REG(reg) \
47	(clk_mgr->regs->reg)
48
49#undef FN
50#define FN(reg_name, field_name) \
51	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
52
53/* set register offset */
54#define SR(reg_name)\
55	.reg_name = mm ## reg_name
56
57static const struct clk_mgr_registers disp_clk_regs = {
58		CLK_COMMON_REG_LIST_DCE60_BASE()
59};
60
61static const struct clk_mgr_shift disp_clk_shift = {
62		CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT)
63};
64
65static const struct clk_mgr_mask disp_clk_mask = {
66		CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK)
67};
68
69
70/* Max clock values for each state indexed by "enum clocks_state": */
71static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
72/* ClocksStateInvalid - should not be used */
73{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
74/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
75{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
76/* ClocksStateLow */
77{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
78/* ClocksStateNominal */
79{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
80/* ClocksStatePerformance */
81{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
82
83static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
84{
85	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
86	int dprefclk_wdivider;
87	int dp_ref_clk_khz;
88	int target_div;
89
90	/* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */
91
92	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
93	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
94	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
95
96	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
97	target_div = dentist_get_divider_from_did(dprefclk_wdivider);
98
99	/* Calculate the current DFS clock, in kHz.*/
100	dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
101		* clk_mgr->base.dentist_vco_freq_khz) / target_div;
102
103	return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
104}
105
106static void dce60_pplib_apply_display_requirements(
107	struct dc *dc,
108	struct dc_state *context)
109{
110	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
111
112	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
113
114	dce110_fill_display_configs(context, pp_display_cfg);
115
116	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
117		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
118}
119
120static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
121			struct dc_state *context,
122			bool safe_to_lower)
123{
124	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
125	struct dm_pp_power_level_change_request level_change_req;
126	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
127
128	/*TODO: W/A for dal3 linux, investigate why this works */
129	if (!clk_mgr_dce->dfs_bypass_active)
130		patched_disp_clk = patched_disp_clk * 115 / 100;
131
132	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
133	/* get max clock state from PPLIB */
134	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
135			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
136		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
137			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
138	}
139
140	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
141		patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
142		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
143	}
144	dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
145}
146
147
148
149
150
151
152
153
154static struct clk_mgr_funcs dce60_funcs = {
155	.get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
156	.update_clocks = dce60_update_clocks
157};
158
159void dce60_clk_mgr_construct(
160		struct dc_context *ctx,
161		struct clk_mgr_internal *clk_mgr)
162{
163	dce_clk_mgr_construct(ctx, clk_mgr);
164
165	memcpy(clk_mgr->max_clks_by_state,
166		dce60_max_clks_by_state,
167		sizeof(dce60_max_clks_by_state));
168
169	clk_mgr->regs = &disp_clk_regs;
170	clk_mgr->clk_mgr_shift = &disp_clk_shift;
171	clk_mgr->clk_mgr_mask = &disp_clk_mask;
172	clk_mgr->base.funcs = &dce60_funcs;
173}
174
175