Lines Matching refs:clk_mgr_base
155 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
157 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
162 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
163 clk_mgr_base->clks.p_state_change_support = true;
164 clk_mgr_base->clks.prev_p_state_change_support = true;
165 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
169 if (!clk_mgr_base->bw_params)
172 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
185 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
189 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
191 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
196 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
198 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
204 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
207 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
209 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
210 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
217 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
219 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
220 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
221 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
222 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
225 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
226 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
228 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
230 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
231 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
232 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
233 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
237 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
437 static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
439 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
454 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
458 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
460 struct dc *dc = clk_mgr_base->ctx->dc;
466 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
472 if (clk_mgr_base->clks.dispclk_khz == 0 ||
479 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
494 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
498 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
500 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
503 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
513 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
515 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
516 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
519 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
521 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
522 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
525 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
527 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
529 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
530 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
532 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
533 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
534 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
535 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
539 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) &&
541 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
544 if (!clk_mgr_base->clks.p_state_change_support) {
568 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
572 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk &&
579 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz) &&
581 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
586 if (clk_mgr_base->clks.p_state_change_support &&
587 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
591 max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
593 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
596 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
597 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
598 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
599 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
604 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
605 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
608 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
611 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
616 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
617 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
623 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
628 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
630 clk_mgr_base->clks.ref_dtbclk_khz =
632 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
641 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
657 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
685 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
687 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
780 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
783 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
806 static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
808 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
814 if (clk_mgr_base->clks.p_state_change_support)
816 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
819 clk_mgr_base->bw_params->max_memclk_mhz);
822 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
827 static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
829 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
834 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
838 static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
840 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
841 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
849 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
851 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
852 clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
858 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
860 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
867 clk_mgr_base->bw_params->max_memclk_mhz =
868 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
869 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
875 dcn32_patch_dpm_table(clk_mgr_base->bw_params);
879 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
880 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
905 static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
907 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
915 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
917 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
921 static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
923 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
931 static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
933 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);