clk_mgr/dcn31/dcn31_clk_mgr.c

113 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
115 	struct dc *dc = clk_mgr_base->ctx->dc;
133 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
138 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
140 	struct dc *dc = clk_mgr_base->ctx->dc;
155 				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
157 			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
158 			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
161 		if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
163 			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
166 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
176 				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
181 				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
183 			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
184 			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
187 		if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
189 			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
193 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
197 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
201 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
202 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
203 		dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
207 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
208 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
209 		dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
219 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
223 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
224 		dcn31_disable_otg_wa(clk_mgr_base, context, true);
226 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
227 		dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
228 		dcn31_disable_otg_wa(clk_mgr_base, context, false);
236 		dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
240 			dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
250 	cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
252 		clk_mgr_base->clks.dcfclk_deep_sleep_khz;
253 	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
254 	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
289 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
291 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
329 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
476 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
478 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
490 	dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
631 static void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
634 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
635 	struct dc *dc = clk_mgr_base->ctx->dc;
638 	if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
649 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
654 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
656 	return clk_mgr_base->clks.ref_dtbclk_khz;