Searched refs:CSR_WRITE_1 (Results 1 - 25 of 32) sorted by relevance

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/openbsd-current/sys/dev/isa/
H A Dif_ex.c140 #define CSR_WRITE_1(sc, off, value) \ macro
196 CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
301 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
304 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
306 CSR_WRITE_1(sc, I_ADDR_REG0 + i, sc->arpcom.ac_enaddr[i]);
314 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md |
316 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins |
318 CSR_WRITE_1(sc, REG3, (CSR_READ_1(sc, REG3) & 0x3f));
319 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
320 CSR_WRITE_1(s
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/openbsd-current/sys/dev/pci/
H A Dif_vge.c191 CSR_WRITE_1(sc, VGE_EEADDR, addr);
249 CSR_WRITE_1(sc, VGE_MIICMD, 0);
268 CSR_WRITE_1(sc, VGE_MIICMD, 0);
269 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
284 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
313 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
349 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
385 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
387 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
391 CSR_WRITE_1(s
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H A Dif_vgevar.h103 #define CSR_WRITE_1(sc, reg, val) \ macro
114 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
121 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
H A Dif_re_pci.c192 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
196 CSR_WRITE_1(sc, RL_CFG2, cfg);
200 CSR_WRITE_1(sc, RL_CFG2, cfg);
203 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
H A Dif_ipwreg.h291 #define CSR_WRITE_1(sc, reg, val) \ macro
309 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
H A Dif_ste.c125 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
128 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
540 CSR_WRITE_1(sc, STE_RX_MODE, rxmode);
1041 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1054 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1060 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, ETHER_MAX_DIX_LEN >> 8);
1066 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (ETHER_MAX_DIX_LEN >> 4));
1080 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1346 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
H A Dif_vr.c178 CSR_WRITE_1(sc, reg, \
182 CSR_WRITE_1(sc, reg, \
202 CSR_WRITE_1(sc, VR_MIICMD, \
206 CSR_WRITE_1(sc, VR_MIICMD, \
220 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
224 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
251 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
255 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
375 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
1403 CSR_WRITE_1(s
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H A Dif_stge.c1148 CSR_WRITE_1(sc, STGE_StationAddress0 + i,
1182 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
1185 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64);
1191 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
1192 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
1198 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
1199 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
1592 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);
H A Dif_iwireg.h470 #define CSR_WRITE_1(sc, reg, val) \ macro
487 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
H A Dif_msk.c377 CSR_WRITE_1(sc, reg, x);
756 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
757 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
760 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
762 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
827 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
834 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP);
835 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR);
841 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP);
842 CSR_WRITE_1(s
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H A Dif_wbreg.h389 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Dif_lgereg.h539 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Dif_stereg.h450 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Dif_stgereg.h51 #define CSR_WRITE_1(_sc, reg, val) \ macro
H A Dif_tlreg.h504 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Dif_vrreg.h547 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Dif_tl.c316 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
341 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
352 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
H A Dif_se.c190 #define CSR_WRITE_1(sc, reg, val) \ macro
1284 CSR_WRITE_1(sc, RxMacAddr + i, sc->sc_ac.ac_enaddr[i]);
/openbsd-current/sys/dev/ic/
H A Drtl81x9.c154 CSR_WRITE_1(sc, RL_EECMD, \
158 CSR_WRITE_1(sc, RL_EECMD, \
199 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
206 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
221 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
253 CSR_WRITE_1(sc, RL_MII, \
257 CSR_WRITE_1(sc, RL_MII, \
495 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
922 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
927 CSR_WRITE_1(s
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H A Dre.c212 CSR_WRITE_1(sc, RL_EECMD, \
216 CSR_WRITE_1(sc, RL_EECMD, \
642 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
653 CSR_WRITE_1(sc, RL_LDPS, 1);
1052 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1054 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1808 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
1921 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1936 CSR_WRITE_1(sc, RL_LEDSEL, RL_LED_LINK | RL_LED_ACT << 4);
1941 CSR_WRITE_1(s
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H A Dmtd8xxreg.h201 #define CSR_WRITE_1(reg, val) \ macro
H A Dxl.c480 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
482 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
746 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
749 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1377 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
1390 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
1416 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
1885 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
1920 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
1961 CSR_WRITE_1(s
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H A Drtl81x9reg.h964 #define CSR_WRITE_1(sc, csr, val) \ macro
975 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
978 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
H A Dif_wireg.h90 #define CSR_WRITE_1(sc, reg, val) \ macro
H A Dxlreg.h647 #define CSR_WRITE_1(sc, reg, val) \ macro

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