Lines Matching refs:CSR_WRITE_1
191 CSR_WRITE_1(sc, VGE_EEADDR, addr);
249 CSR_WRITE_1(sc, VGE_MIICMD, 0);
268 CSR_WRITE_1(sc, VGE_MIICMD, 0);
269 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
284 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
313 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
349 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
385 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
387 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
391 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
393 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
395 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
415 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
419 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
449 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
516 CSR_WRITE_1(sc, VGE_RXCTL, rxctl);
524 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
534 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
1201 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1253 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1278 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1279 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1297 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1478 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1515 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1558 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1559 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1565 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_GIANT);
1578 CSR_WRITE_1(sc, VGE_CRC2, 0xFF);
1579 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);
1584 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
1585 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
1586 CSR_WRITE_1(sc, VGE_CRS0,
1605 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
1609 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
1612 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
1613 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
1618 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
1630 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1718 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |
1721 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_TXFLOWCTL_ENABLE);
1723 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_RXFLOWCTL_ENABLE);
1809 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1810 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
1813 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);