Searched refs:timings (Results 1 - 25 of 28) sorted by relevance

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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/
H A Dfbmon.c225 printk("fbmon: trying to fix monitor timings\n");
1112 static void fb_timings_vfreq(struct __fb_timings *timings) argument
1114 timings->hfreq = fb_get_hfreq(timings->vfreq, timings->vactive);
1115 timings->vblank = fb_get_vblank(timings->hfreq);
1116 timings->vtotal = timings->vactive + timings
1123 fb_timings_hfreq(struct __fb_timings *timings) argument
1134 fb_timings_dclk(struct __fb_timings *timings) argument
1181 struct __fb_timings *timings; local
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H A Dneofb.c267 struct neofb_par *par, struct xtimings *timings)
271 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
274 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
289 par->CRTC[0] = (timings->HTotal >> 3) - 5;
290 par->CRTC[1] = (timings->HDisplay >> 3) - 1;
291 par->CRTC[2] = (timings->HDisplay >> 3) - 1;
292 par->CRTC[3] = (((timings->HTotal >> 3) - 1) & 0x1F) | 0x80;
293 par->CRTC[4] = (timings->HSyncStart >> 3);
294 par->CRTC[5] = ((((timings->HTotal >> 3) - 1) & 0x20) << 2)
295 | (((timings
265 vgaHWInit(const struct fb_var_screeninfo *var, const struct fb_info *info, struct neofb_par *par, struct xtimings *timings) argument
576 struct xtimings timings; local
743 struct xtimings timings; local
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ide/pci/
H A Dsc1200.c50 * have the register with the fast PCI bus timings.
83 * Here are the standard PIO mode 0-4 timings for each "format".
84 * Format-0 uses fast data reg timings, with slower command reg timings.
85 * Format-1 uses fast timings for all registers, but won't work with all drives.
94 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
96 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
115 * different timings can still be chosen for each drive. We could
145 unsigned int reg, timings; local
415 unsigned int pio, timings; local
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H A Dcs5530.c50 * Here are the standard PIO mode 0-4 timings for each "format".
51 * Format-0 uses fast data reg timings, with slower command reg timings.
52 * Format-1 uses fast timings for all registers, but won't work with all drives.
60 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
62 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
80 * will have valid default PIO timings set up before we get here.
100 * different timings can still be chosen for each drive. We could
149 unsigned int reg, timings local
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H A Dit8213.c78 static const u8 timings[][2]= { local
103 slave_data = slave_data | (timings[pio][0] << 2) | timings[pio][1];
108 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
117 * it8213_tune_chipset - set controller timings
H A Dslc90e66.c63 static const u8 timings[][2]= { local
88 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
96 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
H A Dcs5535.c51 /* Format I PIO settings. We seperate out cmd and data for safer timings */
67 #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
68 #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
84 /* Set the PIO timings */
110 /* Set bit 31 of the DMA register for PIO format 1 timings */
221 /* just setting autotune and not worrying about bios timings */
H A Dpiix.c166 static const u8 timings[][2]= { local
196 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
204 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ata/
H A Dpata_efar.c83 * efar_set_piomode - Initialize host controller PATA PIO timings
84 * @ap: Port whose timings we are configuring
107 u8 timings[][2] = { { 0, 0 }, local
128 idetm_data |= (timings[pio][0] << 12) |
129 (timings[pio][1] << 8);
140 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
149 * efar_set_dmamode - Initialize host controller PATA DMA timings
150 * @ap: Port whose timings we are configuring
169 u8 timings[][ local
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H A Dpata_it8213.c77 * it8213_set_piomode - Initialize host controller PATA PIO timings
78 * @ap: Port whose timings we are configuring
79 * @adev: Device whose timings we are configuring
101 u8 timings[][2] = { { 0, 0 }, local
122 idetm_data |= (timings[pio][0] << 12) |
123 (timings[pio][1] << 8);
133 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << 4;
142 * it8213_set_dmamode - Initialize host controller PATA DMA timings
143 * @ap: Port whose timings w
162 u8 timings[][2] = { { 0, 0 }, local
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H A Dpata_cs5535.c70 #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )
236 u32 timings, dummy; local
239 timings for PIO0 */
240 rdmsr(ATAC_CH0D0_PIO, timings, dummy);
241 if (CS5535_BAD_PIO(timings))
243 rdmsr(ATAC_CH0D1_PIO, timings, dummy);
244 if (CS5535_BAD_PIO(timings))
H A Dpata_oldpiix.c11 * does drive selection and we use this to reload the timings.
67 * oldpiix_set_piomode - Initialize host controller PATA PIO timings
68 * @ap: Port whose timings we are configuring
69 * @adev: Device whose timings we are configuring
92 u8 timings[][2] = { { 0, 0 }, local
120 idetm_data |= (timings[pio][0] << 12) |
121 (timings[pio][1] << 8);
129 * oldpiix_set_dmamode - Initialize host controller PATA DMA timings
130 * @ap: Port whose timings we are configuring
147 u8 timings[][ local
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H A Dpata_radisys.c9 * slave timings, SITRE or PPE. In that sense it is a close relative
11 * although no other modes/timings. Also lacking is 32bit I/O on the ATA
30 * radisys_set_piomode - Initialize host controller PATA PIO timings
32 * @adev: Device whose timings we are configuring
55 u8 timings[][2] = { { 0, 0 }, /* Check me */ local
72 idetm_data |= (timings[pio][0] << 12) |
73 (timings[pio][1] << 8);
81 * radisys_set_dmamode - Initialize host controller PATA DMA timings
82 * @ap: Port whose timings we are configuring
99 u8 timings[][ local
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H A Dpata_sc1200.c113 * We cannot mix MWDMA and UDMA without reloading timings each switch
143 u32 timings; local
145 pci_read_config_dword(pdev, reg + 4, &timings);
146 timings &= 0x80000000UL;
147 timings |= format;
148 pci_write_config_dword(pdev, reg + 4, timings);
158 * this interface so that we can load the correct ATA timings if
H A Dpata_mpiix.c12 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
86 * flip the timings back and forth to reduce the pain.
96 u8 timings[][2] = { { 0, 0 }, local
117 idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
130 * this interface so that we can load the correct ATA timings if
H A Data_piix.c47 * series chipsets do _not_ support independant device timings, but this
645 * piix_set_piomode - Initialize host controller PATA PIO timings
646 * @ap: Port whose timings we are configuring
673 u8 timings[][2] = { { 0, 0 }, local
697 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
704 (timings[pio][0] << 12) |
705 (timings[pio][1] << 8);
722 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
723 * @ap: Port whose timings w
744 u8 timings[][2] = { { 0, 0 }, local
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H A Dpata_mpc52xx.c40 struct mpc52xx_ata_timings timings[2]; member in struct:mpc52xx_ata_priv
147 struct mpc52xx_ata_timings *timing = &priv->timings[dev];
172 struct mpc52xx_ata_timings *timing = &priv->timings[device];
213 /* Init timings to PIO0 */
214 memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ide/ppc/
H A Dpmac.c68 u32 timings[4]; member in struct:pmac_ide_hwif
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
201 * is used to reach long timings used in this mode.
231 /* Rounded Multiword DMA timings
282 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
296 /* UniNorth 2 ATA/100 timings */
460 * Apply the timings of the proper unit (master/slave) to the shared
473 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
475 writel(pmif->timings[
619 u32 *timings; local
707 set_timings_udma_ata4(u32 *timings, u8 speed) argument
775 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, u8 speed, int drive_cycle_time) argument
925 u32 *timings, *timings2; local
1693 u32 *timings, *timings2; local
1748 u32 *timings, *timings2; local
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/openssl-0.9.8e/crypto/ec/
H A Dectest.c119 static void timings(EC_GROUP *group, int type, BN_CTX *ctx)
715 timings(P_160, TIMING_BASE_PT, ctx);
716 timings(P_160, TIMING_RAND_PT, ctx);
717 timings(P_160, TIMING_SIMUL, ctx);
718 timings(P_192, TIMING_BASE_PT, ctx);
719 timings(P_192, TIMING_RAND_PT, ctx);
720 timings(P_192, TIMING_SIMUL, ctx);
721 timings(P_224, TIMING_BASE_PT, ctx);
722 timings(P_224, TIMING_RAND_PT, ctx);
723 timings(P_22
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/openssl-0.9.8e/test/
H A Dectest.c119 static void timings(EC_GROUP *group, int type, BN_CTX *ctx)
715 timings(P_160, TIMING_BASE_PT, ctx);
716 timings(P_160, TIMING_RAND_PT, ctx);
717 timings(P_160, TIMING_SIMUL, ctx);
718 timings(P_192, TIMING_BASE_PT, ctx);
719 timings(P_192, TIMING_RAND_PT, ctx);
720 timings(P_192, TIMING_SIMUL, ctx);
721 timings(P_224, TIMING_BASE_PT, ctx);
722 timings(P_224, TIMING_RAND_PT, ctx);
723 timings(P_22
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/savage/
H A Dsavagefb_driver.c152 struct xtimings *timings,
157 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
160 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
175 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
176 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
177 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
178 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
179 reg->CRTC[0x04] = (timings->HSyncStart >> 3);
180 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
181 (((timings
150 vgaHWInit(struct fb_var_screeninfo *var, struct savagefb_par *par, struct xtimings *timings, struct savage_reg *reg) argument
977 struct xtimings timings; local
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/openssl/test/
H A Dectest.c86 static void timings(EC_GROUP *group, int multi, BN_CTX *ctx)
605 timings(P_192, 0, ctx);
606 timings(P_192, 1, ctx);
607 timings(P_224, 0, ctx);
608 timings(P_224, 1, ctx);
609 timings(P_256, 0, ctx);
610 timings(P_256, 1, ctx);
611 timings(P_384, 0, ctx);
612 timings(P_384, 1, ctx);
613 timings(P_52
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/openssl/crypto/ec/
H A Dectest.c86 static void timings(EC_GROUP *group, int multi, BN_CTX *ctx)
605 timings(P_192, 0, ctx);
606 timings(P_192, 1, ctx);
607 timings(P_224, 0, ctx);
608 timings(P_224, 1, ctx);
609 timings(P_256, 0, ctx);
610 timings(P_256, 1, ctx);
611 timings(P_384, 0, ctx);
612 timings(P_384, 1, ctx);
613 timings(P_52
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ide/legacy/
H A Dqd65xx.c90 static int timings[4]={-1,-1,-1,-1}; /* stores current timing for each timer */ variable
123 if (timings[index] != QD_TIMING(drive))
124 qd_write_reg(timings[index] = QD_TIMING(drive), QD_TIMREG(drive));
195 * check whether timings don't conflict
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-omap/
H A Domapfb.h251 int (*convert_timings) (struct extif_timings *timings);
252 void (*set_timings) (const struct extif_timings *timings);

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