1/* 2 * linux/drivers/ide/pci/sc1200.c Version 0.94 Mar 10 2007 3 * 4 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> 5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 6 * 7 * May be copied or modified under the terms of the GNU General Public License 8 * 9 * Development of this chipset driver was funded 10 * by the nice folks at National Semiconductor. 11 * 12 * Documentation: 13 * Available from National Semiconductor 14 */ 15 16#include <linux/module.h> 17#include <linux/types.h> 18#include <linux/kernel.h> 19#include <linux/delay.h> 20#include <linux/timer.h> 21#include <linux/mm.h> 22#include <linux/ioport.h> 23#include <linux/blkdev.h> 24#include <linux/hdreg.h> 25#include <linux/interrupt.h> 26#include <linux/pci.h> 27#include <linux/init.h> 28#include <linux/ide.h> 29#include <linux/pm.h> 30#include <asm/io.h> 31#include <asm/irq.h> 32 33#define SC1200_REV_A 0x00 34#define SC1200_REV_B1 0x01 35#define SC1200_REV_B3 0x02 36#define SC1200_REV_C1 0x03 37#define SC1200_REV_D1 0x04 38 39#define PCI_CLK_33 0x00 40#define PCI_CLK_48 0x01 41#define PCI_CLK_66 0x02 42#define PCI_CLK_33A 0x03 43 44static unsigned short sc1200_get_pci_clock (void) 45{ 46 unsigned char chip_id, silicon_revision; 47 unsigned int pci_clock; 48 /* 49 * Check the silicon revision, as not all versions of the chip 50 * have the register with the fast PCI bus timings. 51 */ 52 chip_id = inb (0x903c); 53 silicon_revision = inb (0x903d); 54 55 // Read the fast pci clock frequency 56 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) { 57 pci_clock = PCI_CLK_33; 58 } else { 59 // check clock generator configuration (cfcc) 60 // the clock is in bits 8 and 9 of this word 61 62 pci_clock = inw (0x901e); 63 pci_clock >>= 8; 64 pci_clock &= 0x03; 65 if (pci_clock == PCI_CLK_33A) 66 pci_clock = PCI_CLK_33; 67 } 68 return pci_clock; 69} 70 71extern char *ide_xfer_verbose (byte xfer_rate); 72 73/* 74 * Set a new transfer mode at the drive 75 */ 76static int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode) 77{ 78 printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode)); 79 return ide_config_drive_speed(drive, mode); 80} 81 82/* 83 * Here are the standard PIO mode 0-4 timings for each "format". 84 * Format-0 uses fast data reg timings, with slower command reg timings. 85 * Format-1 uses fast timings for all registers, but won't work with all drives. 86 */ 87static const unsigned int sc1200_pio_timings[4][5] = 88 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz 89 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz 90 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz 91 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz 92 93/* 94 * After chip reset, the PIO timings are set to 0x00009172, which is not valid. 95 */ 96//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172) 97 98static void sc1200_tunepio(ide_drive_t *drive, u8 pio) 99{ 100 ide_hwif_t *hwif = drive->hwif; 101 struct pci_dev *pdev = hwif->pci_dev; 102 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; 103 104 pci_read_config_dword(pdev, basereg + 4, &format); 105 format = (format >> 31) & 1; 106 if (format) 107 format += sc1200_get_pci_clock(); 108 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3), 109 sc1200_pio_timings[format][pio]); 110} 111 112/* 113 * The SC1200 specifies that two drives sharing a cable cannot mix 114 * UDMA/MDMA. It has to be one or the other, for the pair, though 115 * different timings can still be chosen for each drive. We could 116 * set the appropriate timing bits on the fly, but that might be 117 * a bit confusing. So, for now we statically handle this requirement 118 * by looking at our mate drive to see what it is capable of, before 119 * choosing a mode for our own drive. 120 */ 121static u8 sc1200_udma_filter(ide_drive_t *drive) 122{ 123 ide_hwif_t *hwif = drive->hwif; 124 ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1]; 125 struct hd_driveid *mateid = mate->id; 126 u8 mask = hwif->ultra_mask; 127 128 if (mate->present == 0) 129 goto out; 130 131 if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) { 132 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7)) 133 goto out; 134 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7)) 135 mask = 0; 136 } 137out: 138 return mask; 139} 140 141static int sc1200_tune_chipset(ide_drive_t *drive, u8 mode) 142{ 143 ide_hwif_t *hwif = HWIF(drive); 144 int unit = drive->select.b.unit; 145 unsigned int reg, timings; 146 unsigned short pci_clock; 147 unsigned int basereg = hwif->channel ? 0x50 : 0x40; 148 149 mode = ide_rate_filter(drive, mode); 150 151 /* 152 * Tell the drive to switch to the new mode; abort on failure. 153 */ 154 if (sc1200_set_xfer_mode(drive, mode)) { 155 printk("SC1200: set xfer mode failure\n"); 156 return 1; /* failure */ 157 } 158 159 switch (mode) { 160 case XFER_PIO_4: 161 case XFER_PIO_3: 162 case XFER_PIO_2: 163 case XFER_PIO_1: 164 case XFER_PIO_0: 165 sc1200_tunepio(drive, mode - XFER_PIO_0); 166 return 0; 167 } 168 169 pci_clock = sc1200_get_pci_clock(); 170 171 /* 172 * Now tune the chipset to match the drive: 173 * 174 * Note that each DMA mode has several timings associated with it. 175 * The correct timing depends on the fast PCI clock freq. 176 */ 177 timings = 0; 178 switch (mode) { 179 case XFER_UDMA_0: 180 switch (pci_clock) { 181 case PCI_CLK_33: timings = 0x00921250; break; 182 case PCI_CLK_48: timings = 0x00932470; break; 183 case PCI_CLK_66: timings = 0x009436a1; break; 184 } 185 break; 186 case XFER_UDMA_1: 187 switch (pci_clock) { 188 case PCI_CLK_33: timings = 0x00911140; break; 189 case PCI_CLK_48: timings = 0x00922260; break; 190 case PCI_CLK_66: timings = 0x00933481; break; 191 } 192 break; 193 case XFER_UDMA_2: 194 switch (pci_clock) { 195 case PCI_CLK_33: timings = 0x00911030; break; 196 case PCI_CLK_48: timings = 0x00922140; break; 197 case PCI_CLK_66: timings = 0x00923261; break; 198 } 199 break; 200 case XFER_MW_DMA_0: 201 switch (pci_clock) { 202 case PCI_CLK_33: timings = 0x00077771; break; 203 case PCI_CLK_48: timings = 0x000bbbb2; break; 204 case PCI_CLK_66: timings = 0x000ffff3; break; 205 } 206 break; 207 case XFER_MW_DMA_1: 208 switch (pci_clock) { 209 case PCI_CLK_33: timings = 0x00012121; break; 210 case PCI_CLK_48: timings = 0x00024241; break; 211 case PCI_CLK_66: timings = 0x00035352; break; 212 } 213 break; 214 case XFER_MW_DMA_2: 215 switch (pci_clock) { 216 case PCI_CLK_33: timings = 0x00002020; break; 217 case PCI_CLK_48: timings = 0x00013131; break; 218 case PCI_CLK_66: timings = 0x00015151; break; 219 } 220 break; 221 default: 222 BUG(); 223 break; 224 } 225 226 if (unit == 0) { /* are we configuring drive0? */ 227 pci_read_config_dword(hwif->pci_dev, basereg+4, ®); 228 timings |= reg & 0x80000000; /* preserve PIO format bit */ 229 pci_write_config_dword(hwif->pci_dev, basereg+4, timings); 230 } else { 231 pci_write_config_dword(hwif->pci_dev, basereg+12, timings); 232 } 233 234 return 0; /* success */ 235} 236 237/* 238 * sc1200_config_dma() handles selection/setting of DMA/UDMA modes 239 * for both the chipset and drive. 240 */ 241static int sc1200_config_dma (ide_drive_t *drive) 242{ 243 if (ide_tune_dma(drive)) 244 return 0; 245 246 return 1; 247} 248 249 250/* Replacement for the standard ide_dma_end action in 251 * dma_proc. 252 * 253 * returns 1 on error, 0 otherwise 254 */ 255static int sc1200_ide_dma_end (ide_drive_t *drive) 256{ 257 ide_hwif_t *hwif = HWIF(drive); 258 unsigned long dma_base = hwif->dma_base; 259 byte dma_stat; 260 261 dma_stat = inb(dma_base+2); /* get DMA status */ 262 263 if (!(dma_stat & 4)) 264 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n", 265 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2)); 266 267 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */ 268 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ 269 270 drive->waiting_for_dma = 0; 271 ide_destroy_dmatable(drive); /* purge DMA mappings */ 272 273 return (dma_stat & 7) != 4; /* verify good DMA status */ 274} 275 276/* 277 * sc1200_tuneproc() handles selection/setting of PIO modes 278 * for both the chipset and drive. 279 * 280 * All existing BIOSs for this chipset guarantee that all drives 281 * will have valid default PIO timings set up before we get here. 282 */ 283static void sc1200_tuneproc (ide_drive_t *drive, byte pio) /* mode=255 means "autotune" */ 284{ 285 ide_hwif_t *hwif = HWIF(drive); 286 int mode = -1; 287 288 /* 289 * bad abuse of ->tuneproc interface 290 */ 291 switch (pio) { 292 case 200: mode = XFER_UDMA_0; break; 293 case 201: mode = XFER_UDMA_1; break; 294 case 202: mode = XFER_UDMA_2; break; 295 case 100: mode = XFER_MW_DMA_0; break; 296 case 101: mode = XFER_MW_DMA_1; break; 297 case 102: mode = XFER_MW_DMA_2; break; 298 } 299 if (mode != -1) { 300 printk("SC1200: %s: changing (U)DMA mode\n", drive->name); 301 hwif->dma_off_quietly(drive); 302 if (sc1200_tune_chipset(drive, mode) == 0) 303 hwif->dma_host_on(drive); 304 return; 305 } 306 307 pio = ide_get_best_pio_mode(drive, pio, 4, NULL); 308 printk("SC1200: %s: setting PIO mode%d\n", drive->name, pio); 309 310 if (sc1200_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0) 311 sc1200_tunepio(drive, pio); 312} 313 314#ifdef CONFIG_PM 315static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev) 316{ 317 int h; 318 319 for (h = 0; h < MAX_HWIFS; h++) { 320 ide_hwif_t *hwif = &ide_hwifs[h]; 321 if (prev) { 322 if (hwif == prev) 323 prev = NULL; // found previous, now look for next match 324 } else { 325 if (hwif && hwif->pci_dev == dev) 326 return hwif; // found next match 327 } 328 } 329 return NULL; // not found 330} 331 332typedef struct sc1200_saved_state_s { 333 __u32 regs[4]; 334} sc1200_saved_state_t; 335 336 337static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) 338{ 339 ide_hwif_t *hwif = NULL; 340 341 printk("SC1200: suspend(%u)\n", state.event); 342 343 if (state.event == PM_EVENT_ON) { 344 // we only save state when going from full power to less 345 346 // 347 // Loop over all interfaces that are part of this PCI device: 348 // 349 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { 350 sc1200_saved_state_t *ss; 351 unsigned int basereg, r; 352 // 353 // allocate a permanent save area, if not already allocated 354 // 355 ss = (sc1200_saved_state_t *)hwif->config_data; 356 if (ss == NULL) { 357 ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL); 358 if (ss == NULL) 359 return -ENOMEM; 360 hwif->config_data = (unsigned long)ss; 361 } 362 ss = (sc1200_saved_state_t *)hwif->config_data; 363 // 364 // Save timing registers: this may be unnecessary if 365 // BIOS also does it 366 // 367 basereg = hwif->channel ? 0x50 : 0x40; 368 for (r = 0; r < 4; ++r) { 369 pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]); 370 } 371 } 372 } 373 374 /* You don't need to iterate over disks -- sysfs should have done that for you already */ 375 376 pci_disable_device(dev); 377 pci_set_power_state(dev, pci_choose_state(dev, state)); 378 dev->current_state = state.event; 379 return 0; 380} 381 382static int sc1200_resume (struct pci_dev *dev) 383{ 384 ide_hwif_t *hwif = NULL; 385 386 pci_set_power_state(dev, PCI_D0); // bring chip back from sleep state 387 dev->current_state = PM_EVENT_ON; 388 pci_enable_device(dev); 389 // 390 // loop over all interfaces that are part of this pci device: 391 // 392 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { 393 unsigned int basereg, r, d, format; 394 sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data; 395 396 // 397 // Restore timing registers: this may be unnecessary if BIOS also does it 398 // 399 basereg = hwif->channel ? 0x50 : 0x40; 400 if (ss != NULL) { 401 for (r = 0; r < 4; ++r) { 402 pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]); 403 } 404 } 405 // 406 // Re-program drive PIO modes 407 // 408 pci_read_config_dword(hwif->pci_dev, basereg+4, &format); 409 format = (format >> 31) & 1; 410 if (format) 411 format += sc1200_get_pci_clock(); 412 for (d = 0; d < 2; ++d) { 413 ide_drive_t *drive = &(hwif->drives[d]); 414 if (drive->present) { 415 unsigned int pio, timings; 416 pci_read_config_dword(hwif->pci_dev, basereg+(drive->select.b.unit << 3), &timings); 417 for (pio = 0; pio <= 4; ++pio) { 418 if (sc1200_pio_timings[format][pio] == timings) 419 break; 420 } 421 if (pio > 4) 422 pio = 255; /* autotune */ 423 (void)sc1200_tuneproc(drive, pio); 424 } 425 } 426 // 427 // Re-program drive DMA modes 428 // 429 for (d = 0; d < MAX_DRIVES; ++d) { 430 ide_drive_t *drive = &(hwif->drives[d]); 431 if (drive->present && !__ide_dma_bad_drive(drive)) { 432 int enable_dma = drive->using_dma; 433 hwif->dma_off_quietly(drive); 434 if (sc1200_config_dma(drive)) 435 enable_dma = 0; 436 if (enable_dma) 437 hwif->dma_host_on(drive); 438 } 439 } 440 } 441 return 0; 442} 443#endif 444 445/* 446 * This gets invoked by the IDE driver once for each channel, 447 * and performs channel-specific pre-initialization before drive probing. 448 */ 449static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif) 450{ 451 if (hwif->mate) 452 hwif->serialized = hwif->mate->serialized = 1; 453 hwif->autodma = 0; 454 if (hwif->dma_base) { 455 hwif->udma_filter = sc1200_udma_filter; 456 hwif->ide_dma_check = &sc1200_config_dma; 457 hwif->ide_dma_end = &sc1200_ide_dma_end; 458 if (!noautodma) 459 hwif->autodma = 1; 460 hwif->tuneproc = &sc1200_tuneproc; 461 hwif->speedproc = &sc1200_tune_chipset; 462 } 463 hwif->atapi_dma = 1; 464 hwif->ultra_mask = 0x07; 465 hwif->mwdma_mask = 0x07; 466 467 hwif->drives[0].autodma = hwif->autodma; 468 hwif->drives[1].autodma = hwif->autodma; 469} 470 471static ide_pci_device_t sc1200_chipset __devinitdata = { 472 .name = "SC1200", 473 .init_hwif = init_hwif_sc1200, 474 .channels = 2, 475 .autodma = AUTODMA, 476 .bootable = ON_BOARD, 477}; 478 479static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) 480{ 481 return ide_setup_pci_device(dev, &sc1200_chipset); 482} 483 484static struct pci_device_id sc1200_pci_tbl[] = { 485 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0}, 486 { 0, }, 487}; 488MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl); 489 490static struct pci_driver driver = { 491 .name = "SC1200_IDE", 492 .id_table = sc1200_pci_tbl, 493 .probe = sc1200_init_one, 494#ifdef CONFIG_PM 495 .suspend = sc1200_suspend, 496 .resume = sc1200_resume, 497#endif 498}; 499 500static int __init sc1200_ide_init(void) 501{ 502 return ide_pci_register_driver(&driver); 503} 504 505module_init(sc1200_ide_init); 506 507MODULE_AUTHOR("Mark Lord"); 508MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE"); 509MODULE_LICENSE("GPL"); 510