1/*
2 * pata_mpiix.c 	- Intel MPIIX PATA for new ATA layer
3 *			  (C) 2005-2006 Red Hat Inc
4 *			  Alan Cox <alan@redhat.com>
5 *
6 * The MPIIX is different enough to the PIIX4 and friends that we give it
7 * a separate driver. The old ide/pci code handles this by just not tuning
8 * MPIIX at all.
9 *
10 * The MPIIX also differs in another important way from the majority of PIIX
11 * devices. The chip is a bridge (pardon the pun) between the old world of
12 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
13 * IDE controller is not decoded in PCI space and the chip does not claim to
14 * be IDE class PCI. This requires slightly non-standard probe logic compared
15 * with PCI IDE and also that we do not disable the device when our driver is
16 * unloaded (as it has many other functions).
17 *
18 * The driver conciously keeps this logic internally to avoid pushing quirky
19 * PATA history into the clean libata layer.
20 *
21 * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
22 * hard disk present this driver will not detect it. This is not a bug. In this
23 * configuration the secondary port of the MPIIX is disabled and the addresses
24 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
25 * to operate.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/init.h>
32#include <linux/blkdev.h>
33#include <linux/delay.h>
34#include <scsi/scsi_host.h>
35#include <linux/libata.h>
36
37#define DRV_NAME "pata_mpiix"
38#define DRV_VERSION "0.7.6"
39
40enum {
41	IDETIM = 0x6C,		/* IDE control register */
42	IORDY = (1 << 1),
43	PPE = (1 << 2),
44	FTIM = (1 << 0),
45	ENABLED = (1 << 15),
46	SECONDARY = (1 << 14)
47};
48
49static int mpiix_pre_reset(struct ata_port *ap, unsigned long deadline)
50{
51	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
52	static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
53
54	if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
55		return -ENOENT;
56
57	return ata_std_prereset(ap, deadline);
58}
59
60/**
61 *	mpiix_error_handler		-	probe reset
62 *	@ap: ATA port
63 *
64 *	Perform the ATA probe and bus reset sequence plus specific handling
65 *	for this hardware. The MPIIX has the enable bits in a different place
66 *	to PIIX4 and friends. As a pure PIO device it has no cable detect
67 */
68
69static void mpiix_error_handler(struct ata_port *ap)
70{
71	ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
72}
73
74/**
75 *	mpiix_set_piomode	-	set initial PIO mode data
76 *	@ap: ATA interface
77 *	@adev: ATA device
78 *
79 *	Called to do the PIO mode setup. The MPIIX allows us to program the
80 *	IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
81 *	prefetching or IORDY are used.
82 *
83 *	This would get very ugly because we can only program timing for one
84 *	device at a time, the other gets PIO0. Fortunately libata calls
85 *	our qc_issue_prot command before a command is issued so we can
86 *	flip the timings back and forth to reduce the pain.
87 */
88
89static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
90{
91	int control = 0;
92	int pio = adev->pio_mode - XFER_PIO_0;
93	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
94	u16 idetim;
95	static const	 /* ISP  RTC */
96	u8 timings[][2]	= { { 0, 0 },
97			    { 0, 0 },
98			    { 1, 0 },
99			    { 2, 1 },
100			    { 2, 3 }, };
101
102	pci_read_config_word(pdev, IDETIM, &idetim);
103
104	/* Mask the IORDY/TIME/PPE for this device */
105	if (adev->class == ATA_DEV_ATA)
106		control |= PPE;		/* Enable prefetch/posting for disk */
107	if (ata_pio_need_iordy(adev))
108		control |= IORDY;
109	if (pio > 1)
110		control |= FTIM;	/* This drive is on the fast timing bank */
111
112	/* Mask out timing and clear both TIME bank selects */
113	idetim &= 0xCCEE;
114	idetim &= ~(0x07  << (4 * adev->devno));
115	idetim |= control << (4 * adev->devno);
116
117	idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
118	pci_write_config_word(pdev, IDETIM, idetim);
119
120	/* We use ap->private_data as a pointer to the device currently
121	   loaded for timing */
122	ap->private_data = adev;
123}
124
125/**
126 *	mpiix_qc_issue_prot	-	command issue
127 *	@qc: command pending
128 *
129 *	Called when the libata layer is about to issue a command. We wrap
130 *	this interface so that we can load the correct ATA timings if
131 *	neccessary. Our logic also clears TIME0/TIME1 for the other device so
132 *	that, even if we get this wrong, cycles to the other device will
133 *	be made PIO0.
134 */
135
136static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
137{
138	struct ata_port *ap = qc->ap;
139	struct ata_device *adev = qc->dev;
140
141	/* If modes have been configured and the channel data is not loaded
142	   then load it. We have to check if pio_mode is set as the core code
143	   does not set adev->pio_mode to XFER_PIO_0 while probing as would be
144	   logical */
145
146	if (adev->pio_mode && adev != ap->private_data)
147		mpiix_set_piomode(ap, adev);
148
149	return ata_qc_issue_prot(qc);
150}
151
152static struct scsi_host_template mpiix_sht = {
153	.module			= THIS_MODULE,
154	.name			= DRV_NAME,
155	.ioctl			= ata_scsi_ioctl,
156	.queuecommand		= ata_scsi_queuecmd,
157	.can_queue		= ATA_DEF_QUEUE,
158	.this_id		= ATA_SHT_THIS_ID,
159	.sg_tablesize		= LIBATA_MAX_PRD,
160	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
161	.emulated		= ATA_SHT_EMULATED,
162	.use_clustering		= ATA_SHT_USE_CLUSTERING,
163	.proc_name		= DRV_NAME,
164	.dma_boundary		= ATA_DMA_BOUNDARY,
165	.slave_configure	= ata_scsi_slave_config,
166	.slave_destroy		= ata_scsi_slave_destroy,
167	.bios_param		= ata_std_bios_param,
168};
169
170static struct ata_port_operations mpiix_port_ops = {
171	.port_disable	= ata_port_disable,
172	.set_piomode	= mpiix_set_piomode,
173
174	.tf_load	= ata_tf_load,
175	.tf_read	= ata_tf_read,
176	.check_status 	= ata_check_status,
177	.exec_command	= ata_exec_command,
178	.dev_select 	= ata_std_dev_select,
179
180	.freeze		= ata_bmdma_freeze,
181	.thaw		= ata_bmdma_thaw,
182	.error_handler	= mpiix_error_handler,
183	.post_internal_cmd = ata_bmdma_post_internal_cmd,
184	.cable_detect	= ata_cable_40wire,
185
186	.qc_prep 	= ata_qc_prep,
187	.qc_issue	= mpiix_qc_issue_prot,
188	.data_xfer	= ata_data_xfer,
189
190	.irq_clear	= ata_bmdma_irq_clear,
191	.irq_on		= ata_irq_on,
192	.irq_ack	= ata_irq_ack,
193
194	.port_start	= ata_port_start,
195};
196
197static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
198{
199	/* Single threaded by the PCI probe logic */
200	static int printed_version;
201	struct ata_host *host;
202	struct ata_port *ap;
203	void __iomem *cmd_addr, *ctl_addr;
204	u16 idetim;
205	int irq;
206
207	if (!printed_version++)
208		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
209
210	host = ata_host_alloc(&dev->dev, 1);
211	if (!host)
212		return -ENOMEM;
213
214	/* MPIIX has many functions which can be turned on or off according
215	   to other devices present. Make sure IDE is enabled before we try
216	   and use it */
217
218	pci_read_config_word(dev, IDETIM, &idetim);
219	if (!(idetim & ENABLED))
220		return -ENODEV;
221
222	/* See if it's primary or secondary channel... */
223	if (!(idetim & SECONDARY)) {
224		irq = 14;
225		cmd_addr = devm_ioport_map(&dev->dev, 0x1F0, 8);
226		ctl_addr = devm_ioport_map(&dev->dev, 0x3F6, 1);
227	} else {
228		irq = 15;
229		cmd_addr = devm_ioport_map(&dev->dev, 0x170, 8);
230		ctl_addr = devm_ioport_map(&dev->dev, 0x376, 1);
231	}
232
233	if (!cmd_addr || !ctl_addr)
234		return -ENOMEM;
235
236	/* We do our own plumbing to avoid leaking special cases for whacko
237	   ancient hardware into the core code. There are two issues to
238	   worry about.  #1 The chip is a bridge so if in legacy mode and
239	   without BARs set fools the setup.  #2 If you pci_disable_device
240	   the MPIIX your box goes castors up */
241
242	ap = host->ports[0];
243	ap->ops = &mpiix_port_ops;
244	ap->pio_mask = 0x1F;
245	ap->flags |= ATA_FLAG_SLAVE_POSS;
246
247	ap->ioaddr.cmd_addr = cmd_addr;
248	ap->ioaddr.ctl_addr = ctl_addr;
249	ap->ioaddr.altstatus_addr = ctl_addr;
250
251	/* Let libata fill in the port details */
252	ata_std_ports(&ap->ioaddr);
253
254	/* activate host */
255	return ata_host_activate(host, irq, ata_interrupt, IRQF_SHARED,
256				 &mpiix_sht);
257}
258
259static const struct pci_device_id mpiix[] = {
260	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
261
262	{ },
263};
264
265static struct pci_driver mpiix_pci_driver = {
266	.name 		= DRV_NAME,
267	.id_table	= mpiix,
268	.probe 		= mpiix_init_one,
269	.remove		= ata_pci_remove_one,
270#ifdef CONFIG_PM
271	.suspend	= ata_pci_device_suspend,
272	.resume		= ata_pci_device_resume,
273#endif
274};
275
276static int __init mpiix_init(void)
277{
278	return pci_register_driver(&mpiix_pci_driver);
279}
280
281static void __exit mpiix_exit(void)
282{
283	pci_unregister_driver(&mpiix_pci_driver);
284}
285
286MODULE_AUTHOR("Alan Cox");
287MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
288MODULE_LICENSE("GPL");
289MODULE_DEVICE_TABLE(pci, mpiix);
290MODULE_VERSION(DRV_VERSION);
291
292module_init(mpiix_init);
293module_exit(mpiix_exit);
294