Lines Matching refs:timings
267 struct neofb_par *par, struct xtimings *timings)
271 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
274 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
289 par->CRTC[0] = (timings->HTotal >> 3) - 5;
290 par->CRTC[1] = (timings->HDisplay >> 3) - 1;
291 par->CRTC[2] = (timings->HDisplay >> 3) - 1;
292 par->CRTC[3] = (((timings->HTotal >> 3) - 1) & 0x1F) | 0x80;
293 par->CRTC[4] = (timings->HSyncStart >> 3);
294 par->CRTC[5] = ((((timings->HTotal >> 3) - 1) & 0x20) << 2)
295 | (((timings->HSyncEnd >> 3)) & 0x1F);
296 par->CRTC[6] = (timings->VTotal - 2) & 0xFF;
297 par->CRTC[7] = (((timings->VTotal - 2) & 0x100) >> 8)
298 | (((timings->VDisplay - 1) & 0x100) >> 7)
299 | ((timings->VSyncStart & 0x100) >> 6)
300 | (((timings->VDisplay - 1) & 0x100) >> 5)
301 | 0x10 | (((timings->VTotal - 2) & 0x200) >> 4)
302 | (((timings->VDisplay - 1) & 0x200) >> 3)
303 | ((timings->VSyncStart & 0x200) >> 2);
305 par->CRTC[9] = (((timings->VDisplay - 1) & 0x200) >> 4) | 0x40;
307 if (timings->dblscan)
316 par->CRTC[16] = timings->VSyncStart & 0xFF;
317 par->CRTC[17] = (timings->VSyncEnd & 0x0F) | 0x20;
318 par->CRTC[18] = (timings->VDisplay - 1) & 0xFF;
321 par->CRTC[21] = (timings->VDisplay - 1) & 0xFF;
322 par->CRTC[22] = (timings->VTotal - 1) & 0xFF;
576 struct xtimings timings;
584 timings.pixclock = 1000000000 / pixclock;
585 if (timings.pixclock < 1)
586 timings.pixclock = 1;
588 if (timings.pixclock > par->maxClock)
591 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
592 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
593 timings.HDisplay = var->xres;
594 timings.HSyncStart = timings.HDisplay + var->right_margin;
595 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
596 timings.HTotal = timings.HSyncEnd + var->left_margin;
597 timings.VDisplay = var->yres;
598 timings.VSyncStart = timings.VDisplay + var->lower_margin;
599 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
600 timings.VTotal = timings.VSyncEnd + var->upper_margin;
601 timings.sync = var->sync;
743 struct xtimings timings;
755 timings.dblscan = info->var.vmode & FB_VMODE_DOUBLE;
756 timings.interlaced = info->var.vmode & FB_VMODE_INTERLACED;
757 timings.HDisplay = info->var.xres;
758 timings.HSyncStart = timings.HDisplay + info->var.right_margin;
759 timings.HSyncEnd = timings.HSyncStart + info->var.hsync_len;
760 timings.HTotal = timings.HSyncEnd + info->var.left_margin;
761 timings.VDisplay = info->var.yres;
762 timings.VSyncStart = timings.VDisplay + info->var.lower_margin;
763 timings.VSyncEnd = timings.VSyncStart + info->var.vsync_len;
764 timings.VTotal = timings.VSyncEnd + info->var.upper_margin;
765 timings.sync = info->var.sync;
766 timings.pixclock = PICOS2KHZ(info->var.pixclock);
768 if (timings.pixclock < 1)
769 timings.pixclock = 1;
776 if (vgaHWInit(&info->var, info, par, &timings))
815 par->VerticalExt = (((timings.VTotal - 2) & 0x400) >> 10)
816 | (((timings.VDisplay - 1) & 0x400) >> 9)
817 | (((timings.VSyncStart) & 0x400) >> 8)
818 | (((timings.VSyncStart) & 0x400) >> 7);
979 neoCalcVCLK(info, par, timings.pixclock);