/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/sh/kernel/cpu/ |
H A D | adc.c | 15 unsigned char csr; local 21 csr = ctrl_inb(ADCSR); 22 csr = channel | ADCSR_ADST | ADCSR_CKS; 23 ctrl_outb(csr, ADCSR); 26 csr = ctrl_inb(ADCSR); 27 } while ((csr & ADCSR_ADF) == 0); 29 csr &= ~(ADCSR_ADF | ADCSR_ADST); 30 ctrl_outb(csr, ADCSR);
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ieee1394/ |
H A D | csr.c | 115 host->csr.state &= 0x300; 117 host->csr.bus_manager_id = 0x3f; 118 host->csr.bandwidth_available = 4915; 119 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */ 120 host->csr.channels_available_lo = ~0; 121 host->csr.broadcast_channel = 0x80000000 | 31; 129 host->csr.node_ids = host->node_id << 16; 133 host->csr.state &= ~0x100; 136 host->csr.topology_map[1] = 137 cpu_to_be32(be32_to_cpu(host->csr 159 calculate_expire(struct csr_control *csr) argument [all...] |
H A D | csr1212.c | 166 struct csr1212_csr *csr; local 168 csr = CSR1212_MALLOC(sizeof(*csr)); 169 if (!csr) 172 csr->cache_head = 175 if (!csr->cache_head) { 176 CSR1212_FREE(csr); 183 csr->root_kv = csr1212_new_directory(CSR1212_KV_ID_VENDOR); 184 if (!csr->root_kv) { 185 CSR1212_FREE(csr 200 csr1212_init_local_csr(struct csr1212_csr *csr, const u32 *bus_info_data, int max_rom) argument 547 csr1212_destroy_csr(struct csr1212_csr *csr) argument 573 csr1212_append_new_cache(struct csr1212_csr *csr, size_t romsize) argument 628 csr1212_remove_cache(struct csr1212_csr *csr, struct csr1212_csr_rom_cache *cache) argument 928 csr1212_generate_csr_image(struct csr1212_csr *csr) argument 1037 csr1212_read(struct csr1212_csr *csr, u32 offset, void *buffer, u32 len) argument 1056 csr1212_parse_bus_info_block(struct csr1212_csr *csr) argument 1249 csr1212_read_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv) argument 1409 csr1212_get_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv) argument 1419 csr1212_parse_csr(struct csr1212_csr *csr) argument [all...] |
H A D | hosts.c | 29 #include "csr.h" 37 int generation = host->csr.generation + 1; 44 CSR_SET_BUS_INFO_GENERATION(host->csr.rom, generation); 45 if (csr1212_generate_csr_image(host->csr.rom) != CSR1212_SUCCESS) { 48 CSR_SET_BUS_INFO_GENERATION(host->csr.rom, 49 host->csr.generation); 53 host->csr.generation = generation; 58 host->csr.rom->bus_info_data); 60 host->csr.gen_timestamp[host->csr [all...] |
H A D | config_roms.c | 20 #include "csr.h" 46 root = host->csr.rom->root_kv; 48 vend_id = csr1212_new_immediate(CSR1212_KV_ID_VENDOR, host->csr.guid_hi >> 8); 56 csr1212_destroy_csr(host->csr.rom); 65 csr1212_destroy_csr(host->csr.rom); 139 if (csr1212_attach_keyval_to_directory(host->csr.rom->root_kv, 151 csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, ip1394_ud);
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H A D | csr.h | 53 #define CSR_SET_BUS_INFO_GENERATION(csr, gen) \ 54 ((csr)->bus_info_data[2] = \ 55 cpu_to_be32((be32_to_cpu((csr)->bus_info_data[2]) & \
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H A D | Makefile | 6 highlevel.o csr.o nodemgr.o dma.o iso.o \
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/alpha/kernel/ |
H A D | core_tsunami.c | 180 volatile unsigned long *csr; 185 csr = &pchip->tlbia.csr; 187 csr = &pchip->tlbiv.csr; 193 *csr = value; 195 *csr; 227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ 231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { 232 int source = (TSUNAMI_cchip->misc.csr >> 2 179 volatile unsigned long *csr; local [all...] |
H A D | core_wildfire.c | 118 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; 119 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; 120 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); 122 pci->pci_window[1].wbase.csr = 0x40000000 | 1; 123 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; 124 pci->pci_window[1].tbase.csr = 0; 126 pci->pci_window[2].wbase.csr = 0x80000000 | 1; 127 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; 128 pci->pci_window[2].tbase.csr = 0x40000000; 130 pci->pci_window[3].wbase.csr [all...] |
H A D | core_titan.c | 210 volatile unsigned long *csr; 223 csr = &port->port_specific.g.gtlbia.csr; 225 csr = &port->port_specific.g.gtlbiv.csr; 232 *csr = value; 234 *csr; 243 pctl.pctl_q_whole = port->pctl.csr; 296 saved_config[index].wsba[0] = port->wsba[0].csr; 297 saved_config[index].wsm[0] = port->wsm[0].csr; 207 volatile unsigned long *csr; local [all...] |
H A D | sys_marvel.c | 98 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ 100 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; 204 volatile unsigned long *csr, 209 val = *csr; 213 *csr = val; 215 *csr; 226 val = io7->csrs->PO7_LSI_CTL[which].csr; 230 io7->csrs->PO7_LSI_CTL[which].csr = val; 232 io7->csrs->PO7_LSI_CTL[which].csr; 243 val = io7->csrs->PO7_MSI_CTL[which].csr; 202 io7_redirect_irq(struct io7 *io7, volatile unsigned long *csr, unsigned int where) argument [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m68k/sun3x/ |
H A D | time.h | 9 volatile unsigned char csr; member in struct:mostek_dt
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H A D | time.c | 49 h->csr |= C_WRITE; 57 h->csr &= ~C_WRITE; 59 h->csr |= C_READ; 67 h->csr &= ~C_READ;
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/sh/kernel/ |
H A D | pm.c | 33 u8 stbcr, csr; local 40 csr = sh_wdt_read_csr(); 41 csr &= ~WTCSR_TME; 42 csr |= WTCSR_CKS_4096; 43 sh_wdt_write_csr(csr); 44 csr = sh_wdt_read_csr();
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/mips/dec/ |
H A D | kn02-irq.c | 38 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + local 42 *csr = cached_kn02_csr; 47 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + local 51 *csr = cached_kn02_csr; 71 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + local 77 *csr = cached_kn02_csr;
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H A D | kn01-berr.c | 56 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); local 61 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */ 157 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); local 161 if (!(*csr & KN01_CSR_MEMERR)) 177 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); local 183 cached_kn01_csr = *csr; 189 *csr = cached_kn01_csr;
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/scsi/ |
H A D | sun3_scsi_vme.c | 193 oldcsr = dregs->csr; 194 dregs->csr = 0; 196 if(dregs->csr == 0x1400) 199 dregs->csr = oldcsr; 254 dregs->csr = 0; 256 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; 341 unsigned short csr = dregs->csr; local 344 dregs->csr &= ~CSR_DMA_ENABLE; 348 printk("scsi_intr csr 449 unsigned short csr; local [all...] |
H A D | sun3_scsi.c | 295 dregs->csr = 0; 297 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; 375 unsigned short csr = dregs->csr; local 378 if(csr & ~CSR_GOOD) { 379 if(csr & CSR_DMA_BUSERR) { 383 if(csr & CSR_DMA_CONFLICT) { 389 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { 431 dregs->csr &= ~CSR_FIFO; 432 dregs->csr | [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/watchdog/ |
H A D | shwdt.c | 88 __u8 csr; local 93 csr = sh_wdt_read_csr(); 94 csr |= WTCSR_WT | clock_division_ratio; 95 sh_wdt_write_csr(csr); 107 csr = sh_wdt_read_csr(); 108 csr |= WTCSR_TME; 109 csr &= ~WTCSR_RSTS; 110 sh_wdt_write_csr(csr); 122 csr = sh_wdt_read_rstcsr(); 123 csr 134 __u8 csr; local 174 __u8 csr; local [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/sparc64/kernel/ |
H A D | ebus.c | 87 u32 csr = 0; local 90 csr = readl(p->regs + EBDMA_CSR); 91 writel(csr, p->regs + EBDMA_CSR); 94 if (csr & EBDMA_CSR_ERR_PEND) { 98 } else if (csr & EBDMA_CSR_INT_PEND) { 100 (csr & EBDMA_CSR_TC) ? 112 u32 csr; local 126 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; 129 csr |= EBDMA_CSR_TCI_DIS; 131 writel(csr, 140 u32 csr; local 172 u32 csr; local 192 u32 csr; local 221 u32 csr; local 257 u32 orig_csr, csr; local [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/usb/gadget/ |
H A D | at91_udc.c | 104 u32 csr; local 110 csr = __raw_readl(ep->creg); 123 seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", 124 csr, 125 (csr & 0x07ff0000) >> 16, 126 (csr & (1 << 15)) ? "enabled" : "disabled", 127 (csr & (1 << 11)) ? "DATA1" : "DATA0", 128 types[(csr & 0x700) >> 8], 131 (!(csr & 0x700)) 132 ? ((csr 323 u32 csr; local 390 u32 csr = __raw_readl(creg); local 749 u32 csr; local 1007 u32 csr = __raw_readl(creg); local 1045 handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) argument 1273 u32 csr = __raw_readl(creg); local [all...] |
H A D | lh7a40x_udc.c | 356 u32 csr; local 379 csr = usb_read(ep_reg->csr1); 380 usb_write(csr, ep_reg->csr1); 503 u32 csr; local 507 csr = usb_read(ep->csr1); 508 DEBUG("CSR: %x %d\n", csr, csr & USB_IN_CSR1_FIFO_NOT_EMPTY); 510 if (!(csr & USB_IN_CSR1_FIFO_NOT_EMPTY)) { 556 u32 csr; local 562 csr 768 u32 csr; local 816 u32 csr; local 1176 u32 csr; local 1269 u32 csr = usb_read(ep->csr1); local 1321 u32 csr; local 1431 u32 csr; local 1510 lh7a40x_ep0_out(struct lh7a40x_udc *dev, u32 csr) argument 1552 lh7a40x_ep0_in(struct lh7a40x_udc *dev, u32 csr) argument 1690 lh7a40x_ep0_setup(struct lh7a40x_udc *dev, u32 csr) argument 1799 lh7a40x_ep0_in_zlp(struct lh7a40x_udc *dev, u32 csr) argument 1814 u32 csr; local 1923 u32 csr; local [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/pcmcia/ |
H A D | pxa2xx_sharpsl.c | 90 unsigned short cpr, csr; local 98 csr = read_scoop_reg(scoop, SCOOP_CSR); 99 if (csr & 0x0004) { 107 csr |= SCOOP_DEV[skt->nr].keep_vs; 112 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); 123 state->detect = (csr & 0x0004) ? 0 : 1; 124 state->ready = (csr & 0x0002) ? 1 : 0; 125 state->bvd1 = (csr & 0x0010) ? 1 : 0; 126 state->bvd2 = (csr & 0x0020) ? 1 : 0; 127 state->wrprot = (csr [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm/sibyte/ |
H A D | sb1250_defs.h | 251 #define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) 252 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-mips/sibyte/ |
H A D | sb1250_defs.h | 251 #define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) 252 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
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