Lines Matching refs:csr
115 host->csr.state &= 0x300;
117 host->csr.bus_manager_id = 0x3f;
118 host->csr.bandwidth_available = 4915;
119 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
120 host->csr.channels_available_lo = ~0;
121 host->csr.broadcast_channel = 0x80000000 | 31;
129 host->csr.node_ids = host->node_id << 16;
133 host->csr.state &= ~0x100;
136 host->csr.topology_map[1] =
137 cpu_to_be32(be32_to_cpu(host->csr.topology_map[1]) + 1);
138 host->csr.topology_map[2] = cpu_to_be32(host->node_count << 16
140 host->csr.topology_map[0] =
142 | csr_crc16(host->csr.topology_map + 1,
145 host->csr.speed_map[1] =
146 cpu_to_be32(be32_to_cpu(host->csr.speed_map[1]) + 1);
147 host->csr.speed_map[0] = cpu_to_be32(0x3f1 << 16
148 | csr_crc16(host->csr.speed_map+1,
159 static inline void calculate_expire(struct csr_control *csr)
161 unsigned int usecs = (csr->split_timeout_hi & 7) * 1000000 +
162 (csr->split_timeout_lo >> 19) * 125;
164 csr->expire = usecs_to_jiffies(usecs > 100000 ? usecs : 100000);
165 HPSB_VERBOSE("CSR: setting expire to %lu, HZ=%u", csr->expire, HZ);
192 spin_lock_init(&host->csr.lock);
194 host->csr.state = 0;
195 host->csr.node_ids = 0;
196 host->csr.split_timeout_hi = 0;
197 host->csr.split_timeout_lo = 800 << 19;
198 calculate_expire(&host->csr);
199 host->csr.cycle_time = 0;
200 host->csr.bus_time = 0;
201 host->csr.bus_manager_id = 0x3f;
202 host->csr.bandwidth_available = 4915;
203 host->csr.channels_available_hi = 0xfffffffe; /* pre-alloc ch 31 per 1394a-2000 */
204 host->csr.channels_available_lo = ~0;
205 host->csr.broadcast_channel = 0x80000000 | 31;
213 if (host->csr.max_rec >= 9)
214 host->csr.max_rom = 2;
215 else if (host->csr.max_rec >= 5)
216 host->csr.max_rom = 1;
218 host->csr.max_rom = 0;
220 host->csr.generation = 2;
228 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
229 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
230 (host->csr.max_rom << CSR_MAX_ROM_SHIFT) |
231 (host->csr.generation << CSR_GENERATION_SHIFT) |
232 host->csr.lnk_spd);
234 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
235 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
240 csr1212_init_local_csr(host->csr.rom, bus_info, host->csr.max_rom);
242 root = host->csr.rom->root_kv;
261 (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
262 (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
265 host->csr.lnk_spd);
267 bus_info[3] = cpu_to_be32(host->csr.guid_hi);
268 bus_info[4] = cpu_to_be32(host->csr.guid_lo);
270 csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, node_cap);
272 csr1212_init_local_csr(host->csr.rom, bus_info, 0);
285 spin_lock_irqsave(&host->csr.lock, flags);
286 if (rom_version != host->csr.generation)
288 else if (buffersize > host->csr.rom->cache_head->size)
293 memcpy(host->csr.rom->cache_head->data, new_rom, buffersize);
294 host->csr.rom->cache_head->len = buffersize;
297 host->driver->set_hw_config_rom(host, host->csr.rom->bus_info_data);
300 host->csr.generation++;
301 if (host->csr.generation > 0xf || host->csr.generation < 2)
302 host->csr.generation = 2;
305 spin_unlock_irqrestore(&host->csr.lock, flags);
318 spin_lock_irqsave(&host->csr.lock, flags);
321 src = ((char *)host->csr.topology_map) + csraddr
324 src = ((char *)host->csr.speed_map) + csraddr - CSR_SPEED_MAP;
328 spin_unlock_irqrestore(&host->csr.lock, flags);
349 *(buf++) = cpu_to_be32(host->csr.state);
352 *(buf++) = cpu_to_be32(host->csr.state);
355 *(buf++) = cpu_to_be32(host->csr.node_ids);
364 *(buf++) = cpu_to_be32(host->csr.split_timeout_hi);
367 *(buf++) = cpu_to_be32(host->csr.split_timeout_lo);
374 oldcycle = host->csr.cycle_time;
375 host->csr.cycle_time =
378 if (oldcycle > host->csr.cycle_time) {
380 host->csr.bus_time += 1 << 7;
382 *(buf++) = cpu_to_be32(host->csr.cycle_time);
385 oldcycle = host->csr.cycle_time;
386 host->csr.cycle_time =
389 if (oldcycle > host->csr.cycle_time) {
391 host->csr.bus_time += (1 << 7);
393 *(buf++) = cpu_to_be32(host->csr.bus_time
394 | (host->csr.cycle_time >> 25));
408 ret = host->csr.bus_manager_id;
416 ret = host->csr.bandwidth_available;
424 ret = host->csr.channels_available_hi;
432 ret = host->csr.channels_available_lo;
438 *(buf++) = cpu_to_be32(host->csr.broadcast_channel);
468 host->csr.node_ids &= NODE_MASK << 16;
469 host->csr.node_ids |= be32_to_cpu(*(data++)) & (BUS_MASK << 16);
470 host->node_id = host->csr.node_ids >> 16;
481 host->csr.split_timeout_hi =
483 calculate_expire(&host->csr);
486 host->csr.split_timeout_lo =
488 calculate_expire(&host->csr);
496 host->csr.cycle_time = be32_to_cpu(*data);
501 host->csr.bus_time = be32_to_cpu(*(data++)) & 0xffffff80;
520 host->csr.broadcast_channel = (host->csr.broadcast_channel & ~0x40000000)
575 spin_lock_irqsave(&host->csr.lock, flags);
579 regptr = &host->csr.bus_manager_id;
591 regptr = &host->csr.bandwidth_available;
629 regptr = &host->csr.channels_available_hi;
646 regptr = &host->csr.channels_available_lo;
658 spin_unlock_irqrestore(&host->csr.lock, flags);
731 spin_lock_irqsave(&host->csr.lock, flags);
733 old = ((octlet_t)host->csr.channels_available_hi << 32) | host->csr.channels_available_lo;
736 host->csr.channels_available_hi ^= (affected_channels >> 32);
737 host->csr.channels_available_lo ^= (affected_channels & 0xffffffff);
743 spin_unlock_irqrestore(&host->csr.lock, flags);
747 if (host->csr.channels_available_hi & 0x1)
748 host->csr.channels_available_hi &= ~0x1;
800 if (csr1212_read(host->csr.rom, offset, buffer, length) == CSR1212_SUCCESS)