1/* 2 * linux/arch/alpha/kernel/core_wildfire.c 3 * 4 * Wildfire support. 5 * 6 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 7 */ 8 9#define __EXTERN_INLINE inline 10#include <asm/io.h> 11#include <asm/core_wildfire.h> 12#undef __EXTERN_INLINE 13 14#include <linux/types.h> 15#include <linux/pci.h> 16#include <linux/sched.h> 17#include <linux/init.h> 18 19#include <asm/ptrace.h> 20#include <asm/smp.h> 21 22#include "proto.h" 23#include "pci_impl.h" 24 25#define DEBUG_CONFIG 0 26#define DEBUG_DUMP_REGS 0 27#define DEBUG_DUMP_CONFIG 1 28 29#if DEBUG_CONFIG 30# define DBG_CFG(args) printk args 31#else 32# define DBG_CFG(args) 33#endif 34 35#if DEBUG_DUMP_REGS 36static void wildfire_dump_pci_regs(int qbbno, int hoseno); 37static void wildfire_dump_pca_regs(int qbbno, int pcano); 38static void wildfire_dump_qsa_regs(int qbbno); 39static void wildfire_dump_qsd_regs(int qbbno); 40static void wildfire_dump_iop_regs(int qbbno); 41static void wildfire_dump_gp_regs(int qbbno); 42#endif 43#if DEBUG_DUMP_CONFIG 44static void wildfire_dump_hardware_config(void); 45#endif 46 47unsigned char wildfire_hard_qbb_map[WILDFIRE_MAX_QBB]; 48unsigned char wildfire_soft_qbb_map[WILDFIRE_MAX_QBB]; 49#define QBB_MAP_EMPTY 0xff 50 51unsigned long wildfire_hard_qbb_mask; 52unsigned long wildfire_soft_qbb_mask; 53unsigned long wildfire_gp_mask; 54unsigned long wildfire_hs_mask; 55unsigned long wildfire_iop_mask; 56unsigned long wildfire_ior_mask; 57unsigned long wildfire_pca_mask; 58unsigned long wildfire_cpu_mask; 59unsigned long wildfire_mem_mask; 60 61void __init 62wildfire_init_hose(int qbbno, int hoseno) 63{ 64 struct pci_controller *hose; 65 wildfire_pci *pci; 66 67 hose = alloc_pci_controller(); 68 hose->io_space = alloc_resource(); 69 hose->mem_space = alloc_resource(); 70 71 /* This is for userland consumption. */ 72 hose->sparse_mem_base = 0; 73 hose->sparse_io_base = 0; 74 hose->dense_mem_base = WILDFIRE_MEM(qbbno, hoseno); 75 hose->dense_io_base = WILDFIRE_IO(qbbno, hoseno); 76 77 hose->config_space_base = WILDFIRE_CONF(qbbno, hoseno); 78 hose->index = (qbbno << 3) + hoseno; 79 80 hose->io_space->start = WILDFIRE_IO(qbbno, hoseno) - WILDFIRE_IO_BIAS; 81 hose->io_space->end = hose->io_space->start + WILDFIRE_IO_SPACE - 1; 82 hose->io_space->name = pci_io_names[hoseno]; 83 hose->io_space->flags = IORESOURCE_IO; 84 85 hose->mem_space->start = WILDFIRE_MEM(qbbno, hoseno)-WILDFIRE_MEM_BIAS; 86 hose->mem_space->end = hose->mem_space->start + 0xffffffff; 87 hose->mem_space->name = pci_mem_names[hoseno]; 88 hose->mem_space->flags = IORESOURCE_MEM; 89 90 if (request_resource(&ioport_resource, hose->io_space) < 0) 91 printk(KERN_ERR "Failed to request IO on qbb %d hose %d\n", 92 qbbno, hoseno); 93 if (request_resource(&iomem_resource, hose->mem_space) < 0) 94 printk(KERN_ERR "Failed to request MEM on qbb %d hose %d\n", 95 qbbno, hoseno); 96 97#if DEBUG_DUMP_REGS 98 wildfire_dump_pci_regs(qbbno, hoseno); 99#endif 100 101 /* 102 * Set up the PCI to main memory translation windows. 103 * 104 * Note: Window 3 is scatter-gather only 105 * 106 * Window 0 is scatter-gather 8MB at 8MB (for isa) 107 * Window 1 is direct access 1GB at 1GB 108 * Window 2 is direct access 1GB at 2GB 109 * Window 3 is scatter-gather 128MB at 3GB 110 * ??? We ought to scale window 3 memory. 111 * 112 */ 113 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0); 114 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x08000000, 0); 115 116 pci = WILDFIRE_pci(qbbno, hoseno); 117 118 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; 119 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; 120 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); 121 122 pci->pci_window[1].wbase.csr = 0x40000000 | 1; 123 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; 124 pci->pci_window[1].tbase.csr = 0; 125 126 pci->pci_window[2].wbase.csr = 0x80000000 | 1; 127 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; 128 pci->pci_window[2].tbase.csr = 0x40000000; 129 130 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; 131 pci->pci_window[3].wmask.csr = (hose->sg_pci->size - 1) & 0xfff00000; 132 pci->pci_window[3].tbase.csr = virt_to_phys(hose->sg_pci->ptes); 133 134 wildfire_pci_tbi(hose, 0, 0); /* Flush TLB at the end. */ 135} 136 137void __init 138wildfire_init_pca(int qbbno, int pcano) 139{ 140 141 /* Test for PCA existence first. */ 142 if (!WILDFIRE_PCA_EXISTS(qbbno, pcano)) 143 return; 144 145#if DEBUG_DUMP_REGS 146 wildfire_dump_pca_regs(qbbno, pcano); 147#endif 148 149 /* Do both hoses of the PCA. */ 150 wildfire_init_hose(qbbno, (pcano << 1) + 0); 151 wildfire_init_hose(qbbno, (pcano << 1) + 1); 152} 153 154void __init 155wildfire_init_qbb(int qbbno) 156{ 157 int pcano; 158 159 /* Test for QBB existence first. */ 160 if (!WILDFIRE_QBB_EXISTS(qbbno)) 161 return; 162 163#if DEBUG_DUMP_REGS 164 wildfire_dump_qsa_regs(qbbno); 165 wildfire_dump_qsd_regs(qbbno); 166 wildfire_dump_iop_regs(qbbno); 167 wildfire_dump_gp_regs(qbbno); 168#endif 169 170 /* Init all PCAs here. */ 171 for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) { 172 wildfire_init_pca(qbbno, pcano); 173 } 174} 175 176void __init 177wildfire_hardware_probe(void) 178{ 179 unsigned long temp; 180 unsigned int hard_qbb, soft_qbb; 181 wildfire_fast_qsd *fast = WILDFIRE_fast_qsd(); 182 wildfire_qsd *qsd; 183 wildfire_qsa *qsa; 184 wildfire_iop *iop; 185 wildfire_gp *gp; 186 wildfire_ne *ne; 187 wildfire_fe *fe; 188 int i; 189 190 temp = fast->qsd_whami.csr; 191 192 hard_qbb = (temp >> 8) & 7; 193 soft_qbb = (temp >> 4) & 7; 194 195 /* Init the HW configuration variables. */ 196 wildfire_hard_qbb_mask = (1 << hard_qbb); 197 wildfire_soft_qbb_mask = (1 << soft_qbb); 198 199 wildfire_gp_mask = 0; 200 wildfire_hs_mask = 0; 201 wildfire_iop_mask = 0; 202 wildfire_ior_mask = 0; 203 wildfire_pca_mask = 0; 204 205 wildfire_cpu_mask = 0; 206 wildfire_mem_mask = 0; 207 208 memset(wildfire_hard_qbb_map, QBB_MAP_EMPTY, WILDFIRE_MAX_QBB); 209 memset(wildfire_soft_qbb_map, QBB_MAP_EMPTY, WILDFIRE_MAX_QBB); 210 211 /* First, determine which QBBs are present. */ 212 qsa = WILDFIRE_qsa(soft_qbb); 213 214 temp = qsa->qsa_qbb_id.csr; 215 216 if (temp & 0x40) /* Is there an HS? */ 217 wildfire_hs_mask = 1; 218 219 if (temp & 0x20) { /* Is there a GP? */ 220 gp = WILDFIRE_gp(soft_qbb); 221 temp = 0; 222 for (i = 0; i < 4; i++) { 223 temp |= gp->gpa_qbb_map[i].csr << (i * 8); 224 } 225 226 for (hard_qbb = 0; hard_qbb < WILDFIRE_MAX_QBB; hard_qbb++) { 227 if (temp & 8) { /* Is there a QBB? */ 228 soft_qbb = temp & 7; 229 wildfire_hard_qbb_mask |= (1 << hard_qbb); 230 wildfire_soft_qbb_mask |= (1 << soft_qbb); 231 } 232 temp >>= 4; 233 } 234 wildfire_gp_mask = wildfire_soft_qbb_mask; 235 } 236 237 /* Next determine each QBBs resources. */ 238 for (soft_qbb = 0; soft_qbb < WILDFIRE_MAX_QBB; soft_qbb++) { 239 if (WILDFIRE_QBB_EXISTS(soft_qbb)) { 240 qsd = WILDFIRE_qsd(soft_qbb); 241 temp = qsd->qsd_whami.csr; 242 hard_qbb = (temp >> 8) & 7; 243 wildfire_hard_qbb_map[hard_qbb] = soft_qbb; 244 wildfire_soft_qbb_map[soft_qbb] = hard_qbb; 245 246 qsa = WILDFIRE_qsa(soft_qbb); 247 temp = qsa->qsa_qbb_pop[0].csr; 248 wildfire_cpu_mask |= ((temp >> 0) & 0xf) << (soft_qbb << 2); 249 wildfire_mem_mask |= ((temp >> 4) & 0xf) << (soft_qbb << 2); 250 251 temp = qsa->qsa_qbb_pop[1].csr; 252 wildfire_iop_mask |= (1 << soft_qbb); 253 wildfire_ior_mask |= ((temp >> 4) & 0xf) << (soft_qbb << 2); 254 255 temp = qsa->qsa_qbb_id.csr; 256 if (temp & 0x20) 257 wildfire_gp_mask |= (1 << soft_qbb); 258 259 /* Probe for PCA existence here. */ 260 for (i = 0; i < WILDFIRE_PCA_PER_QBB; i++) { 261 iop = WILDFIRE_iop(soft_qbb); 262 ne = WILDFIRE_ne(soft_qbb, i); 263 fe = WILDFIRE_fe(soft_qbb, i); 264 265 if ((iop->iop_hose[i].init.csr & 1) == 1 && 266 ((ne->ne_what_am_i.csr & 0xf00000300UL) == 0x100000300UL) && 267 ((fe->fe_what_am_i.csr & 0xf00000300UL) == 0x100000200UL)) 268 { 269 wildfire_pca_mask |= 1 << ((soft_qbb << 2) + i); 270 } 271 } 272 273 } 274 } 275#if DEBUG_DUMP_CONFIG 276 wildfire_dump_hardware_config(); 277#endif 278} 279 280void __init 281wildfire_init_arch(void) 282{ 283 int qbbno; 284 285 /* With multiple PCI buses, we play with I/O as physical addrs. */ 286 ioport_resource.end = ~0UL; 287 288 289 /* Probe the hardware for info about configuration. */ 290 wildfire_hardware_probe(); 291 292 /* Now init all the found QBBs. */ 293 for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) { 294 wildfire_init_qbb(qbbno); 295 } 296 297 /* Normal direct PCI DMA mapping. */ 298 __direct_map_base = 0x40000000UL; 299 __direct_map_size = 0x80000000UL; 300} 301 302void 303wildfire_machine_check(unsigned long vector, unsigned long la_ptr) 304{ 305 mb(); 306 mb(); /* magic */ 307 draina(); 308 wrmces(0x7); 309 mb(); 310 311 process_mcheck_info(vector, la_ptr, "WILDFIRE", 312 mcheck_expected(smp_processor_id())); 313} 314 315void 316wildfire_kill_arch(int mode) 317{ 318} 319 320void 321wildfire_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) 322{ 323 int qbbno = hose->index >> 3; 324 int hoseno = hose->index & 7; 325 wildfire_pci *pci = WILDFIRE_pci(qbbno, hoseno); 326 327 mb(); 328 pci->pci_flush_tlb.csr; /* reading does the trick */ 329} 330 331static int 332mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, 333 unsigned long *pci_addr, unsigned char *type1) 334{ 335 struct pci_controller *hose = pbus->sysdata; 336 unsigned long addr; 337 u8 bus = pbus->number; 338 339 DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, " 340 "pci_addr=0x%p, type1=0x%p)\n", 341 bus, device_fn, where, pci_addr, type1)); 342 343 if (!pbus->parent) /* No parent means peer PCI bus. */ 344 bus = 0; 345 *type1 = (bus != 0); 346 347 addr = (bus << 16) | (device_fn << 8) | where; 348 addr |= hose->config_space_base; 349 350 *pci_addr = addr; 351 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); 352 return 0; 353} 354 355static int 356wildfire_read_config(struct pci_bus *bus, unsigned int devfn, int where, 357 int size, u32 *value) 358{ 359 unsigned long addr; 360 unsigned char type1; 361 362 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 363 return PCIBIOS_DEVICE_NOT_FOUND; 364 365 switch (size) { 366 case 1: 367 *value = __kernel_ldbu(*(vucp)addr); 368 break; 369 case 2: 370 *value = __kernel_ldwu(*(vusp)addr); 371 break; 372 case 4: 373 *value = *(vuip)addr; 374 break; 375 } 376 377 return PCIBIOS_SUCCESSFUL; 378} 379 380static int 381wildfire_write_config(struct pci_bus *bus, unsigned int devfn, int where, 382 int size, u32 value) 383{ 384 unsigned long addr; 385 unsigned char type1; 386 387 if (mk_conf_addr(bus, devfn, where, &addr, &type1)) 388 return PCIBIOS_DEVICE_NOT_FOUND; 389 390 switch (size) { 391 case 1: 392 __kernel_stb(value, *(vucp)addr); 393 mb(); 394 __kernel_ldbu(*(vucp)addr); 395 break; 396 case 2: 397 __kernel_stw(value, *(vusp)addr); 398 mb(); 399 __kernel_ldwu(*(vusp)addr); 400 break; 401 case 4: 402 *(vuip)addr = value; 403 mb(); 404 *(vuip)addr; 405 break; 406 } 407 408 return PCIBIOS_SUCCESSFUL; 409} 410 411struct pci_ops wildfire_pci_ops = 412{ 413 .read = wildfire_read_config, 414 .write = wildfire_write_config, 415}; 416 417 418/* 419 * NUMA Support 420 */ 421int wildfire_pa_to_nid(unsigned long pa) 422{ 423 return pa >> 36; 424} 425 426int wildfire_cpuid_to_nid(int cpuid) 427{ 428 /* assume 4 CPUs per node */ 429 return cpuid >> 2; 430} 431 432unsigned long wildfire_node_mem_start(int nid) 433{ 434 /* 64GB per node */ 435 return (unsigned long)nid * (64UL * 1024 * 1024 * 1024); 436} 437 438unsigned long wildfire_node_mem_size(int nid) 439{ 440 /* 64GB per node */ 441 return 64UL * 1024 * 1024 * 1024; 442} 443 444#if DEBUG_DUMP_REGS 445 446static void __init 447wildfire_dump_pci_regs(int qbbno, int hoseno) 448{ 449 wildfire_pci *pci = WILDFIRE_pci(qbbno, hoseno); 450 int i; 451 452 printk(KERN_ERR "PCI registers for QBB %d hose %d (%p)\n", 453 qbbno, hoseno, pci); 454 455 printk(KERN_ERR " PCI_IO_ADDR_EXT: 0x%16lx\n", 456 pci->pci_io_addr_ext.csr); 457 printk(KERN_ERR " PCI_CTRL: 0x%16lx\n", pci->pci_ctrl.csr); 458 printk(KERN_ERR " PCI_ERR_SUM: 0x%16lx\n", pci->pci_err_sum.csr); 459 printk(KERN_ERR " PCI_ERR_ADDR: 0x%16lx\n", pci->pci_err_addr.csr); 460 printk(KERN_ERR " PCI_STALL_CNT: 0x%16lx\n", pci->pci_stall_cnt.csr); 461 printk(KERN_ERR " PCI_PEND_INT: 0x%16lx\n", pci->pci_pend_int.csr); 462 printk(KERN_ERR " PCI_SENT_INT: 0x%16lx\n", pci->pci_sent_int.csr); 463 464 printk(KERN_ERR " DMA window registers for QBB %d hose %d (%p)\n", 465 qbbno, hoseno, pci); 466 for (i = 0; i < 4; i++) { 467 printk(KERN_ERR " window %d: 0x%16lx 0x%16lx 0x%16lx\n", i, 468 pci->pci_window[i].wbase.csr, 469 pci->pci_window[i].wmask.csr, 470 pci->pci_window[i].tbase.csr); 471 } 472 printk(KERN_ERR "\n"); 473} 474 475static void __init 476wildfire_dump_pca_regs(int qbbno, int pcano) 477{ 478 wildfire_pca *pca = WILDFIRE_pca(qbbno, pcano); 479 int i; 480 481 printk(KERN_ERR "PCA registers for QBB %d PCA %d (%p)\n", 482 qbbno, pcano, pca); 483 484 printk(KERN_ERR " PCA_WHAT_AM_I: 0x%16lx\n", pca->pca_what_am_i.csr); 485 printk(KERN_ERR " PCA_ERR_SUM: 0x%16lx\n", pca->pca_err_sum.csr); 486 printk(KERN_ERR " PCA_PEND_INT: 0x%16lx\n", pca->pca_pend_int.csr); 487 printk(KERN_ERR " PCA_SENT_INT: 0x%16lx\n", pca->pca_sent_int.csr); 488 printk(KERN_ERR " PCA_STDIO_EL: 0x%16lx\n", 489 pca->pca_stdio_edge_level.csr); 490 491 printk(KERN_ERR " PCA target registers for QBB %d PCA %d (%p)\n", 492 qbbno, pcano, pca); 493 for (i = 0; i < 4; i++) { 494 printk(KERN_ERR " target %d: 0x%16lx 0x%16lx\n", i, 495 pca->pca_int[i].target.csr, 496 pca->pca_int[i].enable.csr); 497 } 498 499 printk(KERN_ERR "\n"); 500} 501 502static void __init 503wildfire_dump_qsa_regs(int qbbno) 504{ 505 wildfire_qsa *qsa = WILDFIRE_qsa(qbbno); 506 int i; 507 508 printk(KERN_ERR "QSA registers for QBB %d (%p)\n", qbbno, qsa); 509 510 printk(KERN_ERR " QSA_QBB_ID: 0x%16lx\n", qsa->qsa_qbb_id.csr); 511 printk(KERN_ERR " QSA_PORT_ENA: 0x%16lx\n", qsa->qsa_port_ena.csr); 512 printk(KERN_ERR " QSA_REF_INT: 0x%16lx\n", qsa->qsa_ref_int.csr); 513 514 for (i = 0; i < 5; i++) 515 printk(KERN_ERR " QSA_CONFIG_%d: 0x%16lx\n", 516 i, qsa->qsa_config[i].csr); 517 518 for (i = 0; i < 2; i++) 519 printk(KERN_ERR " QSA_QBB_POP_%d: 0x%16lx\n", 520 i, qsa->qsa_qbb_pop[0].csr); 521 522 printk(KERN_ERR "\n"); 523} 524 525static void __init 526wildfire_dump_qsd_regs(int qbbno) 527{ 528 wildfire_qsd *qsd = WILDFIRE_qsd(qbbno); 529 530 printk(KERN_ERR "QSD registers for QBB %d (%p)\n", qbbno, qsd); 531 532 printk(KERN_ERR " QSD_WHAMI: 0x%16lx\n", qsd->qsd_whami.csr); 533 printk(KERN_ERR " QSD_REV: 0x%16lx\n", qsd->qsd_rev.csr); 534 printk(KERN_ERR " QSD_PORT_PRESENT: 0x%16lx\n", 535 qsd->qsd_port_present.csr); 536 printk(KERN_ERR " QSD_PORT_ACTUVE: 0x%16lx\n", 537 qsd->qsd_port_active.csr); 538 printk(KERN_ERR " QSD_FAULT_ENA: 0x%16lx\n", 539 qsd->qsd_fault_ena.csr); 540 printk(KERN_ERR " QSD_CPU_INT_ENA: 0x%16lx\n", 541 qsd->qsd_cpu_int_ena.csr); 542 printk(KERN_ERR " QSD_MEM_CONFIG: 0x%16lx\n", 543 qsd->qsd_mem_config.csr); 544 printk(KERN_ERR " QSD_ERR_SUM: 0x%16lx\n", 545 qsd->qsd_err_sum.csr); 546 547 printk(KERN_ERR "\n"); 548} 549 550static void __init 551wildfire_dump_iop_regs(int qbbno) 552{ 553 wildfire_iop *iop = WILDFIRE_iop(qbbno); 554 int i; 555 556 printk(KERN_ERR "IOP registers for QBB %d (%p)\n", qbbno, iop); 557 558 printk(KERN_ERR " IOA_CONFIG: 0x%16lx\n", iop->ioa_config.csr); 559 printk(KERN_ERR " IOD_CONFIG: 0x%16lx\n", iop->iod_config.csr); 560 printk(KERN_ERR " IOP_SWITCH_CREDITS: 0x%16lx\n", 561 iop->iop_switch_credits.csr); 562 printk(KERN_ERR " IOP_HOSE_CREDITS: 0x%16lx\n", 563 iop->iop_hose_credits.csr); 564 565 for (i = 0; i < 4; i++) 566 printk(KERN_ERR " IOP_HOSE_%d_INIT: 0x%16lx\n", 567 i, iop->iop_hose[i].init.csr); 568 for (i = 0; i < 4; i++) 569 printk(KERN_ERR " IOP_DEV_INT_TARGET_%d: 0x%16lx\n", 570 i, iop->iop_dev_int[i].target.csr); 571 572 printk(KERN_ERR "\n"); 573} 574 575static void __init 576wildfire_dump_gp_regs(int qbbno) 577{ 578 wildfire_gp *gp = WILDFIRE_gp(qbbno); 579 int i; 580 581 printk(KERN_ERR "GP registers for QBB %d (%p)\n", qbbno, gp); 582 for (i = 0; i < 4; i++) 583 printk(KERN_ERR " GPA_QBB_MAP_%d: 0x%16lx\n", 584 i, gp->gpa_qbb_map[i].csr); 585 586 printk(KERN_ERR " GPA_MEM_POP_MAP: 0x%16lx\n", 587 gp->gpa_mem_pop_map.csr); 588 printk(KERN_ERR " GPA_SCRATCH: 0x%16lx\n", gp->gpa_scratch.csr); 589 printk(KERN_ERR " GPA_DIAG: 0x%16lx\n", gp->gpa_diag.csr); 590 printk(KERN_ERR " GPA_CONFIG_0: 0x%16lx\n", gp->gpa_config_0.csr); 591 printk(KERN_ERR " GPA_INIT_ID: 0x%16lx\n", gp->gpa_init_id.csr); 592 printk(KERN_ERR " GPA_CONFIG_2: 0x%16lx\n", gp->gpa_config_2.csr); 593 594 printk(KERN_ERR "\n"); 595} 596#endif /* DUMP_REGS */ 597 598#if DEBUG_DUMP_CONFIG 599static void __init 600wildfire_dump_hardware_config(void) 601{ 602 int i; 603 604 printk(KERN_ERR "Probed Hardware Configuration\n"); 605 606 printk(KERN_ERR " hard_qbb_mask: 0x%16lx\n", wildfire_hard_qbb_mask); 607 printk(KERN_ERR " soft_qbb_mask: 0x%16lx\n", wildfire_soft_qbb_mask); 608 609 printk(KERN_ERR " gp_mask: 0x%16lx\n", wildfire_gp_mask); 610 printk(KERN_ERR " hs_mask: 0x%16lx\n", wildfire_hs_mask); 611 printk(KERN_ERR " iop_mask: 0x%16lx\n", wildfire_iop_mask); 612 printk(KERN_ERR " ior_mask: 0x%16lx\n", wildfire_ior_mask); 613 printk(KERN_ERR " pca_mask: 0x%16lx\n", wildfire_pca_mask); 614 615 printk(KERN_ERR " cpu_mask: 0x%16lx\n", wildfire_cpu_mask); 616 printk(KERN_ERR " mem_mask: 0x%16lx\n", wildfire_mem_mask); 617 618 printk(" hard_qbb_map: "); 619 for (i = 0; i < WILDFIRE_MAX_QBB; i++) 620 if (wildfire_hard_qbb_map[i] == QBB_MAP_EMPTY) 621 printk("--- "); 622 else 623 printk("%3d ", wildfire_hard_qbb_map[i]); 624 printk("\n"); 625 626 printk(" soft_qbb_map: "); 627 for (i = 0; i < WILDFIRE_MAX_QBB; i++) 628 if (wildfire_soft_qbb_map[i] == QBB_MAP_EMPTY) 629 printk("--- "); 630 else 631 printk("%3d ", wildfire_soft_qbb_map[i]); 632 printk("\n"); 633} 634#endif /* DUMP_CONFIG */ 635