Lines Matching refs:csr
210 volatile unsigned long *csr;
223 csr = &port->port_specific.g.gtlbia.csr;
225 csr = &port->port_specific.g.gtlbiv.csr;
232 *csr = value;
234 *csr;
243 pctl.pctl_q_whole = port->pctl.csr;
296 saved_config[index].wsba[0] = port->wsba[0].csr;
297 saved_config[index].wsm[0] = port->wsm[0].csr;
298 saved_config[index].tba[0] = port->tba[0].csr;
300 saved_config[index].wsba[1] = port->wsba[1].csr;
301 saved_config[index].wsm[1] = port->wsm[1].csr;
302 saved_config[index].tba[1] = port->tba[1].csr;
304 saved_config[index].wsba[2] = port->wsba[2].csr;
305 saved_config[index].wsm[2] = port->wsm[2].csr;
306 saved_config[index].tba[2] = port->tba[2].csr;
308 saved_config[index].wsba[3] = port->wsba[3].csr;
309 saved_config[index].wsm[3] = port->wsm[3].csr;
310 saved_config[index].tba[3] = port->tba[3].csr;
327 port->wsba[0].csr = hose->sg_isa->dma_base | 3;
328 port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
329 port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
331 port->wsba[1].csr = __direct_map_base | 1;
332 port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000;
333 port->tba[1].csr = 0;
335 port->wsba[2].csr = hose->sg_pci->dma_base | 3;
336 port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000;
337 port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes);
339 port->wsba[3].csr = 0;
342 port->pctl.csr |= pctl_m_mwin;
348 port->port_specific.a.agplastwr.csr = __direct_map_base;
356 titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14;
391 port->wsba[0].csr = saved_config[index].wsba[0];
392 port->wsm[0].csr = saved_config[index].wsm[0];
393 port->tba[0].csr = saved_config[index].tba[0];
395 port->wsba[1].csr = saved_config[index].wsba[1];
396 port->wsm[1].csr = saved_config[index].wsm[1];
397 port->tba[1].csr = saved_config[index].tba[1];
399 port->wsba[2].csr = saved_config[index].wsba[2];
400 port->wsm[2].csr = saved_config[index].wsm[2];
401 port->tba[2].csr = saved_config[index].tba[2];
403 port->wsba[3].csr = saved_config[index].wsba[3];
404 port->wsm[3].csr = saved_config[index].wsm[3];
405 port->tba[3].csr = saved_config[index].tba[3];
629 pctl.pctl_q_whole = port->pctl.csr;
654 port->pctl.csr = pctl.pctl_q_whole;
767 pctl.pctl_q_whole = port->pctl.csr;