1/* 2 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl) 3 * 4 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net) 5 * 6 * Adapted from mac_scsinew.c: 7 */ 8/* 9 * Generic Macintosh NCR5380 driver 10 * 11 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov> 12 * 13 * derived in part from: 14 */ 15/* 16 * Generic Generic NCR5380 driver 17 * 18 * Copyright 1995, Russell King 19 * 20 * ALPHA RELEASE 1. 21 * 22 * For more information, please consult 23 * 24 * NCR 5380 Family 25 * SCSI Protocol Controller 26 * Databook 27 * 28 * NCR Microelectronics 29 * 1635 Aeroplaza Drive 30 * Colorado Springs, CO 80916 31 * 1+ (719) 578-3400 32 * 1+ (800) 334-5454 33 */ 34 35 36/* 37 * This is from mac_scsi.h, but hey, maybe this is useful for Sun3 too! :) 38 * 39 * Options : 40 * 41 * PARITY - enable parity checking. Not supported. 42 * 43 * SCSI2 - enable support for SCSI-II tagged queueing. Untested. 44 * 45 * USLEEP - enable support for devices that don't disconnect. Untested. 46 */ 47 48/* 49 * $Log: sun3_scsi.c,v $ 50 * Revision 1.1.1.1 2007/08/03 18:52:57 rnuti 51 * Importing Linux MIPS Kernel 2.6.22 52 * 53 */ 54 55#define AUTOSENSE 56 57#include <linux/types.h> 58#include <linux/stddef.h> 59#include <linux/ctype.h> 60#include <linux/delay.h> 61 62#include <linux/module.h> 63#include <linux/signal.h> 64#include <linux/ioport.h> 65#include <linux/init.h> 66#include <linux/blkdev.h> 67 68#include <asm/io.h> 69#include <asm/system.h> 70 71#include <asm/sun3ints.h> 72#include <asm/dvma.h> 73#include <asm/idprom.h> 74#include <asm/machines.h> 75 76/* dma on! */ 77#define REAL_DMA 78 79#include "scsi.h" 80#include "initio.h" 81#include <scsi/scsi_host.h> 82#include "sun3_scsi.h" 83 84static void NCR5380_print(struct Scsi_Host *instance); 85 86/* #define OLDDMA */ 87 88#define USE_WRAPPER 89/*#define RESET_BOOT */ 90#define DRIVER_SETUP 91 92#define NDEBUG 0 93 94/* 95 * BUG can be used to trigger a strange code-size related hang on 2.1 kernels 96 */ 97#ifdef BUG 98#undef RESET_BOOT 99#undef DRIVER_SETUP 100#endif 101 102/* #define SUPPORT_TAGS */ 103 104#define ENABLE_IRQ() enable_irq( IRQ_SUN3_SCSI ); 105 106 107static irqreturn_t scsi_sun3_intr(int irq, void *dummy); 108static inline unsigned char sun3scsi_read(int reg); 109static inline void sun3scsi_write(int reg, int value); 110 111static int setup_can_queue = -1; 112module_param(setup_can_queue, int, 0); 113static int setup_cmd_per_lun = -1; 114module_param(setup_cmd_per_lun, int, 0); 115static int setup_sg_tablesize = -1; 116module_param(setup_sg_tablesize, int, 0); 117#ifdef SUPPORT_TAGS 118static int setup_use_tagged_queuing = -1; 119module_param(setup_use_tagged_queuing, int, 0); 120#endif 121static int setup_hostid = -1; 122module_param(setup_hostid, int, 0); 123 124static struct scsi_cmnd *sun3_dma_setup_done = NULL; 125 126#define AFTER_RESET_DELAY (HZ/2) 127 128/* ms to wait after hitting dma regs */ 129#define SUN3_DMA_DELAY 10 130 131/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */ 132#define SUN3_DVMA_BUFSIZE 0xe000 133 134/* minimum number of bytes to do dma on */ 135#define SUN3_DMA_MINSIZE 128 136 137static volatile unsigned char *sun3_scsi_regp; 138static volatile struct sun3_dma_regs *dregs; 139#ifdef OLDDMA 140static unsigned char *dmabuf = NULL; /* dma memory buffer */ 141#endif 142static struct sun3_udc_regs *udc_regs = NULL; 143static unsigned char *sun3_dma_orig_addr = NULL; 144static unsigned long sun3_dma_orig_count = 0; 145static int sun3_dma_active = 0; 146static unsigned long last_residual = 0; 147 148/* 149 * NCR 5380 register access functions 150 */ 151 152static inline unsigned char sun3scsi_read(int reg) 153{ 154 return( sun3_scsi_regp[reg] ); 155} 156 157static inline void sun3scsi_write(int reg, int value) 158{ 159 sun3_scsi_regp[reg] = value; 160} 161 162/* dma controller register access functions */ 163 164static inline unsigned short sun3_udc_read(unsigned char reg) 165{ 166 unsigned short ret; 167 168 dregs->udc_addr = UDC_CSR; 169 udelay(SUN3_DMA_DELAY); 170 ret = dregs->udc_data; 171 udelay(SUN3_DMA_DELAY); 172 173 return ret; 174} 175 176static inline void sun3_udc_write(unsigned short val, unsigned char reg) 177{ 178 dregs->udc_addr = reg; 179 udelay(SUN3_DMA_DELAY); 180 dregs->udc_data = val; 181 udelay(SUN3_DMA_DELAY); 182} 183 184static struct Scsi_Host *default_instance; 185 186/* 187 * Function : int sun3scsi_detect(struct scsi_host_template * tpnt) 188 * 189 * Purpose : initializes mac NCR5380 driver based on the 190 * command line / compile time port and irq definitions. 191 * 192 * Inputs : tpnt - template for this SCSI adapter. 193 * 194 * Returns : 1 if a host adapter was found, 0 if not. 195 * 196 */ 197 198int sun3scsi_detect(struct scsi_host_template * tpnt) 199{ 200 unsigned long ioaddr; 201 static int called = 0; 202 struct Scsi_Host *instance; 203 204 /* check that this machine has an onboard 5380 */ 205 switch(idprom->id_machtype) { 206 case SM_SUN3|SM_3_50: 207 case SM_SUN3|SM_3_60: 208 break; 209 210 default: 211 return 0; 212 } 213 214 if(called) 215 return 0; 216 217 tpnt->proc_name = "Sun3 5380 SCSI"; 218 219 /* setup variables */ 220 tpnt->can_queue = 221 (setup_can_queue > 0) ? setup_can_queue : CAN_QUEUE; 222 tpnt->cmd_per_lun = 223 (setup_cmd_per_lun > 0) ? setup_cmd_per_lun : CMD_PER_LUN; 224 tpnt->sg_tablesize = 225 (setup_sg_tablesize >= 0) ? setup_sg_tablesize : SG_TABLESIZE; 226 227 if (setup_hostid >= 0) 228 tpnt->this_id = setup_hostid; 229 else { 230 /* use 7 as default */ 231 tpnt->this_id = 7; 232 } 233 234 ioaddr = (unsigned long)ioremap(IOBASE_SUN3_SCSI, PAGE_SIZE); 235 sun3_scsi_regp = (unsigned char *)ioaddr; 236 237 dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8); 238 239 if((udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs))) 240 == NULL) { 241 printk("SUN3 Scsi couldn't allocate DVMA memory!\n"); 242 return 0; 243 } 244#ifdef OLDDMA 245 if((dmabuf = dvma_malloc_align(SUN3_DVMA_BUFSIZE, 0x10000)) == NULL) { 246 printk("SUN3 Scsi couldn't allocate DVMA memory!\n"); 247 return 0; 248 } 249#endif 250#ifdef SUPPORT_TAGS 251 if (setup_use_tagged_queuing < 0) 252 setup_use_tagged_queuing = USE_TAGGED_QUEUING; 253#endif 254 255 instance = scsi_register (tpnt, sizeof(struct NCR5380_hostdata)); 256 if(instance == NULL) 257 return 0; 258 259 default_instance = instance; 260 261 instance->io_port = (unsigned long) ioaddr; 262 instance->irq = IRQ_SUN3_SCSI; 263 264 NCR5380_init(instance, 0); 265 266 instance->n_io_port = 32; 267 268 ((struct NCR5380_hostdata *)instance->hostdata)->ctrl = 0; 269 270 if (request_irq(instance->irq, scsi_sun3_intr, 271 0, "Sun3SCSI-5380", NULL)) { 272#ifndef REAL_DMA 273 printk("scsi%d: IRQ%d not free, interrupts disabled\n", 274 instance->host_no, instance->irq); 275 instance->irq = SCSI_IRQ_NONE; 276#else 277 printk("scsi%d: IRQ%d not free, bailing out\n", 278 instance->host_no, instance->irq); 279 return 0; 280#endif 281 } 282 283 printk("scsi%d: Sun3 5380 at port %lX irq", instance->host_no, instance->io_port); 284 if (instance->irq == SCSI_IRQ_NONE) 285 printk ("s disabled"); 286 else 287 printk (" %d", instance->irq); 288 printk(" options CAN_QUEUE=%d CMD_PER_LUN=%d release=%d", 289 instance->can_queue, instance->cmd_per_lun, 290 SUN3SCSI_PUBLIC_RELEASE); 291 printk("\nscsi%d:", instance->host_no); 292 NCR5380_print_options(instance); 293 printk("\n"); 294 295 dregs->csr = 0; 296 udelay(SUN3_DMA_DELAY); 297 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; 298 udelay(SUN3_DMA_DELAY); 299 dregs->fifo_count = 0; 300 301 called = 1; 302 303#ifdef RESET_BOOT 304 sun3_scsi_reset_boot(instance); 305#endif 306 307 return 1; 308} 309 310int sun3scsi_release (struct Scsi_Host *shpnt) 311{ 312 if (shpnt->irq != SCSI_IRQ_NONE) 313 free_irq (shpnt->irq, NULL); 314 315 iounmap((void *)sun3_scsi_regp); 316 317 return 0; 318} 319 320#ifdef RESET_BOOT 321/* 322 * Our 'bus reset on boot' function 323 */ 324 325static void sun3_scsi_reset_boot(struct Scsi_Host *instance) 326{ 327 unsigned long end; 328 329 NCR5380_local_declare(); 330 NCR5380_setup(instance); 331 332 /* 333 * Do a SCSI reset to clean up the bus during initialization. No 334 * messing with the queues, interrupts, or locks necessary here. 335 */ 336 337 printk( "Sun3 SCSI: resetting the SCSI bus..." ); 338 339 /* switch off SCSI IRQ - catch an interrupt without IRQ bit set else */ 340// sun3_disable_irq( IRQ_SUN3_SCSI ); 341 342 /* get in phase */ 343 NCR5380_write( TARGET_COMMAND_REG, 344 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); 345 346 /* assert RST */ 347 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST ); 348 349 /* The min. reset hold time is 25us, so 40us should be enough */ 350 udelay( 50 ); 351 352 /* reset RST and interrupt */ 353 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE ); 354 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); 355 356 for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); ) 357 barrier(); 358 359 /* switch on SCSI IRQ again */ 360// sun3_enable_irq( IRQ_SUN3_SCSI ); 361 362 printk( " done\n" ); 363} 364#endif 365 366const char * sun3scsi_info (struct Scsi_Host *spnt) { 367 return ""; 368} 369 370// safe bits for the CSR 371#define CSR_GOOD 0x060f 372 373static irqreturn_t scsi_sun3_intr(int irq, void *dummy) 374{ 375 unsigned short csr = dregs->csr; 376 int handled = 0; 377 378 if(csr & ~CSR_GOOD) { 379 if(csr & CSR_DMA_BUSERR) { 380 printk("scsi%d: bus error in dma\n", default_instance->host_no); 381 } 382 383 if(csr & CSR_DMA_CONFLICT) { 384 printk("scsi%d: dma conflict\n", default_instance->host_no); 385 } 386 handled = 1; 387 } 388 389 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { 390 NCR5380_intr(irq, dummy); 391 handled = 1; 392 } 393 394 return IRQ_RETVAL(handled); 395} 396 397/* 398 * Debug stuff - to be called on NMI, or sysrq key. Use at your own risk; 399 * reentering NCR5380_print_status seems to have ugly side effects 400 */ 401 402/* this doesn't seem to get used at all -- sam */ 403 404 405/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */ 406static unsigned long sun3scsi_dma_setup(void *data, unsigned long count, int write_flag) 407{ 408#ifdef OLDDMA 409 if(write_flag) 410 memcpy(dmabuf, data, count); 411 else { 412 sun3_dma_orig_addr = data; 413 sun3_dma_orig_count = count; 414 } 415#else 416 void *addr; 417 418 if(sun3_dma_orig_addr != NULL) 419 dvma_unmap(sun3_dma_orig_addr); 420 421// addr = sun3_dvma_page((unsigned long)data, (unsigned long)dmabuf); 422 addr = (void *)dvma_map((unsigned long) data, count); 423 424 sun3_dma_orig_addr = addr; 425 sun3_dma_orig_count = count; 426#endif 427 dregs->fifo_count = 0; 428 sun3_udc_write(UDC_RESET, UDC_CSR); 429 430 /* reset fifo */ 431 dregs->csr &= ~CSR_FIFO; 432 dregs->csr |= CSR_FIFO; 433 434 /* set direction */ 435 if(write_flag) 436 dregs->csr |= CSR_SEND; 437 else 438 dregs->csr &= ~CSR_SEND; 439 440 /* byte count for fifo */ 441 dregs->fifo_count = count; 442 443 sun3_udc_write(UDC_RESET, UDC_CSR); 444 445 /* reset fifo */ 446 dregs->csr &= ~CSR_FIFO; 447 dregs->csr |= CSR_FIFO; 448 449 if(dregs->fifo_count != count) { 450 printk("scsi%d: fifo_mismatch %04x not %04x\n", 451 default_instance->host_no, dregs->fifo_count, 452 (unsigned int) count); 453 NCR5380_print(default_instance); 454 } 455 456 /* setup udc */ 457#ifdef OLDDMA 458 udc_regs->addr_hi = ((dvma_vtob(dmabuf) & 0xff0000) >> 8); 459 udc_regs->addr_lo = (dvma_vtob(dmabuf) & 0xffff); 460#else 461 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8); 462 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff); 463#endif 464 udc_regs->count = count/2; /* count in words */ 465 udc_regs->mode_hi = UDC_MODE_HIWORD; 466 if(write_flag) { 467 if(count & 1) 468 udc_regs->count++; 469 udc_regs->mode_lo = UDC_MODE_LSEND; 470 udc_regs->rsel = UDC_RSEL_SEND; 471 } else { 472 udc_regs->mode_lo = UDC_MODE_LRECV; 473 udc_regs->rsel = UDC_RSEL_RECV; 474 } 475 476 /* announce location of regs block */ 477 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8), 478 UDC_CHN_HI); 479 480 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO); 481 482 /* set dma master on */ 483 sun3_udc_write(0xd, UDC_MODE); 484 485 /* interrupt enable */ 486 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR); 487 488 return count; 489 490} 491 492static inline unsigned long sun3scsi_dma_count(struct Scsi_Host *instance) 493{ 494 unsigned short resid; 495 496 dregs->udc_addr = 0x32; 497 udelay(SUN3_DMA_DELAY); 498 resid = dregs->udc_data; 499 udelay(SUN3_DMA_DELAY); 500 resid *= 2; 501 502 return (unsigned long) resid; 503} 504 505static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance) 506{ 507 return last_residual; 508} 509 510static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted, 511 struct scsi_cmnd *cmd, 512 int write_flag) 513{ 514 if(blk_fs_request(cmd->request)) 515 return wanted; 516 else 517 return 0; 518} 519 520static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data) 521{ 522 523 sun3_udc_write(UDC_CHN_START, UDC_CSR); 524 525 return 0; 526} 527 528/* clean up after our dma is done */ 529static int sun3scsi_dma_finish(int write_flag) 530{ 531 unsigned short count; 532 unsigned short fifo; 533 int ret = 0; 534 535 sun3_dma_active = 0; 536 // check to empty the fifo on a read 537 if(!write_flag) { 538 int tmo = 20000; /* .2 sec */ 539 540 while(1) { 541 if(dregs->csr & CSR_FIFO_EMPTY) 542 break; 543 544 if(--tmo <= 0) { 545 printk("sun3scsi: fifo failed to empty!\n"); 546 return 1; 547 } 548 udelay(10); 549 } 550 } 551 552 553 count = sun3scsi_dma_count(default_instance); 554#ifdef OLDDMA 555 556 /* if we've finished a read, copy out the data we read */ 557 if(sun3_dma_orig_addr) { 558 /* check for residual bytes after dma end */ 559 if(count && (NCR5380_read(BUS_AND_STATUS_REG) & 560 (BASR_PHASE_MATCH | BASR_ACK))) { 561 printk("scsi%d: sun3_scsi_finish: read overrun baby... ", default_instance->host_no); 562 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG)); 563 ret = count; 564 } 565 566 /* copy in what we dma'd no matter what */ 567 memcpy(sun3_dma_orig_addr, dmabuf, sun3_dma_orig_count); 568 sun3_dma_orig_addr = NULL; 569 570 } 571#else 572 573 fifo = dregs->fifo_count; 574 last_residual = fifo; 575 576 /* empty bytes from the fifo which didn't make it */ 577 if((!write_flag) && (count - fifo) == 2) { 578 unsigned short data; 579 unsigned char *vaddr; 580 581 data = dregs->fifo_data; 582 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr); 583 584 vaddr += (sun3_dma_orig_count - fifo); 585 586 vaddr[-2] = (data & 0xff00) >> 8; 587 vaddr[-1] = (data & 0xff); 588 } 589 590 dvma_unmap(sun3_dma_orig_addr); 591 sun3_dma_orig_addr = NULL; 592#endif 593 sun3_udc_write(UDC_RESET, UDC_CSR); 594 dregs->fifo_count = 0; 595 dregs->csr &= ~CSR_SEND; 596 597 /* reset fifo */ 598 dregs->csr &= ~CSR_FIFO; 599 dregs->csr |= CSR_FIFO; 600 601 sun3_dma_setup_done = NULL; 602 603 return ret; 604 605} 606 607#include "sun3_NCR5380.c" 608 609static struct scsi_host_template driver_template = { 610 .name = SUN3_SCSI_NAME, 611 .detect = sun3scsi_detect, 612 .release = sun3scsi_release, 613 .info = sun3scsi_info, 614 .queuecommand = sun3scsi_queue_command, 615 .eh_abort_handler = sun3scsi_abort, 616 .eh_bus_reset_handler = sun3scsi_bus_reset, 617 .can_queue = CAN_QUEUE, 618 .this_id = 7, 619 .sg_tablesize = SG_TABLESIZE, 620 .cmd_per_lun = CMD_PER_LUN, 621 .use_clustering = DISABLE_CLUSTERING 622}; 623 624 625#include "scsi_module.c" 626 627MODULE_LICENSE("GPL"); 628