Searched refs:wr32 (Results 1 - 8 of 8) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/igb/ |
H A D | e1000_82575.c | 260 wr32(E1000_CTRL_EXT, ctrl_ext); 471 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 505 wr32(E1000_CTRL_EXT, ctrl_ext); 700 wr32(E1000_SW_FW_SYNC, swfw_sync); 725 wr32(E1000_SW_FW_SYNC, swfw_sync); 814 wr32(E1000_PCS_CFG0, reg); 819 wr32(E1000_CTRL_EXT, reg); 900 wr32(E1000_PCS_CFG0, reg); 905 wr32(E1000_CTRL_EXT, reg); 940 wr32(E1000_IM [all...] |
H A D | e1000_nvm.c | 44 wr32(E1000_EECD, *eecd); 59 wr32(E1000_EECD, *eecd); 90 wr32(E1000_EECD, eecd); 102 wr32(E1000_EECD, eecd); 189 wr32(E1000_EECD, eecd | E1000_EECD_REQ); 202 wr32(E1000_EECD, eecd); 224 wr32(E1000_EECD, eecd); 228 wr32(E1000_EECD, eecd); 266 wr32(E1000_EECD, eecd); 287 wr32(E1000_EEC [all...] |
H A D | igb_main.c | 850 wr32(E1000_CTRL_EXT, tmp); 864 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 872 wr32(E1000_IVAR_MISC, tmp); 1041 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1284 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1285 wr32(E1000_EIMC, adapter->eims_enable_mask); 1287 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1290 wr32(E1000_IAM, 0); 1291 wr32(E1000_IMC, ~0); 1313 wr32(E1000_EIA [all...] |
H A D | e1000_mac.c | 268 wr32(E1000_RAL(index), rar_low); 270 wr32(E1000_RAH(index), rar_high); 589 wr32(E1000_FCT, FLOW_CONTROL_TYPE); 590 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 591 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 593 wr32(E1000_FCTTV, hw->fc.pause_time); 618 wr32(E1000_TCTL, tctl); 654 wr32(E1000_FCRTL, fcrtl); 655 wr32(E1000_FCRTH, fcrth); 758 wr32(E1000_CTR [all...] |
H A D | e1000_mbx.c | 251 wr32(E1000_MBVFICR, mask); 309 wr32(E1000_VFLRE, (1 << vf_number)); 330 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); 369 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); 406 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK);
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H A D | igb_ethtool.c | 1071 wr32(reg, (_test[pat] & write)); 1090 wr32(reg, write & mask); 1148 wr32(E1000_STATUS, toggle); 1157 wr32(E1000_STATUS, before); 1274 wr32(E1000_IMC, ~0); 1314 wr32(E1000_ICR, ~0); 1316 wr32(E1000_IMC, mask); 1317 wr32(E1000_ICS, mask); 1335 wr32(E1000_ICR, ~0); 1337 wr32(E1000_IM [all...] |
H A D | e1000_phy.c | 160 wr32(E1000_MDIC, mdic); 219 wr32(E1000_MDIC, mdic); 271 wr32(E1000_I2CCMD, i2ccmd); 323 wr32(E1000_I2CCMD, i2ccmd); 1235 wr32(E1000_CTRL, ctrl); 1830 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 1835 wr32(E1000_CTRL, ctrl);
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H A D | e1000_regs.h | 315 #define wr32(reg, value) (writel(value, hw->hw_addr + reg)) macro
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