/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | amdgpu_vega12_hwmgr.c | 541 dpm_table->dpm_levels[i].value = clk; 542 dpm_table->dpm_levels[i].enabled = true; 575 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 588 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 601 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 614 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 627 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 640 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 653 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 718 dpm_table->dpm_levels[min_leve [all...] |
H A D | amdgpu_vega20_hwmgr.c | 587 dpm_table->dpm_levels[i].value = clk; 588 dpm_table->dpm_levels[i].enabled = true; 609 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 630 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 662 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 689 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 702 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 715 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 728 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 774 dpm_table->dpm_levels[ [all...] |
H A D | amdgpu_vega10_hwmgr.c | 1243 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= 1245 dpm_table->dpm_levels[dpm_table->count].value = 1247 dpm_table->dpm_levels[dpm_table->count].enabled = true; 1361 dpm_table->dpm_levels[dpm_table->count-1].value; 1372 dpm_table->dpm_levels[dpm_table->count-1].value; 1378 if (i == 0 || dpm_table->dpm_levels 1381 dpm_table->dpm_levels[dpm_table->count].value = 1383 dpm_table->dpm_levels[dpm_table->count].enabled = 1394 if (i == 0 || dpm_table->dpm_levels 1397 dpm_table->dpm_levels[dpm_tabl [all...] |
H A D | amdgpu_smu7_hwmgr.c | 703 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != 705 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 707 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; 717 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != 719 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 721 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; 728 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 729 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; 731 data->dpm_table.vddc_table.dpm_levels[i].enabled = true; 740 data->dpm_table.vddci_table.dpm_levels[ [all...] |
H A D | smu7_hwmgr.h | 102 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member in struct:smu7_single_dpm_table
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H A D | vega10_hwmgr.h | 138 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member in struct:vega10_single_dpm_table
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H A D | vega12_hwmgr.h | 112 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member in struct:vega12_single_dpm_table
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H A D | vega20_hwmgr.h | 164 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member in struct:vega20_single_dpm_table
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
H A D | amdgpu_vega20_ppt.c | 707 single_dpm_table->dpm_levels[i].value = clk; 708 single_dpm_table->dpm_levels[i].enabled = true; 743 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 759 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 775 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 790 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100; 805 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 820 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 836 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 917 smu->pstate_sclk = gfx_table->dpm_levels[ [all...] |
H A D | arcturus_ppt.h | 51 struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER]; member in struct:arcturus_single_dpm_table
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H A D | vega20_ppt.h | 101 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member in struct:vega20_single_dpm_table
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H A D | amdgpu_arcturus_ppt.c | 407 single_dpm_table->dpm_levels[i].value = clk; 408 single_dpm_table->dpm_levels[i].enabled = true; 442 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 457 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 472 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 487 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 580 smu->pstate_sclk = gfx_table->dpm_levels[0].value; 581 smu->pstate_mclk = mem_table->dpm_levels[0].value; 585 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value; 586 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVE [all...] |
H A D | amdgpu_navi10_ppt.c | 1637 uint16_t *dpm_levels = NULL; local 1647 dpm_levels = driver_ppt->FreqTableUclk; 1649 if (num_discrete_levels == 0 || dpm_levels == NULL) 1655 *clocks_in_khz = (*dpm_levels) * 1000; 1657 dpm_levels++;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_ci_dpm.c | 2564 pi->dpm_table.sclk_table.dpm_levels[i].value, 2565 pi->dpm_table.mclk_table.dpm_levels[j].value, 2623 if (dpm_table->dpm_levels[i-1].enabled) 2641 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; 2643 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 3297 dpm_table->sclk_table.dpm_levels[i].value, 3343 if (dpm_table->mclk_table.dpm_levels[i].value == 0) 3346 dpm_table->mclk_table.dpm_levels[i].value, 3388 dpm_table->dpm_levels[i].enabled = false; 3394 dpm_table->dpm_levels[inde [all...] |
H A D | ci_dpm.h | 67 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member in struct:ci_single_dpm_table
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
H A D | amdgpu_fiji_smumgr.c | 845 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 847 dpm_table->pcie_speed_table.dpm_levels[i].param1); 1031 dpm_table->sclk_table.dpm_levels[i].value, 1242 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1246 dpm_table->mclk_table.dpm_levels[i].value, 1323 data->dpm_table.sclk_table.dpm_levels[0].value; 1381 data->dpm_table.mclk_table.dpm_levels[0].value; 1402 data->dpm_table.mclk_table.dpm_levels[0].value, 1542 data->dpm_table.sclk_table.dpm_levels[i].value, 1543 data->dpm_table.mclk_table.dpm_levels[ [all...] |
H A D | amdgpu_iceland_smumgr.c | 779 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 781 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 987 dpm_table->sclk_table.dpm_levels[i].value, 1367 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1369 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, 1629 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, 1630 data->dpm_table.mclk_table.dpm_levels[j].value, 1769 data->dpm_table.mclk_table.dpm_levels[i].value,
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H A D | amdgpu_vegam_smumgr.c | 585 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 587 dpm_table->pcie_speed_table.dpm_levels[i].param1); 893 dpm_table->sclk_table.dpm_levels[i].value, 1052 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1056 dpm_table->mclk_table.dpm_levels[i].value, 1292 hw_data->dpm_table.sclk_table.dpm_levels[i].value, 1293 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
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H A D | amdgpu_polaris10_smumgr.c | 783 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 785 dpm_table->pcie_speed_table.dpm_levels[i].param1); 1009 dpm_table->sclk_table.dpm_levels[i].value, 1145 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1149 dpm_table->mclk_table.dpm_levels[i].value, 1267 data->dpm_table.mclk_table.dpm_levels[0].value, 1378 hw_data->dpm_table.sclk_table.dpm_levels[i].value, 1379 hw_data->dpm_table.mclk_table.dpm_levels[j].value, 1382 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
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H A D | amdgpu_ci_smumgr.c | 491 dpm_table->sclk_table.dpm_levels[i].value, 1010 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 1012 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 1320 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1322 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, 1666 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, 1667 data->dpm_table.mclk_table.dpm_levels[j].value, 1802 data->dpm_table.mclk_table.dpm_levels[i].value,
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H A D | amdgpu_tonga_smumgr.c | 522 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 524 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 717 dpm_table->sclk_table.dpm_levels[i].value, 1113 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1118 dpm_table->mclk_table.dpm_levels[i].value, 1505 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, 1506 data->dpm_table.mclk_table.dpm_levels[j].value, 2148 data->dpm_table.mclk_table.dpm_levels[i].value,
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