Searched refs:SVE (Results 1 - 25 of 26) sorted by relevance

12

/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/aarch64/
H A Dsve-movprfx_15.l2 .*: Warning: SVE `movprfx' compatible instruction expected -- `orr z1.d,z3.d,z2.d'
H A Dsve-movprfx_20.l2 .*: Warning: SVE `movprfx' compatible instruction expected -- `add z1.s,z2.s,z2.s'
H A Dsve-movprfx_24.l2 .*: Warning: SVE `movprfx' compatible instruction expected -- `bic z1.D,z1.D,z2.D'
3 .*: Warning: SVE `movprfx' compatible instruction expected -- `bic z1.D,z1.D,z2.D'
H A Dsve-movprfx_28.l4 .*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
5 .*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
6 .*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
7 .*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
8 .*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
H A Dsve-movprfx_9.l2 .*: Warning: SVE instruction expected after `movprfx' -- `mov x0,sp'
H A Dsve-reg-diagnostic.d1 #name: Diagnostics Quality (SVE registers)
H A Dsve-invalid.d1 #name: Invalid SVE instructions
H A Dillegal-sve2.l11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
12 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclb z0\.d,z32\.d,z0\.d'
13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
20 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclt z0\.s,z32\.s,z0\.s'
21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
29 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnb z0\.b,z32\.h,z0\.h'
30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
37 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vecto
[all...]
H A Dillegal-bfloat16.l28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h'
29 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h'
30 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\.h'
35 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
36 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
41 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h'
42 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h'
43 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalb z0\.s,z0\.h,z32\.h'
48 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
49 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vecto
[all...]
H A Dsve-invalid.l2 .*: Error: operand 2 must be an SVE predicate register -- `fmov z1,z2'
129 .*: Error: operand 1 must be an SVE vector register -- `movprfx p0,p1'
187 .*: Error: operand 2 must be an SVE predicate register -- `mov p0\.b,p16\.b'
278 .*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {x0},p1/z,\[x1\]'
279 .*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {b0},p1/z,\[x1\]'
280 .*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {h0},p1/z,\[x1\]'
281 .*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {s0},p1/z,\[x1\]'
282 .*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {d0},p1/z,\[x1\]'
283 .*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {v0\.2s},p1/z,\[x1\]'
862 .*: Error: operand 3 must be an SVE vecto
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.arch/
H A Daarch64-sighandler-regs.c52 #ifdef SVE
123 #ifdef SVE
/netbsd-current/external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/
H A Daarch64-sighandler-regs.c52 #ifdef SVE
123 #ifdef SVE
/netbsd-current/external/apache2/llvm/dist/clang/include/clang/Basic/
H A DTargetBuiltins.h46 namespace SVE { namespace in namespace:clang
61 LastSVEBuiltin = SVE::FirstTSBuiltin - 1,
181 /// Flags to identify the types for overloaded SVE builtins.
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DVFABIDemangling.cpp37 .Case("s", VFISAKind::SVE)
/netbsd-current/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGBuiltin.cpp6210 #NameBase, SVE::BI__builtin_sve_##NameBase, Intrinsic::LLVMIntrinsic, 0, \
6215 { #NameBase, SVE::BI__builtin_sve_##NameBase, 0, 0, TypeModifier }
8872 if (BuiltinID >= SVE::BI__builtin_sve_reinterpret_s8_s8 &&
8873 BuiltinID <= SVE::BI__builtin_sve_reinterpret_f64_f64) {
8889 // Immediates for SVE llvm intrinsics are always 32bit. We can safely
8975 case SVE::BI__builtin_sve_svmov_b_z: {
8983 case SVE::BI__builtin_sve_svnot_b_z: {
8991 case SVE::BI__builtin_sve_svmovlb_u16:
8992 case SVE::BI__builtin_sve_svmovlb_u32:
8993 case SVE
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DVectorUtils.h46 SVE, // AArch64 Scalable Vector Extension member in class:llvm::VFISAKind
/netbsd-current/external/gpl3/binutils/dist/include/opcode/
H A Daarch64.h96 /* SVE instructions. */
314 | AARCH64_FEATBIT (X, SVE) \
614 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
615 AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
616 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
617 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
618 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
619 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
620 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
621 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<X
[all...]
/netbsd-current/external/gpl3/binutils/dist/gas/config/
H A Dtc-aarch64.c307 /* Typecheck: same, plus SVE registers. */ \
313 /* Typecheck: same, plus SVE registers. */ \
333 be used for SVE instructions, since Zn and Pn are valid symbols \
354 /* An SVE vector or predicate register. */ \
466 return N_("expected an SVE vector register at operand %d");
473 return N_("expected an SVE predicate register at operand %d");
475 return N_("expected an SVE predicate-as-counter register at operand %d");
479 return N_("expected an SVE vector or predicate register at operand %d");
498 return N_("expected an integer register or SVE vector register"
508 /* SVE an
[all...]
/netbsd-current/external/gpl3/binutils/dist/opcodes/
H A Daarch64-tbl.h1459 /* The naming convention for SVE macros is:
1470 - .[BHSDQ] suffixes on an SVE vector or predicate
2520 Any SVE or SVE2 feature must include AARCH64_FEATURE_{SVE|SVE2} in its
2522 allows verify_constraints to identify SVE instructions when selecting an
2546 AARCH64_FEATURE (SVE);
2584 AARCH64_FEATURES (2, BFLOAT16, SVE);
2612 AARCH64_FEATURES (2, I8MM, SVE);
2614 AARCH64_FEATURES (2, F32MM, SVE);
2616 AARCH64_FEATURES (2, F64MM, SVE);
2664 #define SVE macro
[all...]
H A Daarch64-opc.c38 /* The enumeration strings associated with each value of a 5-bit SVE
79 /* The enumeration strings associated with each value of a 4-bit SVE
276 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
285 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
286 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
290 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
291 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
292 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
293 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
294 { 16, 5 }, /* SVE_Zm_16: SVE vecto
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/opcodes/
H A Daarch64-opc.c38 /* The enumeration strings associated with each value of a 5-bit SVE
79 /* The enumeration strings associated with each value of a 4-bit SVE
276 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
285 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
286 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
290 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
291 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
292 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
293 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
294 { 16, 5 }, /* SVE_Zm_16: SVE vecto
[all...]
H A Daarch64-tbl.h1427 /* The naming convention for SVE macros is:
1437 .[BHSD] suffixes on an SVE predicate or vector register and
2426 #define SVE &aarch64_feature_sve
2483 { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
2486 { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
3909 /* SVE instructions. */
5484 "an SVE predicate register") \
5486 "an SVE predicate register") \
5488 "an SVE predicate register") \
5490 "an SVE predicat
2423 #define SVE macro
[all...]
/netbsd-current/external/gpl3/gdb/dist/opcodes/
H A Daarch64-tbl.h1433 /* The naming convention for SVE macros is:
1443 .[BHSD] suffixes on an SVE predicate or vector register and
2527 #define SVE &aarch64_feature_sve
2595 { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
2598 { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
4113 /* SVE instructions. */
5826 "an SVE predicate register") \
5828 "an SVE predicate register") \
5830 "an SVE predicate register") \
5832 "an SVE predicat
2524 #define SVE macro
[all...]
H A Daarch64-opc.c38 /* The enumeration strings associated with each value of a 5-bit SVE
79 /* The enumeration strings associated with each value of a 4-bit SVE
277 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
286 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
287 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
291 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
293 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
294 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
295 { 16, 5 }, /* SVE_Zm_16: SVE vecto
[all...]
/netbsd-current/external/gpl3/binutils.old/dist/opcodes/
H A Daarch64-tbl.h1433 /* The naming convention for SVE macros is:
1443 .[BHSD] suffixes on an SVE predicate or vector register and
2516 #define SVE &aarch64_feature_sve
2583 { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
2586 { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
4098 /* SVE instructions. */
5796 "an SVE predicate register") \
5798 "an SVE predicate register") \
5800 "an SVE predicate register") \
5802 "an SVE predicat
2513 #define SVE macro
[all...]

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