gas/config/tc-aarch64.c

307   /* Typecheck: same, plus SVE registers.  */				\
313   /* Typecheck: same, plus SVE registers.  */				\
333      be used for SVE instructions, since Zn and Pn are valid symbols	\
354   /* An SVE vector or predicate register.  */				\
466     return N_("expected an SVE vector register at operand %d");
473     return N_("expected an SVE predicate register at operand %d");
475     return N_("expected an SVE predicate-as-counter register at operand %d");
479     return N_("expected an SVE vector or predicate register at operand %d");
498     return N_("expected an integer register or SVE vector register"
508   /* SVE and SME combos.  */
510     return N_("expected an SVE vector register or ZA tile slice"
949 /* Try to parse a base or offset register.  Allow SVE base and offset
950    registers if REG_TYPE includes SVE registers.  Return the register
1097 /* *STR contains an SVE zero/merge predication suffix.  Parse it into
2606   /* Check for unsuffixed SVE registers, which are allowed
3836    SVE:
4193 /* Parse a base AArch64 address (as opposed to an SVE one).  Return TRUE
4203 /* Parse an address in which SVE vector registers and MUL VL are allowed.
6496   else if (AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE)
7542 	     but recognizing SVE registers.  */
7570 	     but recognizing SVE registers.  */
7597 	     but recognizing SVE registers.  */
8613   /* SVE vector registers.  */
8616   /* SVE predicate(-as-mask) registers.  */
8619   /* SVE predicate-as-counter registers.  */
10295 					      SVE, SVE2, SVE2_BITPERM, MEMTAG,
10297   {"neoverse-v1",	AARCH64_CPU_FEATURES (V8_4A, 8, PROFILE, CVADP, SVE,
10381   {"sve",		AARCH64_FEATURE (SVE), AARCH64_FEATURE (COMPNUM)},
10402   {"sve2",		AARCH64_FEATURE (SVE2), AARCH64_FEATURE (SVE)},
10420   {"f32mm",		AARCH64_FEATURE (F32MM), AARCH64_FEATURE (SVE)},
10421   {"f64mm",		AARCH64_FEATURE (F64MM), AARCH64_FEATURE (SVE)},