dist/opcodes/aarch64-opc.c

38 /* The enumeration strings associated with each value of a 5-bit SVE
79 /* The enumeration strings associated with each value of a 4-bit SVE
276     { 17,  1 }, /* SVE_N: SVE equivalent of N.  */
285     {  5,  5 }, /* SVE_Rm: SVE alternative position for Rm.  */
286     { 16,  5 }, /* SVE_Rn: SVE alternative position for Rn.  */
290     {  5,  5 }, /* SVE_Za_5: SVE vector register, bits [9,5].  */
291     { 16,  5 }, /* SVE_Za_16: SVE vector register, bits [20,16].  */
292     {  0,  5 }, /* SVE_Zd: SVE vector register. bits [4,0].  */
293     {  5,  5 }, /* SVE_Zm_5: SVE vector register, bits [9,5].  */
294     { 16,  5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
295     {  5,  5 }, /* SVE_Zn: SVE vector register, bits [9,5].  */
296     {  0,  5 }, /* SVE_Zt: SVE vector register, bits [4,0].  */
310     { 11,  6 }, /* SVE_immr: SVE equivalent of immr.  */
311     {  5,  6 }, /* SVE_imms: SVE equivalent of imms.  */
314     {  0,  4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD].  */
1554    PREFIX is the register prefix, such as "z" for SVE vector registers.  */
3481 /* Names of the SVE vector registers, first with .S suffixes,
3534 /* Get the name of the SVE vector offset register in OPND, using the operand
5451 	  /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
5454 	      || (!AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE)
5458 	      mismatch_detail->error = _("SVE instruction expected after "
5466 	  /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
5471 	      mismatch_detail->error = _("SVE `movprfx' compatible instruction "
5665 /* Return true if VALUE cannot be moved into an SVE register using DUP