include/opcode/aarch64.h

96   /* SVE instructions.  */
314 					 | AARCH64_FEATBIT (X, SVE)	\
614   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
615   AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
616   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
617   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
618   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
619   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
620   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
621   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
622   AARCH64_OPND_SVE_ADDR_RI_U6,	    /* SVE [<Xn|SP>, #<uimm6>].  */
623   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
624   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
625   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
626   AARCH64_OPND_SVE_ADDR_R,	    /* SVE [<Xn|SP>].  */
627   AARCH64_OPND_SVE_ADDR_RR,	    /* SVE [<Xn|SP>, <Xm|XZR>].  */
628   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
629   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
630   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
631   AARCH64_OPND_SVE_ADDR_RR_LSL4,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4].  */
632   AARCH64_OPND_SVE_ADDR_RX,	    /* SVE [<Xn|SP>, <Xm>].  */
633   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
634   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
635   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
636   AARCH64_OPND_SVE_ADDR_ZX,	    /* SVE [Zn.<T>{, <Xm>}].  */
637   AARCH64_OPND_SVE_ADDR_RZ,	    /* SVE [<Xn|SP>, Zm.D].  */
638   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
639   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
640   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
641   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
643   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
645   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
647   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
649   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
651   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
653   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
655   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
657   AARCH64_OPND_SVE_ADDR_ZI_U5,	    /* SVE [Zn.<T>, #<uimm5>].  */
658   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
659   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
660   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
661   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
662   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
663   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
664   AARCH64_OPND_SVE_AIMM,	/* SVE unsigned arithmetic immediate.  */
665   AARCH64_OPND_SVE_ASIMM,	/* SVE signed arithmetic immediate.  */
666   AARCH64_OPND_SVE_FPIMM8,	/* SVE 8-bit floating-point immediate.  */
667   AARCH64_OPND_SVE_I1_HALF_ONE,	/* SVE choice between 0.5 and 1.0.  */
668   AARCH64_OPND_SVE_I1_HALF_TWO,	/* SVE choice between 0.5 and 2.0.  */
669   AARCH64_OPND_SVE_I1_ZERO_ONE,	/* SVE choice between 0.0 and 1.0.  */
670   AARCH64_OPND_SVE_IMM_ROT1,	/* SVE 1-bit rotate operand (90 or 270).  */
671   AARCH64_OPND_SVE_IMM_ROT2,	/* SVE 2-bit rotate operand (N*90).  */
672   AARCH64_OPND_SVE_IMM_ROT3,	/* SVE cadd 1-bit rotate (90 or 270).  */
673   AARCH64_OPND_SVE_INV_LIMM,	/* SVE inverted logical immediate.  */
674   AARCH64_OPND_SVE_LIMM,	/* SVE logical immediate.  */
675   AARCH64_OPND_SVE_LIMM_MOV,	/* SVE logical immediate for MOV.  */
676   AARCH64_OPND_SVE_PATTERN,	/* SVE vector pattern enumeration.  */
678   AARCH64_OPND_SVE_PRFOP,	/* SVE prefetch operation.  */
679   AARCH64_OPND_SVE_Pd,		/* SVE p0-p15 in Pd.  */
680   AARCH64_OPND_SVE_PNd,		/* SVE pn0-pn15 in Pd.  */
681   AARCH64_OPND_SVE_Pg3,		/* SVE p0-p7 in Pg.  */
682   AARCH64_OPND_SVE_Pg4_5,	/* SVE p0-p15 in Pg, bits [8,5].  */
683   AARCH64_OPND_SVE_Pg4_10,	/* SVE p0-p15 in Pg, bits [13,10].  */
684   AARCH64_OPND_SVE_PNg4_10,	/* SVE pn0-pn15 in Pg, bits [13,10].  */
685   AARCH64_OPND_SVE_Pg4_16,	/* SVE p0-p15 in Pg, bits [19,16].  */
686   AARCH64_OPND_SVE_Pm,		/* SVE p0-p15 in Pm.  */
687   AARCH64_OPND_SVE_Pn,		/* SVE p0-p15 in Pn.  */
688   AARCH64_OPND_SVE_PNn,		/* SVE pn0-pn15 in Pn.  */
689   AARCH64_OPND_SVE_Pt,		/* SVE p0-p15 in Pt.  */
690   AARCH64_OPND_SVE_PNt,		/* SVE pn0-pn15 in Pt.  */
691   AARCH64_OPND_SVE_Rm,		/* Integer Rm or ZR, alt. SVE position.  */
692   AARCH64_OPND_SVE_Rn_SP,	/* Integer Rn or SP, alt. SVE position.  */
693   AARCH64_OPND_SVE_SHLIMM_PRED,	  /* SVE shift left amount (predicated).  */
694   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
695   AARCH64_OPND_SVE_SHLIMM_UNPRED_22,	/* SVE 3 bit shift left unpred.  */
696   AARCH64_OPND_SVE_SHRIMM_PRED,	  /* SVE shift right amount (predicated).  */
697   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
698   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,	/* SVE 3 bit shift right unpred.  */
699   AARCH64_OPND_SVE_SIMM5,	/* SVE signed 5-bit immediate.  */
700   AARCH64_OPND_SVE_SIMM5B,	/* SVE secondary signed 5-bit immediate.  */
701   AARCH64_OPND_SVE_SIMM6,	/* SVE signed 6-bit immediate.  */
702   AARCH64_OPND_SVE_SIMM8,	/* SVE signed 8-bit immediate.  */
703   AARCH64_OPND_SVE_UIMM3,	/* SVE unsigned 3-bit immediate.  */
704   AARCH64_OPND_SVE_UIMM7,	/* SVE unsigned 7-bit immediate.  */
705   AARCH64_OPND_SVE_UIMM8,	/* SVE unsigned 8-bit immediate.  */
706   AARCH64_OPND_SVE_UIMM8_53,	/* SVE split unsigned 8-bit immediate.  */
719   AARCH64_OPND_SVE_Za_5,	/* SVE vector register in Za, bits [9,5].  */
720   AARCH64_OPND_SVE_Za_16,	/* SVE vector register in Za, bits [20,16].  */
721   AARCH64_OPND_SVE_Zd,		/* SVE vector register in Zd.  */
722   AARCH64_OPND_SVE_Zm_5,	/* SVE vector register in Zm, bits [9,5].  */
723   AARCH64_OPND_SVE_Zm_16,	/* SVE vector register in Zm, bits [20,16].  */
729   AARCH64_OPND_SVE_Zm_imm4,     /* SVE vector register with 4bit index.  */
731   AARCH64_OPND_SVE_Zn,		/* SVE vector register in Zn.  */
732   AARCH64_OPND_SVE_Zn_5_INDEX,	/* Indexed SVE vector register, for DUPQ.  */
733   AARCH64_OPND_SVE_Zn_INDEX,	/* Indexed SVE vector register, for DUP.  */
734   AARCH64_OPND_SVE_ZnxN,	/* SVE vector register list in Zn.  */
735   AARCH64_OPND_SVE_Zt,		/* SVE vector register in Zt.  */
736   AARCH64_OPND_SVE_ZtxN,	/* SVE vector register list in Zt.  */
737   AARCH64_OPND_SME_Zdnx2,	/* SVE vector register list from [4:1]*2.  */
738   AARCH64_OPND_SME_Zdnx4,	/* SVE vector register list from [4:2]*4.  */
739   AARCH64_OPND_SME_Zm,		/* SVE vector register list in 4-bit Zm.  */
740   AARCH64_OPND_SME_Zmx2,	/* SVE vector register list from [20:17]*2.  */
741   AARCH64_OPND_SME_Zmx4,	/* SVE vector register list from [20:18]*4.  */
742   AARCH64_OPND_SME_Znx2,	/* SVE vector register list from [9:6]*2.  */
743   AARCH64_OPND_SME_Znx4,	/* SVE vector register list from [9:7]*4.  */
744   AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23.  */
745   AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19.  */
799   AARCH64_OPND_SME_Zt2,		/* Qobule SVE vector register list.  */
800   AARCH64_OPND_SME_Zt3,		/* Trible SVE vector register list.  */
801   AARCH64_OPND_SME_Zt4,		/* Quad SVE vector register list.  */