Searched refs:SMU__NUM_SCLK_DPM_STATE (Results 1 - 22 of 22) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Dci_smumgr.h28 #define SMU__NUM_SCLK_DPM_STATE 8 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dkv_dpm.h28 #define SMU__NUM_SCLK_DPM_STATE 8 macro
159 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
H A Damdgpu_kv_dpm.c2883 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
3305 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dkv_dpm.h28 #define SMU__NUM_SCLK_DPM_STATE 8 macro
133 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
H A Dsmu7.h43 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dci_dpm.h31 #define SMU__NUM_SCLK_DPM_STATE 8 macro
H A Dsmu7_fusion.h235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
H A Dsmu7_discrete.h237 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dradeon_kv_dpm.c2819 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2842 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dsmu7.h43 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dsmu71.h33 #define SMU__NUM_SCLK_DPM_STATE 8 macro
63 #define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
H A Dsmu72.h33 #define SMU__NUM_SCLK_DPM_STATE 8 macro
111 #define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
H A Dsmu73.h95 #define SMU__NUM_SCLK_DPM_STATE 8 macro
110 #define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dsmu7_fusion.h235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
H A Dsmu74.h34 #define SMU__NUM_SCLK_DPM_STATE 8 macro
136 #define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
H A Dsmu75.h42 #define SMU__NUM_SCLK_DPM_STATE 8 macro
57 #define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
H A Dsmu71_discrete.h181 SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu7_discrete.h237 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu72_discrete.h168 SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu73_discrete.h158 SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu74_discrete.h181 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu75_discrete.h194 SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];

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