1154484Sjhb/* $NetBSD: smu72.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2154484Sjhb 3154484Sjhb/* 4154484Sjhb * Copyright 2017 Advanced Micro Devices, Inc. 5154484Sjhb * 6154484Sjhb * Permission is hereby granted, free of charge, to any person obtaining a 7154484Sjhb * copy of this software and associated documentation files (the "Software"), 8154484Sjhb * to deal in the Software without restriction, including without limitation 9154484Sjhb * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10154484Sjhb * and/or sell copies of the Software, and to permit persons to whom the 11154484Sjhb * Software is furnished to do so, subject to the following conditions: 12154484Sjhb * 13154484Sjhb * The above copyright notice and this permission notice shall be included in 14154484Sjhb * all copies or substantial portions of the Software. 15154484Sjhb * 16154484Sjhb * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17154484Sjhb * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18154484Sjhb * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19154484Sjhb * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20154484Sjhb * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21154484Sjhb * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22154484Sjhb * OTHER DEALINGS IN THE SOFTWARE. 23154484Sjhb * 24154484Sjhb */ 25154484Sjhb 26154484Sjhb#ifndef SMU72_H 27154484Sjhb#define SMU72_H 28154484Sjhb 29154484Sjhb#if !defined(SMC_MICROCODE) 30154484Sjhb#pragma pack(push, 1) 31154484Sjhb#endif 32154484Sjhb 33154484Sjhb#define SMU__NUM_SCLK_DPM_STATE 8 34154484Sjhb#define SMU__NUM_MCLK_DPM_LEVELS 4 35154484Sjhb#define SMU__NUM_LCLK_DPM_LEVELS 8 36154484Sjhb#define SMU__NUM_PCIE_DPM_LEVELS 8 37154484Sjhb 38154485Sjhbenum SID_OPTION { 39164159Skmacy SID_OPTION_HI, 40154485Sjhb SID_OPTION_LO, 41154484Sjhb SID_OPTION_COUNT 42154484Sjhb}; 43154484Sjhb 44154485Sjhbenum Poly3rdOrderCoeff { 45154484Sjhb LEAKAGE_TEMPERATURE_SCALAR, 46164159Skmacy LEAKAGE_VOLTAGE_SCALAR, 47164159Skmacy DYNAMIC_VOLTAGE_SCALAR, 48164159Skmacy POLY_3RD_ORDER_COUNT 49154484Sjhb}; 50154484Sjhb 51154484Sjhbstruct SMU7_Poly3rdOrder_Data { 52154484Sjhb int32_t a; 53154484Sjhb int32_t b; 54154484Sjhb int32_t c; 55154484Sjhb int32_t d; 56154484Sjhb uint8_t a_shift; 57154484Sjhb uint8_t b_shift; 58154484Sjhb uint8_t c_shift; 59154484Sjhb uint8_t x_shift; 60154941Sjhb}; 61154484Sjhb 62154484Sjhbtypedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; 63164159Skmacy 64164159Skmacystruct Power_Calculator_Data { 65164159Skmacy uint16_t NoLoadVoltage; 66164159Skmacy uint16_t LoadVoltage; 67164159Skmacy uint16_t Resistance; 68164159Skmacy uint16_t Temperature; 69164159Skmacy uint16_t BaseLeakage; 70164159Skmacy uint16_t LkgTempScalar; 71164159Skmacy uint16_t LkgVoltScalar; 72164159Skmacy uint16_t LkgAreaScalar; 73164159Skmacy uint16_t LkgPower; 74164159Skmacy uint16_t DynVoltScalar; 75164159Skmacy uint32_t Cac; 76164159Skmacy uint32_t DynPower; 77164159Skmacy uint32_t TotalCurrent; 78164159Skmacy uint32_t TotalPower; 79164159Skmacy}; 80164159Skmacy 81164159Skmacytypedef struct Power_Calculator_Data PowerCalculatorData_t; 82164159Skmacy 83164159Skmacystruct Gc_Cac_Weight_Data { 84164159Skmacy uint8_t index; 85164159Skmacy uint32_t value; 86164159Skmacy}; 87164159Skmacy 88164159Skmacytypedef struct Gc_Cac_Weight_Data GcCacWeight_Data; 89164159Skmacy 90164159Skmacy 91164159Skmacytypedef struct { 92164159Skmacy uint32_t high; 93164159Skmacy uint32_t low; 94164159Skmacy} data_64_t; 95164159Skmacy 96164159Skmacytypedef struct { 97164159Skmacy data_64_t high; 98164159Skmacy data_64_t low; 99164159Skmacy} data_128_t; 100164159Skmacy 101164159Skmacy#define SMU7_CONTEXT_ID_SMC 1 102164159Skmacy#define SMU7_CONTEXT_ID_VBIOS 2 103164159Skmacy 104164159Skmacy#define SMU72_MAX_LEVELS_VDDC 16 105164159Skmacy#define SMU72_MAX_LEVELS_VDDGFX 16 106164159Skmacy#define SMU72_MAX_LEVELS_VDDCI 8 107164159Skmacy#define SMU72_MAX_LEVELS_MVDD 4 108164159Skmacy 109164159Skmacy#define SMU_MAX_SMIO_LEVELS 4 110164159Skmacy 111164159Skmacy#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */ 112164159Skmacy#define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */ 113164159Skmacy#define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */ 114164159Skmacy#define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */ 115164159Skmacy#define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */ 116164159Skmacy#define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */ 117164159Skmacy#define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */ 118164159Skmacy#define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */ 119164159Skmacy#define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */ 120164159Skmacy 121164159Skmacy#define DPM_NO_LIMIT 0 122164159Skmacy#define DPM_NO_UP 1 123164159Skmacy#define DPM_GO_DOWN 2 124164159Skmacy#define DPM_GO_UP 3 125164159Skmacy 126164159Skmacy#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 127164159Skmacy#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 128164159Skmacy 129164159Skmacy#define GPIO_CLAMP_MODE_VRHOT 1 130164159Skmacy#define GPIO_CLAMP_MODE_THERM 2 131164159Skmacy#define GPIO_CLAMP_MODE_DC 4 132164159Skmacy 133164159Skmacy#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 134164159Skmacy#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 135164159Skmacy#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 136164159Skmacy#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 137164159Skmacy#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 138164159Skmacy#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 139164159Skmacy#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 140164159Skmacy#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 141164159Skmacy#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 142164159Skmacy#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 143164159Skmacy#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 144164159Skmacy#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 145164159Skmacy#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 146164159Skmacy#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 147164159Skmacy#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 148164159Skmacy#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 149164159Skmacy#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 150164159Skmacy#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 151164159Skmacy#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 152164159Skmacy#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 153164159Skmacy 154164159Skmacy/* Virtualization Defines */ 155164159Skmacy#define CG_XDMA_MASK 0x1 156164159Skmacy#define CG_XDMA_SHIFT 0 157164159Skmacy#define CG_UVD_MASK 0x2 158164159Skmacy#define CG_UVD_SHIFT 1 159164159Skmacy#define CG_VCE_MASK 0x4 160164159Skmacy#define CG_VCE_SHIFT 2 161164159Skmacy#define CG_SAMU_MASK 0x8 162164159Skmacy#define CG_SAMU_SHIFT 3 163164159Skmacy#define CG_GFX_MASK 0x10 164164159Skmacy#define CG_GFX_SHIFT 4 165164159Skmacy#define CG_SDMA_MASK 0x20 166164159Skmacy#define CG_SDMA_SHIFT 5 167164159Skmacy#define CG_HDP_MASK 0x40 168164159Skmacy#define CG_HDP_SHIFT 6 169164159Skmacy#define CG_MC_MASK 0x80 170164159Skmacy#define CG_MC_SHIFT 7 171164159Skmacy#define CG_DRM_MASK 0x100 172164159Skmacy#define CG_DRM_SHIFT 8 173164159Skmacy#define CG_ROM_MASK 0x200 174164159Skmacy#define CG_ROM_SHIFT 9 175164159Skmacy#define CG_BIF_MASK 0x400 176164159Skmacy#define CG_BIF_SHIFT 10 177164159Skmacy 178164159Skmacy#define SMU72_DTE_ITERATIONS 5 179164159Skmacy#define SMU72_DTE_SOURCES 3 180164159Skmacy#define SMU72_DTE_SINKS 1 181164159Skmacy#define SMU72_NUM_CPU_TES 0 182164159Skmacy#define SMU72_NUM_GPU_TES 1 183164159Skmacy#define SMU72_NUM_NON_TES 2 184164159Skmacy#define SMU72_DTE_FAN_SCALAR_MIN 0x100 185164159Skmacy#define SMU72_DTE_FAN_SCALAR_MAX 0x166 186164159Skmacy#define SMU72_DTE_FAN_TEMP_MAX 93 187164159Skmacy#define SMU72_DTE_FAN_TEMP_MIN 83 188164159Skmacy 189164159Skmacy#if defined SMU__FUSION_ONLY 190164159Skmacy#define SMU7_DTE_ITERATIONS 5 191164159Skmacy#define SMU7_DTE_SOURCES 5 192164159Skmacy#define SMU7_DTE_SINKS 3 193154484Sjhb#define SMU7_NUM_CPU_TES 2 194154484Sjhb#define SMU7_NUM_GPU_TES 1 195154484Sjhb#define SMU7_NUM_NON_TES 2 196154484Sjhb#endif 197154484Sjhb 198154484Sjhbstruct SMU7_HystController_Data { 199154484Sjhb uint8_t waterfall_up; 200154484Sjhb uint8_t waterfall_down; 201154484Sjhb uint8_t waterfall_limit; 202154484Sjhb uint8_t spare; 203154484Sjhb uint16_t release_cnt; 204154484Sjhb uint16_t release_limit; 205154484Sjhb}; 206154484Sjhb 207154484Sjhbtypedef struct SMU7_HystController_Data SMU7_HystController_Data; 208154484Sjhb 209154484Sjhbstruct SMU72_PIDController { 210154484Sjhb uint32_t Ki; 211154484Sjhb int32_t LFWindupUpperLim; 212154484Sjhb int32_t LFWindupLowerLim; 213154484Sjhb uint32_t StatePrecision; 214154484Sjhb uint32_t LfPrecision; 215154484Sjhb uint32_t LfOffset; 216154484Sjhb uint32_t MaxState; 217154484Sjhb uint32_t MaxLfFraction; 218154484Sjhb uint32_t StateShift; 219154484Sjhb}; 220154484Sjhb 221154484Sjhbtypedef struct SMU72_PIDController SMU72_PIDController; 222154484Sjhb 223154484Sjhbstruct SMU7_LocalDpmScoreboard { 224154484Sjhb uint32_t PercentageBusy; 225154484Sjhb 226154484Sjhb int32_t PIDError; 227154484Sjhb int32_t PIDIntegral; 228154484Sjhb int32_t PIDOutput; 229154484Sjhb 230154484Sjhb uint32_t SigmaDeltaAccum; 231154484Sjhb uint32_t SigmaDeltaOutput; 232154484Sjhb uint32_t SigmaDeltaLevel; 233154484Sjhb 234154484Sjhb uint32_t UtilizationSetpoint; 235154484Sjhb 236154484Sjhb uint8_t TdpClampMode; 237154484Sjhb uint8_t TdcClampMode; 238154484Sjhb uint8_t ThermClampMode; 239154484Sjhb uint8_t VoltageBusy; 240154484Sjhb 241154484Sjhb int8_t CurrLevel; 242154484Sjhb int8_t TargLevel; 243154484Sjhb uint8_t LevelChangeInProgress; 244154484Sjhb uint8_t UpHyst; 245154484Sjhb 246154484Sjhb uint8_t DownHyst; 247154484Sjhb uint8_t VoltageDownHyst; 248154484Sjhb uint8_t DpmEnable; 249154484Sjhb uint8_t DpmRunning; 250164159Skmacy 251164159Skmacy uint8_t DpmForce; 252164159Skmacy uint8_t DpmForceLevel; 253164159Skmacy uint8_t DisplayWatermark; 254164159Skmacy uint8_t McArbIndex; 255164159Skmacy 256164159Skmacy uint32_t MinimumPerfSclk; 257164159Skmacy 258164159Skmacy uint8_t AcpiReq; 259164159Skmacy uint8_t AcpiAck; 260164159Skmacy uint8_t GfxClkSlow; 261164159Skmacy uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */ 262164159Skmacy 263164159Skmacy uint8_t FpsFilterWeight; 264164159Skmacy uint8_t EnabledLevelsChange; 265164159Skmacy uint8_t DteClampMode; 266164159Skmacy uint8_t FpsClampMode; 267164159Skmacy 268164159Skmacy uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS]; 269164159Skmacy uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS]; 270164159Skmacy 271164159Skmacy void (*TargetStateCalculator)(uint8_t); 272164159Skmacy void (*SavedTargetStateCalculator)(uint8_t); 273164159Skmacy 274164159Skmacy uint16_t AutoDpmInterval; 275164159Skmacy uint16_t AutoDpmRange; 276164159Skmacy 277164159Skmacy uint8_t FpsEnabled; 278164159Skmacy uint8_t MaxPerfLevel; 279164159Skmacy uint8_t AllowLowClkInterruptToHost; 280164159Skmacy uint8_t FpsRunning; 281164159Skmacy 282164159Skmacy uint32_t MaxAllowedFrequency; 283164159Skmacy 284164159Skmacy uint32_t FilteredSclkFrequency; 285164159Skmacy uint32_t LastSclkFrequency; 286164159Skmacy uint32_t FilteredSclkFrequencyCnt; 287164159Skmacy}; 288164159Skmacy 289164159Skmacytypedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 290164159Skmacy 291164159Skmacy#define SMU7_MAX_VOLTAGE_CLIENTS 12 292164159Skmacy 293164159Skmacytypedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); 294164159Skmacy 295164159Skmacystruct SMU_VoltageLevel { 296164159Skmacy uint8_t Vddc; 297164159Skmacy uint8_t Vddci; 298164159Skmacy uint8_t VddGfx; 299164159Skmacy uint8_t Phases; 300164159Skmacy}; 301164159Skmacy 302164159Skmacytypedef struct SMU_VoltageLevel SMU_VoltageLevel; 303164159Skmacy 304164159Skmacystruct SMU7_VoltageScoreboard { 305164159Skmacy SMU_VoltageLevel CurrentVoltage; 306164159Skmacy SMU_VoltageLevel TargetVoltage; 307164159Skmacy uint16_t MaxVid; 308164159Skmacy uint8_t HighestVidOffset; 309164159Skmacy uint8_t CurrentVidOffset; 310164159Skmacy 311164159Skmacy uint8_t ControllerBusy; 312164159Skmacy uint8_t CurrentVid; 313164159Skmacy uint8_t CurrentVddciVid; 314164159Skmacy uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */ 315164159Skmacy 316164159Skmacy SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 317164159Skmacy uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 318164159Skmacy 319164159Skmacy uint8_t TargetIndex; 320164159Skmacy uint8_t Delay; 321164159Skmacy uint8_t ControllerEnable; 322164159Skmacy uint8_t ControllerRunning; 323164159Skmacy uint16_t CurrentStdVoltageHiSidd; 324164159Skmacy uint16_t CurrentStdVoltageLoSidd; 325164159Skmacy uint8_t OverrideVoltage; 326164159Skmacy uint8_t VddcUseUlvOffset; 327164159Skmacy uint8_t VddGfxUseUlvOffset; 328164159Skmacy uint8_t padding; 329164159Skmacy 330164159Skmacy VoltageChangeHandler_t ChangeVddc; 331164159Skmacy VoltageChangeHandler_t ChangeVddGfx; 332164159Skmacy VoltageChangeHandler_t ChangeVddci; 333164159Skmacy VoltageChangeHandler_t ChangePhase; 334164159Skmacy VoltageChangeHandler_t ChangeMvdd; 335164159Skmacy 336164159Skmacy VoltageChangeHandler_t functionLinks[6]; 337164159Skmacy 338164159Skmacy uint8_t *VddcFollower1; 339164159Skmacy uint8_t *VddcFollower2; 340164159Skmacy int16_t Driver_OD_RequestedVidOffset1; 341164159Skmacy int16_t Driver_OD_RequestedVidOffset2; 342164159Skmacy 343164159Skmacy}; 344164159Skmacy 345164159Skmacytypedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 346164159Skmacy 347164159Skmacy#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 348164159Skmacy 349164159Skmacystruct SMU7_PCIeLinkSpeedScoreboard { 350164159Skmacy uint8_t DpmEnable; 351164159Skmacy uint8_t DpmRunning; 352164159Skmacy uint8_t DpmForce; 353164159Skmacy uint8_t DpmForceLevel; 354164159Skmacy 355164159Skmacy uint8_t CurrentLinkSpeed; 356164159Skmacy uint8_t EnabledLevelsChange; 357164159Skmacy uint16_t AutoDpmInterval; 358164159Skmacy 359164159Skmacy uint16_t AutoDpmRange; 360164159Skmacy uint16_t AutoDpmCount; 361164159Skmacy 362164159Skmacy uint8_t DpmMode; 363164159Skmacy uint8_t AcpiReq; 364164159Skmacy uint8_t AcpiAck; 365164159Skmacy uint8_t CurrentLinkLevel; 366164159Skmacy 367164159Skmacy}; 368164159Skmacy 369164159Skmacytypedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 370164159Skmacy 371164159Skmacy/* -------------------------------------------------------- CAC table ------------------------------------------------------ */ 372164159Skmacy#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 373164159Skmacy#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 374164159Skmacy#define SMU7_SCALE_I 7 375164159Skmacy#define SMU7_SCALE_R 12 376164159Skmacy 377164159Skmacystruct SMU7_PowerScoreboard { 378164159Skmacy PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT]; 379164159Skmacy PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT]; 380164159Skmacy 381164159Skmacy uint32_t TotalGpuPower; 382164159Skmacy uint32_t TdcCurrent; 383164159Skmacy 384164159Skmacy uint16_t VddciTotalPower; 385164159Skmacy uint16_t sparesasfsdfd; 386164159Skmacy uint16_t Vddr1Power; 387164159Skmacy uint16_t RocPower; 388164159Skmacy 389164159Skmacy uint16_t CalcMeasPowerBlend; 390164159Skmacy uint8_t SidOptionPower; 391164159Skmacy uint8_t SidOptionCurrent; 392164159Skmacy 393164159Skmacy uint32_t WinTime; 394164159Skmacy 395164159Skmacy uint16_t Telemetry_1_slope; 396164159Skmacy uint16_t Telemetry_2_slope; 397164159Skmacy int32_t Telemetry_1_offset; 398164159Skmacy int32_t Telemetry_2_offset; 399164159Skmacy 400164159Skmacy uint32_t VddcCurrentTelemetry; 401164159Skmacy uint32_t VddGfxCurrentTelemetry; 402164159Skmacy uint32_t VddcPowerTelemetry; 403164159Skmacy uint32_t VddGfxPowerTelemetry; 404164159Skmacy uint32_t VddciPowerTelemetry; 405164159Skmacy 406164159Skmacy uint32_t VddcPower; 407 uint32_t VddGfxPower; 408 uint32_t VddciPower; 409 410 uint32_t TelemetryCurrent[2]; 411 uint32_t TelemetryVoltage[2]; 412 uint32_t TelemetryPower[2]; 413}; 414 415typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 416 417struct SMU7_ThermalScoreboard { 418 int16_t GpuLimit; 419 int16_t GpuHyst; 420 uint16_t CurrGnbTemp; 421 uint16_t FilteredGnbTemp; 422 423 uint8_t ControllerEnable; 424 uint8_t ControllerRunning; 425 uint8_t AutoTmonCalInterval; 426 uint8_t AutoTmonCalEnable; 427 428 uint8_t ThermalDpmEnabled; 429 uint8_t SclkEnabledMask; 430 uint8_t spare[2]; 431 int32_t temperature_gradient; 432 433 SMU7_HystController_Data HystControllerData; 434 int32_t WeightedSensorTemperature; 435 uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS]; 436 uint32_t Alpha; 437}; 438 439typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; 440 441/* For FeatureEnables: */ 442#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 443#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 444#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 445#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 446#define SMU7_UVD_DPM_CONFIG_MASK 0x10 447#define SMU7_VCE_DPM_CONFIG_MASK 0x20 448#define SMU7_ACP_DPM_CONFIG_MASK 0x40 449#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 450#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 451 452#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 453#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 454#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 455#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 456#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 457#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 458 459/* All 'soft registers' should be uint32_t. */ 460struct SMU72_SoftRegisters { 461 uint32_t RefClockFrequency; 462 uint32_t PmTimerPeriod; 463 uint32_t FeatureEnables; 464 465 uint32_t PreVBlankGap; 466 uint32_t VBlankTimeout; 467 uint32_t TrainTimeGap; 468 469 uint32_t MvddSwitchTime; 470 uint32_t LongestAcpiTrainTime; 471 uint32_t AcpiDelay; 472 uint32_t G5TrainTime; 473 uint32_t DelayMpllPwron; 474 uint32_t VoltageChangeTimeout; 475 476 uint32_t HandshakeDisables; 477 478 uint8_t DisplayPhy1Config; 479 uint8_t DisplayPhy2Config; 480 uint8_t DisplayPhy3Config; 481 uint8_t DisplayPhy4Config; 482 483 uint8_t DisplayPhy5Config; 484 uint8_t DisplayPhy6Config; 485 uint8_t DisplayPhy7Config; 486 uint8_t DisplayPhy8Config; 487 488 uint32_t AverageGraphicsActivity; 489 uint32_t AverageMemoryActivity; 490 uint32_t AverageGioActivity; 491 492 uint8_t SClkDpmEnabledLevels; 493 uint8_t MClkDpmEnabledLevels; 494 uint8_t LClkDpmEnabledLevels; 495 uint8_t PCIeDpmEnabledLevels; 496 497 uint8_t UVDDpmEnabledLevels; 498 uint8_t SAMUDpmEnabledLevels; 499 uint8_t ACPDpmEnabledLevels; 500 uint8_t VCEDpmEnabledLevels; 501 502 uint32_t DRAM_LOG_ADDR_H; 503 uint32_t DRAM_LOG_ADDR_L; 504 uint32_t DRAM_LOG_PHY_ADDR_H; 505 uint32_t DRAM_LOG_PHY_ADDR_L; 506 uint32_t DRAM_LOG_BUFF_SIZE; 507 uint32_t UlvEnterCount; 508 uint32_t UlvTime; 509 uint32_t UcodeLoadStatus; 510 uint32_t Reserved[2]; 511 512}; 513 514typedef struct SMU72_SoftRegisters SMU72_SoftRegisters; 515 516struct SMU72_Firmware_Header { 517 uint32_t Digest[5]; 518 uint32_t Version; 519 uint32_t HeaderSize; 520 uint32_t Flags; 521 uint32_t EntryPoint; 522 uint32_t CodeSize; 523 uint32_t ImageSize; 524 525 uint32_t Rtos; 526 uint32_t SoftRegisters; 527 uint32_t DpmTable; 528 uint32_t FanTable; 529 uint32_t CacConfigTable; 530 uint32_t CacStatusTable; 531 uint32_t mcRegisterTable; 532 uint32_t mcArbDramTimingTable; 533 uint32_t PmFuseTable; 534 uint32_t Globals; 535 uint32_t ClockStretcherTable; 536 uint32_t Reserved[41]; 537 uint32_t Signature; 538}; 539 540typedef struct SMU72_Firmware_Header SMU72_Firmware_Header; 541 542#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000 543 544enum DisplayConfig { 545 PowerDown = 1, 546 DP54x4, 547 DP54x2, 548 DP54x1, 549 DP27x4, 550 DP27x2, 551 DP27x1, 552 HDMI297, 553 HDMI162, 554 LVDS, 555 DP324x4, 556 DP324x2, 557 DP324x1 558}; 559 560#define MC_BLOCK_COUNT 1 561#define CPL_BLOCK_COUNT 5 562#define SE_BLOCK_COUNT 15 563#define GC_BLOCK_COUNT 24 564 565struct SMU7_Local_Cac { 566 uint8_t BlockId; 567 uint8_t SignalId; 568 uint8_t Threshold; 569 uint8_t Padding; 570}; 571 572typedef struct SMU7_Local_Cac SMU7_Local_Cac; 573 574struct SMU7_Local_Cac_Table { 575 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 576 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 577 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; 578 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; 579}; 580 581typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 582 583#if !defined(SMC_MICROCODE) 584#pragma pack(pop) 585#endif 586 587/* Description of Clock Gating bitmask for Tonga: */ 588/* System Clock Gating */ 589#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */ 590#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */ 591#define CG_SYS_BIF_MGLS_SHIFT 0 592#define CG_SYS_ROM_SHIFT 1 593#define CG_SYS_MC_MGCG_SHIFT 2 594#define CG_SYS_MC_MGLS_SHIFT 3 595#define CG_SYS_SDMA_MGCG_SHIFT 4 596#define CG_SYS_SDMA_MGLS_SHIFT 5 597#define CG_SYS_DRM_MGCG_SHIFT 6 598#define CG_SYS_HDP_MGCG_SHIFT 7 599#define CG_SYS_HDP_MGLS_SHIFT 8 600#define CG_SYS_DRM_MGLS_SHIFT 9 601 602#define CG_SYS_BIF_MGLS_MASK 0x1 603#define CG_SYS_ROM_MASK 0x2 604#define CG_SYS_MC_MGCG_MASK 0x4 605#define CG_SYS_MC_MGLS_MASK 0x8 606#define CG_SYS_SDMA_MGCG_MASK 0x10 607#define CG_SYS_SDMA_MGLS_MASK 0x20 608#define CG_SYS_DRM_MGCG_MASK 0x40 609#define CG_SYS_HDP_MGCG_MASK 0x80 610#define CG_SYS_HDP_MGLS_MASK 0x100 611#define CG_SYS_DRM_MGLS_MASK 0x200 612 613/* Graphics Clock Gating */ 614#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */ 615#define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */ 616#define CG_GFX_CGCG_SHIFT 16 617#define CG_GFX_CGLS_SHIFT 17 618#define CG_CPF_MGCG_SHIFT 18 619#define CG_RLC_MGCG_SHIFT 19 620#define CG_GFX_OTHERS_MGCG_SHIFT 20 621 622#define CG_GFX_CGCG_MASK 0x00010000 623#define CG_GFX_CGLS_MASK 0x00020000 624#define CG_CPF_MGCG_MASK 0x00040000 625#define CG_RLC_MGCG_MASK 0x00080000 626#define CG_GFX_OTHERS_MGCG_MASK 0x00100000 627 628/* Voltage Regulator Configuration */ 629/* VR Config info is contained in dpmTable.VRConfig */ 630 631#define VRCONF_VDDC_MASK 0x000000FF 632#define VRCONF_VDDC_SHIFT 0 633#define VRCONF_VDDGFX_MASK 0x0000FF00 634#define VRCONF_VDDGFX_SHIFT 8 635#define VRCONF_VDDCI_MASK 0x00FF0000 636#define VRCONF_VDDCI_SHIFT 16 637#define VRCONF_MVDD_MASK 0xFF000000 638#define VRCONF_MVDD_SHIFT 24 639 640#define VR_MERGED_WITH_VDDC 0 641#define VR_SVI2_PLANE_1 1 642#define VR_SVI2_PLANE_2 2 643#define VR_SMIO_PATTERN_1 3 644#define VR_SMIO_PATTERN_2 4 645#define VR_STATIC_VOLTAGE 5 646 647/* Clock Stretcher Configuration */ 648 649#define CLOCK_STRETCHER_MAX_ENTRIES 0x4 650#define CKS_LOOKUPTable_MAX_ENTRIES 0x4 651 652/* The 'settings' field is subdivided in the following way: */ 653#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 654#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 655#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E 656#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 657#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 658#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 659 660struct SMU_ClockStretcherDataTableEntry { 661 uint8_t minVID; 662 uint8_t maxVID; 663 664 uint16_t setting; 665}; 666typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 667 668struct SMU_ClockStretcherDataTable { 669 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; 670}; 671typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; 672 673struct SMU_CKS_LOOKUPTableEntry { 674 uint16_t minFreq; 675 uint16_t maxFreq; 676 677 uint8_t setting; 678 uint8_t padding[3]; 679}; 680typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; 681 682struct SMU_CKS_LOOKUPTable { 683 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; 684}; 685typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; 686 687#endif 688 689 690