1/*	$NetBSD: kv_dpm.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $	*/
2
3/*
4 * Copyright 2013 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25#ifndef __KV_DPM_H__
26#define __KV_DPM_H__
27
28#define SMU__NUM_SCLK_DPM_STATE  8
29#define SMU__NUM_MCLK_DPM_LEVELS 4
30#define SMU__NUM_LCLK_DPM_LEVELS 8
31#define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
32#include "smu7_fusion.h"
33#include "trinity_dpm.h"
34#include "ppsmc.h"
35
36#define KV_NUM_NBPSTATES   4
37
38enum kv_pt_config_reg_type {
39	KV_CONFIGREG_MMR = 0,
40	KV_CONFIGREG_SMC_IND,
41	KV_CONFIGREG_DIDT_IND,
42	KV_CONFIGREG_CACHE,
43	KV_CONFIGREG_MAX
44};
45
46struct kv_pt_config_reg {
47	u32 offset;
48	u32 mask;
49	u32 shift;
50	u32 value;
51	enum kv_pt_config_reg_type type;
52};
53
54struct kv_lcac_config_values {
55	u32 block_id;
56	u32 signal_id;
57	u32 t;
58};
59
60struct kv_lcac_config_reg {
61	u32 cntl;
62	u32 block_mask;
63	u32 block_shift;
64	u32 signal_mask;
65	u32 signal_shift;
66	u32 t_mask;
67	u32 t_shift;
68	u32 enable_mask;
69	u32 enable_shift;
70};
71
72struct kv_pl {
73	u32 sclk;
74	u8 vddc_index;
75	u8 ds_divider_index;
76	u8 ss_divider_index;
77	u8 allow_gnb_slow;
78	u8 force_nbp_state;
79	u8 display_wm;
80	u8 vce_wm;
81};
82
83struct kv_ps {
84	struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
85	u32 num_levels;
86	bool need_dfs_bypass;
87	u8 dpm0_pg_nb_ps_lo;
88	u8 dpm0_pg_nb_ps_hi;
89	u8 dpmx_nb_ps_lo;
90	u8 dpmx_nb_ps_hi;
91};
92
93struct kv_sys_info {
94	u32 bootup_uma_clk;
95	u32 bootup_sclk;
96	u32 dentist_vco_freq;
97	u32 nb_dpm_enable;
98	u32 nbp_memory_clock[KV_NUM_NBPSTATES];
99	u32 nbp_n_clock[KV_NUM_NBPSTATES];
100	u16 bootup_nb_voltage_index;
101	u8 htc_tmp_lmt;
102	u8 htc_hyst_lmt;
103	struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
104	struct sumo_vid_mapping_table vid_mapping_table;
105	u32 uma_channel_number;
106};
107
108struct kv_power_info {
109	u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
110	u32 voltage_drop_t;
111	struct kv_sys_info sys_info;
112	struct kv_pl boot_pl;
113	bool enable_nb_ps_policy;
114	bool disable_nb_ps3_in_battery;
115	bool video_start;
116	bool battery_state;
117	u32 lowest_valid;
118	u32 highest_valid;
119	u16 high_voltage_t;
120	bool cac_enabled;
121	bool bapm_enable;
122	/* smc offsets */
123	u32 sram_end;
124	u32 dpm_table_start;
125	u32 soft_regs_start;
126	/* dpm SMU tables */
127	u8 graphics_dpm_level_count;
128	u8 uvd_level_count;
129	u8 vce_level_count;
130	u8 acp_level_count;
131	u8 samu_level_count;
132	u16 fps_high_t;
133	SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
134	SMU7_Fusion_ACPILevel acpi_level;
135	SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
136	SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
137	SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
138	SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
139	u8 uvd_boot_level;
140	u8 vce_boot_level;
141	u8 acp_boot_level;
142	u8 samu_boot_level;
143	u8 uvd_interval;
144	u8 vce_interval;
145	u8 acp_interval;
146	u8 samu_interval;
147	u8 graphics_boot_level;
148	u8 graphics_interval;
149	u8 graphics_therm_throttle_enable;
150	u8 graphics_voltage_change_enable;
151	u8 graphics_clk_slow_enable;
152	u8 graphics_clk_slow_divider;
153	u8 fps_low_t;
154	u32 low_sclk_interrupt_t;
155	bool uvd_power_gated;
156	bool vce_power_gated;
157	bool acp_power_gated;
158	bool samu_power_gated;
159	bool nb_dpm_enabled;
160	/* flags */
161	bool enable_didt;
162	bool enable_dpm;
163	bool enable_auto_thermal_throttling;
164	bool enable_nb_dpm;
165	/* caps */
166	bool caps_cac;
167	bool caps_power_containment;
168	bool caps_sq_ramping;
169	bool caps_db_ramping;
170	bool caps_td_ramping;
171	bool caps_tcp_ramping;
172	bool caps_sclk_throttle_low_notification;
173	bool caps_fps;
174	bool caps_uvd_dpm;
175	bool caps_uvd_pg;
176	bool caps_vce_pg;
177	bool caps_samu_pg;
178	bool caps_acp_pg;
179	bool caps_stable_p_state;
180	bool caps_enable_dfs_bypass;
181	bool caps_sclk_ds;
182	struct radeon_ps current_rps;
183	struct kv_ps current_ps;
184	struct radeon_ps requested_rps;
185	struct kv_ps requested_ps;
186};
187
188
189/* kv_smc.c */
190int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);
191int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
192int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
193				      PPSMC_Msg msg, u32 parameter);
194int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
195			   u32 *value, u32 limit);
196int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
197int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);
198int kv_copy_bytes_to_smc(struct radeon_device *rdev,
199			 u32 smc_start_address,
200			 const u8 *src, u32 byte_count, u32 limit);
201
202#endif
203