1/*	$NetBSD: smu74_discrete.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
2
3/*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef SMU74_DISCRETE_H
27#define SMU74_DISCRETE_H
28
29#include "smu74.h"
30
31#pragma pack(push, 1)
32
33
34#define NUM_SCLK_RANGE 8
35
36#define VCO_3_6 1
37#define VCO_2_4 3
38
39#define POSTDIV_DIV_BY_1  0
40#define POSTDIV_DIV_BY_2  1
41#define POSTDIV_DIV_BY_4  2
42#define POSTDIV_DIV_BY_8  3
43#define POSTDIV_DIV_BY_16 4
44
45struct sclkFcwRange_t {
46	uint8_t  vco_setting;
47	uint8_t  postdiv;
48	uint16_t fcw_pcc;
49
50	uint16_t fcw_trans_upper;
51	uint16_t fcw_trans_lower;
52};
53typedef struct sclkFcwRange_t sclkFcwRange_t;
54
55struct SMIO_Pattern {
56	uint16_t Voltage;
57	uint8_t  Smio;
58	uint8_t  padding;
59};
60
61typedef struct SMIO_Pattern SMIO_Pattern;
62
63struct SMIO_Table {
64	SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
65};
66
67typedef struct SMIO_Table SMIO_Table;
68
69struct SMU_SclkSetting {
70	uint32_t    SclkFrequency;
71	uint16_t    Fcw_int;
72	uint16_t    Fcw_frac;
73	uint16_t    Pcc_fcw_int;
74	uint8_t     PllRange;
75	uint8_t     SSc_En;
76	uint16_t    Sclk_slew_rate;
77	uint16_t    Pcc_up_slew_rate;
78	uint16_t    Pcc_down_slew_rate;
79	uint16_t    Fcw1_int;
80	uint16_t    Fcw1_frac;
81	uint16_t    Sclk_ss_slew_rate;
82};
83typedef struct SMU_SclkSetting SMU_SclkSetting;
84
85struct SMU74_Discrete_GraphicsLevel {
86	SMU_VoltageLevel MinVoltage;
87	uint8_t     pcieDpmLevel;
88	uint8_t     DeepSleepDivId;
89	uint16_t    ActivityLevel;
90	uint32_t    CgSpllFuncCntl3;
91	uint32_t    CgSpllFuncCntl4;
92	uint32_t    CcPwrDynRm;
93	uint32_t    CcPwrDynRm1;
94	uint8_t     SclkDid;
95	uint8_t     padding;
96	uint8_t     EnabledForActivity;
97	uint8_t     EnabledForThrottle;
98	uint8_t     UpHyst;
99	uint8_t     DownHyst;
100	uint8_t     VoltageDownHyst;
101	uint8_t     PowerThrottle;
102	SMU_SclkSetting SclkSetting;
103};
104
105typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
106
107struct SMU74_Discrete_ACPILevel {
108	uint32_t    Flags;
109	SMU_VoltageLevel MinVoltage;
110	uint32_t    SclkFrequency;
111	uint8_t     SclkDid;
112	uint8_t     DisplayWatermark;
113	uint8_t     DeepSleepDivId;
114	uint8_t     padding;
115	uint32_t    CcPwrDynRm;
116	uint32_t    CcPwrDynRm1;
117
118	SMU_SclkSetting SclkSetting;
119};
120
121typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
122
123struct SMU74_Discrete_Ulv {
124	uint32_t    CcPwrDynRm;
125	uint32_t    CcPwrDynRm1;
126	uint16_t    VddcOffset;
127	uint8_t     VddcOffsetVid;
128	uint8_t     VddcPhase;
129	uint16_t    BifSclkDfs;
130	uint16_t    Reserved;
131};
132
133typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
134
135struct SMU74_Discrete_MemoryLevel {
136	SMU_VoltageLevel MinVoltage;
137	uint32_t    MinMvdd;
138
139	uint32_t    MclkFrequency;
140
141	uint8_t     StutterEnable;
142	uint8_t     EnabledForThrottle;
143	uint8_t     EnabledForActivity;
144	uint8_t     padding_0;
145
146	uint8_t     UpHyst;
147	uint8_t     DownHyst;
148	uint8_t     VoltageDownHyst;
149	uint8_t     padding_1;
150
151	uint16_t    ActivityLevel;
152	uint8_t     DisplayWatermark;
153	uint8_t     Reserved;
154};
155
156typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
157
158struct SMU74_Discrete_LinkLevel {
159	uint8_t     PcieGenSpeed;
160	uint8_t     PcieLaneCount;
161	uint8_t     EnabledForActivity;
162	uint8_t     SPC;
163	uint32_t    DownThreshold;
164	uint32_t    UpThreshold;
165	uint16_t    BifSclkDfs;
166	uint16_t    Reserved;
167};
168
169typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
170
171struct SMU74_Discrete_MCArbDramTimingTableEntry {
172	uint32_t McArbDramTiming;
173	uint32_t McArbDramTiming2;
174	uint8_t  McArbBurstTime;
175	uint8_t  padding[3];
176};
177
178typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
179
180struct SMU74_Discrete_MCArbDramTimingTable {
181	SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
182};
183
184typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
185
186struct SMU74_Discrete_UvdLevel {
187	uint32_t VclkFrequency;
188	uint32_t DclkFrequency;
189	SMU_VoltageLevel MinVoltage;
190	uint8_t  VclkDivider;
191	uint8_t  DclkDivider;
192	uint8_t  padding[2];
193};
194
195typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
196
197struct SMU74_Discrete_ExtClkLevel {
198	uint32_t Frequency;
199	SMU_VoltageLevel MinVoltage;
200	uint8_t  Divider;
201	uint8_t  padding[3];
202};
203
204typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
205
206struct SMU74_Discrete_StateInfo {
207	uint32_t SclkFrequency;
208	uint32_t MclkFrequency;
209	uint32_t VclkFrequency;
210	uint32_t DclkFrequency;
211	uint32_t SamclkFrequency;
212	uint32_t AclkFrequency;
213	uint32_t EclkFrequency;
214	uint16_t MvddVoltage;
215	uint16_t padding16;
216	uint8_t  DisplayWatermark;
217	uint8_t  McArbIndex;
218	uint8_t  McRegIndex;
219	uint8_t  SeqIndex;
220	uint8_t  SclkDid;
221	int8_t   SclkIndex;
222	int8_t   MclkIndex;
223	uint8_t  PCIeGen;
224};
225
226typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
227
228struct SMU_QuadraticCoeffs {
229	int32_t m1;
230	uint32_t b;
231
232	int16_t m2;
233	uint8_t m1_shift;
234	uint8_t m2_shift;
235};
236typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
237
238struct SMU74_Discrete_DpmTable {
239
240	SMU74_PIDController                  GraphicsPIDController;
241	SMU74_PIDController                  MemoryPIDController;
242	SMU74_PIDController                  LinkPIDController;
243
244	uint32_t                            SystemFlags;
245
246	uint32_t                            VRConfig;
247	uint32_t                            SmioMask1;
248	uint32_t                            SmioMask2;
249	SMIO_Table                          SmioTable1;
250	SMIO_Table                          SmioTable2;
251
252	uint32_t                            MvddLevelCount;
253
254
255	uint8_t                             BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
256	uint8_t                             BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
257	uint8_t                             BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
258
259	uint8_t                             GraphicsDpmLevelCount;
260	uint8_t                             MemoryDpmLevelCount;
261	uint8_t                             LinkLevelCount;
262	uint8_t                             MasterDeepSleepControl;
263
264	uint8_t                             UvdLevelCount;
265	uint8_t                             VceLevelCount;
266	uint8_t                             AcpLevelCount;
267	uint8_t                             SamuLevelCount;
268
269	uint8_t                             ThermOutGpio;
270	uint8_t                             ThermOutPolarity;
271	uint8_t                             ThermOutMode;
272	uint8_t                             BootPhases;
273
274	uint8_t                             VRHotLevel;
275	uint8_t                             LdoRefSel;
276	uint8_t                             Reserved1[2];
277	uint16_t                            FanStartTemperature;
278	uint16_t                            FanStopTemperature;
279	uint16_t                            MaxVoltage;
280	uint16_t                            Reserved2;
281	uint32_t                            Reserved[1];
282
283	SMU74_Discrete_GraphicsLevel        GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
284	SMU74_Discrete_MemoryLevel          MemoryACPILevel;
285	SMU74_Discrete_MemoryLevel          MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
286	SMU74_Discrete_LinkLevel            LinkLevel[SMU74_MAX_LEVELS_LINK];
287	SMU74_Discrete_ACPILevel            ACPILevel;
288	SMU74_Discrete_UvdLevel             UvdLevel[SMU74_MAX_LEVELS_UVD];
289	SMU74_Discrete_ExtClkLevel          VceLevel[SMU74_MAX_LEVELS_VCE];
290	SMU74_Discrete_ExtClkLevel          AcpLevel[SMU74_MAX_LEVELS_ACP];
291	SMU74_Discrete_ExtClkLevel          SamuLevel[SMU74_MAX_LEVELS_SAMU];
292	SMU74_Discrete_Ulv                  Ulv;
293
294	uint8_t                             DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
295
296	uint32_t                            SclkStepSize;
297	uint32_t                            Smio[SMU74_MAX_ENTRIES_SMIO];
298
299	uint8_t                             UvdBootLevel;
300	uint8_t                             VceBootLevel;
301	uint8_t                             AcpBootLevel;
302	uint8_t                             SamuBootLevel;
303
304	uint8_t                             GraphicsBootLevel;
305	uint8_t                             GraphicsVoltageChangeEnable;
306	uint8_t                             GraphicsThermThrottleEnable;
307	uint8_t                             GraphicsInterval;
308
309	uint8_t                             VoltageInterval;
310	uint8_t                             ThermalInterval;
311	uint16_t                            TemperatureLimitHigh;
312
313	uint16_t                            TemperatureLimitLow;
314	uint8_t                             MemoryBootLevel;
315	uint8_t                             MemoryVoltageChangeEnable;
316
317	uint16_t                            BootMVdd;
318	uint8_t                             MemoryInterval;
319	uint8_t                             MemoryThermThrottleEnable;
320
321	uint16_t                            VoltageResponseTime;
322	uint16_t                            PhaseResponseTime;
323
324	uint8_t                             PCIeBootLinkLevel;
325	uint8_t                             PCIeGenInterval;
326	uint8_t                             DTEInterval;
327	uint8_t                             DTEMode;
328
329	uint8_t                             SVI2Enable;
330	uint8_t                             VRHotGpio;
331	uint8_t                             AcDcGpio;
332	uint8_t                             ThermGpio;
333
334	uint16_t                            PPM_PkgPwrLimit;
335	uint16_t                            PPM_TemperatureLimit;
336
337	uint16_t                            DefaultTdp;
338	uint16_t                            TargetTdp;
339
340	uint16_t                            FpsHighThreshold;
341	uint16_t                            FpsLowThreshold;
342
343	uint16_t                            BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
344	uint16_t                            BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
345
346	uint16_t                            TemperatureLimitEdge;
347	uint16_t                            TemperatureLimitHotspot;
348
349	uint16_t                            BootVddc;
350	uint16_t                            BootVddci;
351
352	uint16_t                            FanGainEdge;
353	uint16_t                            FanGainHotspot;
354
355	uint32_t                            LowSclkInterruptThreshold;
356	uint32_t                            VddGfxReChkWait;
357
358	uint8_t                             ClockStretcherAmount;
359	uint8_t                             Sclk_CKS_masterEn0_7;
360	uint8_t                             Sclk_CKS_masterEn8_15;
361	uint8_t                             DPMFreezeAndForced;
362
363	uint8_t                             Sclk_voltageOffset[8];
364
365	SMU_ClockStretcherDataTable         ClockStretcherDataTable;
366	SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
367
368	uint32_t                            CurrSclkPllRange;
369	sclkFcwRange_t                      SclkFcwRangeTable[NUM_SCLK_RANGE];
370	GB_VDROOP_TABLE_t                   BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
371	SMU_QuadraticCoeffs                 AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
372};
373
374typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
375
376
377struct SMU74_Discrete_FanTable {
378	uint16_t FdoMode;
379	int16_t  TempMin;
380	int16_t  TempMed;
381	int16_t  TempMax;
382	int16_t  Slope1;
383	int16_t  Slope2;
384	int16_t  FdoMin;
385	int16_t  HystUp;
386	int16_t  HystDown;
387	int16_t  HystSlope;
388	int16_t  TempRespLim;
389	int16_t  TempCurr;
390	int16_t  SlopeCurr;
391	int16_t  PwmCurr;
392	uint32_t RefreshPeriod;
393	int16_t  FdoMax;
394	uint8_t  TempSrc;
395	int8_t   Padding;
396};
397
398typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
399
400#define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
401#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
402
403
404struct SMU7_MclkDpmScoreboard {
405	uint32_t PercentageBusy;
406
407	int32_t  PIDError;
408	int32_t  PIDIntegral;
409	int32_t  PIDOutput;
410
411	uint32_t SigmaDeltaAccum;
412	uint32_t SigmaDeltaOutput;
413	uint32_t SigmaDeltaLevel;
414
415	uint32_t UtilizationSetpoint;
416
417	uint8_t  TdpClampMode;
418	uint8_t  TdcClampMode;
419	uint8_t  ThermClampMode;
420	uint8_t  VoltageBusy;
421
422	int8_t   CurrLevel;
423	int8_t   TargLevel;
424	uint8_t  LevelChangeInProgress;
425	uint8_t  UpHyst;
426
427	uint8_t  DownHyst;
428	uint8_t  VoltageDownHyst;
429	uint8_t  DpmEnable;
430	uint8_t  DpmRunning;
431
432	uint8_t  DpmForce;
433	uint8_t  DpmForceLevel;
434	uint8_t  padding2;
435	uint8_t  McArbIndex;
436
437	uint32_t MinimumPerfMclk;
438
439	uint8_t  AcpiReq;
440	uint8_t  AcpiAck;
441	uint8_t  MclkSwitchInProgress;
442	uint8_t  MclkSwitchCritical;
443
444	uint8_t  IgnoreVBlank;
445	uint8_t  TargetMclkIndex;
446	uint16_t VbiFailureCount;
447	uint8_t  VbiWaitCounter;
448	uint8_t  EnabledLevelsChange;
449
450	uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
451	uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
452
453	void     (*TargetStateCalculator)(uint8_t);
454	void     (*SavedTargetStateCalculator)(uint8_t);
455
456	uint16_t AutoDpmInterval;
457	uint16_t AutoDpmRange;
458
459	uint16_t VbiTimeoutCount;
460	uint16_t MclkSwitchingTime;
461
462	uint8_t  fastSwitch;
463	uint8_t  Save_PIC_VDDGFX_EXIT;
464	uint8_t  Save_PIC_VDDGFX_ENTER;
465	uint8_t  padding;
466};
467
468typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
469
470struct SMU7_UlvScoreboard {
471	uint8_t     EnterUlv;
472	uint8_t     ExitUlv;
473	uint8_t     UlvActive;
474	uint8_t     WaitingForUlv;
475	uint8_t     UlvEnable;
476	uint8_t     UlvRunning;
477	uint8_t     UlvMasterEnable;
478	uint8_t     padding;
479	uint32_t    UlvAbortedCount;
480	uint32_t    UlvTimeStamp;
481};
482
483typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
484
485struct VddgfxSavedRegisters {
486	uint32_t GPU_DBG[3];
487	uint32_t MEC_BaseAddress_Hi;
488	uint32_t MEC_BaseAddress_Lo;
489	uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
490	uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
491	uint32_t CP_INT_CNTL;
492};
493
494typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
495
496struct SMU7_VddGfxScoreboard {
497	uint8_t     VddGfxEnable;
498	uint8_t     VddGfxActive;
499	uint8_t     VPUResetOccured;
500	uint8_t     padding;
501
502	uint32_t    VddGfxEnteredCount;
503	uint32_t    VddGfxAbortedCount;
504
505	uint32_t    VddGfxVid;
506
507	VddgfxSavedRegisters SavedRegisters;
508};
509
510typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
511
512struct SMU7_TdcLimitScoreboard {
513	uint8_t  Enable;
514	uint8_t  Running;
515	uint16_t Alpha;
516	uint32_t FilteredIddc;
517	uint32_t IddcLimit;
518	uint32_t IddcHyst;
519	SMU7_HystController_Data HystControllerData;
520};
521
522typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
523
524struct SMU7_PkgPwrLimitScoreboard {
525	uint8_t  Enable;
526	uint8_t  Running;
527	uint16_t Alpha;
528	uint32_t FilteredPkgPwr;
529	uint32_t Limit;
530	uint32_t Hyst;
531	uint32_t LimitFromDriver;
532	SMU7_HystController_Data HystControllerData;
533};
534
535typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
536
537struct SMU7_BapmScoreboard {
538	uint32_t source_powers[SMU74_DTE_SOURCES];
539	uint32_t source_powers_last[SMU74_DTE_SOURCES];
540	int32_t entity_temperatures[SMU74_NUM_GPU_TES];
541	int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
542	int32_t Limit;
543	int32_t Hyst;
544	int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
545	int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
546	uint16_t ConfigTDPPowerScalar;
547	uint16_t FanSpeedPowerScalar;
548	uint16_t OverDrivePowerScalar;
549	uint16_t OverDriveLimitScalar;
550	uint16_t FinalPowerScalar;
551	uint8_t VariantID;
552	uint8_t spare997;
553
554	SMU7_HystController_Data HystControllerData;
555
556	int32_t temperature_gradient_slope;
557	int32_t temperature_gradient;
558	uint32_t measured_temperature;
559};
560
561
562typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
563
564struct SMU7_AcpiScoreboard {
565	uint32_t SavedInterruptMask[2];
566	uint8_t LastACPIRequest;
567	uint8_t CgBifResp;
568	uint8_t RequestType;
569	uint8_t Padding;
570	SMU74_Discrete_ACPILevel D0Level;
571};
572
573typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
574
575struct SMU74_Discrete_PmFuses {
576	uint8_t BapmVddCVidHiSidd[8];
577	uint8_t BapmVddCVidLoSidd[8];
578	uint8_t VddCVid[8];
579	uint8_t SviLoadLineEn;
580	uint8_t SviLoadLineVddC;
581	uint8_t SviLoadLineTrimVddC;
582	uint8_t SviLoadLineOffsetVddC;
583	uint16_t TDC_VDDC_PkgLimit;
584	uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
585	uint8_t TDC_MAWt;
586	uint8_t TdcWaterfallCtl;
587	uint8_t LPMLTemperatureMin;
588	uint8_t LPMLTemperatureMax;
589	uint8_t Reserved;
590
591	uint8_t LPMLTemperatureScaler[16];
592
593	int16_t FuzzyFan_ErrorSetDelta;
594	int16_t FuzzyFan_ErrorRateSetDelta;
595	int16_t FuzzyFan_PwmSetDelta;
596	uint16_t Reserved6;
597
598	uint8_t GnbLPML[16];
599
600	uint8_t GnbLPMLMaxVid;
601	uint8_t GnbLPMLMinVid;
602	uint8_t Reserved1[2];
603
604	uint16_t BapmVddCBaseLeakageHiSidd;
605	uint16_t BapmVddCBaseLeakageLoSidd;
606
607	uint16_t  VFT_Temp[3];
608	uint16_t  padding;
609
610	SMU_QuadraticCoeffs VFT_ATE[3];
611
612	SMU_QuadraticCoeffs AVFS_GB;
613	SMU_QuadraticCoeffs ATE_ACBTC_GB;
614
615	SMU_QuadraticCoeffs P2V;
616
617	uint32_t PsmCharzFreq;
618
619	uint16_t InversionVoltage;
620	uint16_t PsmCharzTemp;
621
622	uint32_t EnabledAvfsModules;
623};
624
625typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
626
627struct SMU7_Discrete_Log_Header_Table {
628	uint32_t    version;
629	uint32_t    asic_id;
630	uint16_t    flags;
631	uint16_t    entry_size;
632	uint32_t    total_size;
633	uint32_t    num_of_entries;
634	uint8_t     type;
635	uint8_t     mode;
636	uint8_t     filler_0[2];
637	uint32_t    filler_1[2];
638};
639
640typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
641
642struct SMU7_Discrete_Log_Cntl {
643	uint8_t             Enabled;
644	uint8_t             Type;
645	uint8_t             padding[2];
646	uint32_t            BufferSize;
647	uint32_t            SamplesLogged;
648	uint32_t            SampleSize;
649	uint32_t            AddrL;
650	uint32_t            AddrH;
651};
652
653typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
654
655#if defined SMU__DGPU_ONLY
656#define CAC_ACC_NW_NUM_OF_SIGNALS 87
657#endif
658
659
660struct SMU7_Discrete_Cac_Collection_Table {
661	uint32_t temperature;
662	uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
663};
664
665typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
666
667struct SMU7_Discrete_Cac_Verification_Table {
668	uint32_t VddcTotalPower;
669	uint32_t VddcLeakagePower;
670	uint32_t VddcConstantPower;
671	uint32_t VddcGfxDynamicPower;
672	uint32_t VddcUvdDynamicPower;
673	uint32_t VddcVceDynamicPower;
674	uint32_t VddcAcpDynamicPower;
675	uint32_t VddcPcieDynamicPower;
676	uint32_t VddcDceDynamicPower;
677	uint32_t VddcCurrent;
678	uint32_t VddcVoltage;
679	uint32_t VddciTotalPower;
680	uint32_t VddciLeakagePower;
681	uint32_t VddciConstantPower;
682	uint32_t VddciDynamicPower;
683	uint32_t Vddr1TotalPower;
684	uint32_t Vddr1LeakagePower;
685	uint32_t Vddr1ConstantPower;
686	uint32_t Vddr1DynamicPower;
687	uint32_t spare[4];
688	uint32_t temperature;
689};
690
691typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
692
693struct SMU7_Discrete_Pm_Status_Table {
694	int32_t T_meas_max;
695	int32_t T_meas_acc;
696	int32_t T_calc_max;
697	int32_t T_calc_acc;
698	uint32_t P_scalar_acc;
699	uint32_t P_calc_max;
700	uint32_t P_calc_acc;
701
702	uint32_t I_calc_max;
703	uint32_t I_calc_acc;
704	uint32_t I_calc_acc_vddci;
705	uint32_t V_calc_noload_acc;
706	uint32_t V_calc_load_acc;
707	uint32_t V_calc_noload_acc_vddci;
708	uint32_t P_meas_acc;
709	uint32_t V_meas_noload_acc;
710	uint32_t V_meas_load_acc;
711	uint32_t I_meas_acc;
712	uint32_t P_meas_acc_vddci;
713	uint32_t V_meas_noload_acc_vddci;
714	uint32_t V_meas_load_acc_vddci;
715	uint32_t I_meas_acc_vddci;
716
717	uint16_t Sclk_dpm_residency[8];
718	uint16_t Uvd_dpm_residency[8];
719	uint16_t Vce_dpm_residency[8];
720	uint16_t Mclk_dpm_residency[4];
721
722	uint32_t P_vddci_acc;
723	uint32_t P_vddr1_acc;
724	uint32_t P_nte1_acc;
725	uint32_t PkgPwr_max;
726	uint32_t PkgPwr_acc;
727	uint32_t MclkSwitchingTime_max;
728	uint32_t MclkSwitchingTime_acc;
729	uint32_t FanPwm_acc;
730	uint32_t FanRpm_acc;
731
732	uint32_t AccCnt;
733};
734
735typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
736
737#define SMU7_MAX_GFX_CU_COUNT 16
738
739struct SMU7_GfxCuPgScoreboard {
740	uint8_t Enabled;
741	uint8_t WaterfallUp;
742	uint8_t WaterfallDown;
743	uint8_t WaterfallLimit;
744	uint8_t CurrMaxCu;
745	uint8_t TargMaxCu;
746	uint8_t ClampMode;
747	uint8_t Active;
748	uint8_t MaxSupportedCu;
749	uint8_t MinSupportedCu;
750	uint8_t PendingGfxCuHostInterrupt;
751	uint8_t LastFilteredMaxCuInteger;
752	uint16_t FilteredMaxCu;
753	uint16_t FilteredMaxCuAlpha;
754	uint16_t FilterResetCount;
755	uint16_t FilterResetCountLimit;
756	uint8_t ForceCu;
757	uint8_t ForceCuCount;
758	uint8_t spare[2];
759};
760
761typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
762
763#define SMU7_SCLK_CAC 0x561
764#define SMU7_MCLK_CAC 0xF9
765#define SMU7_VCLK_CAC 0x2DE
766#define SMU7_DCLK_CAC 0x2DE
767#define SMU7_ECLK_CAC 0x25E
768#define SMU7_ACLK_CAC 0x25E
769#define SMU7_SAMCLK_CAC 0x25E
770#define SMU7_DISPCLK_CAC 0x100
771#define SMU7_CAC_CONSTANT 0x2EE3430
772#define SMU7_CAC_CONSTANT_SHIFT 18
773
774#define SMU7_VDDCI_MCLK_CONST        1765
775#define SMU7_VDDCI_MCLK_CONST_SHIFT  16
776#define SMU7_VDDCI_VDDCI_CONST       50958
777#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
778#define SMU7_VDDCI_CONST             11781
779#define SMU7_VDDCI_STROBE_PWR        1331
780
781#define SMU7_VDDR1_CONST            693
782#define SMU7_VDDR1_CAC_WEIGHT       20
783#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
784#define SMU7_VDDR1_STROBE_PWR       512
785
786#define SMU7_AREA_COEFF_UVD 0xA78
787#define SMU7_AREA_COEFF_VCE 0x190A
788#define SMU7_AREA_COEFF_ACP 0x22D1
789#define SMU7_AREA_COEFF_SAMU 0x534
790
791#define SMU7_THERM_OUT_MODE_DISABLE       0x0
792#define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
793#define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
794
795// DIDT Defines
796#define SQ_Enable_MASK 0x1
797#define SQ_IR_MASK 0x2
798#define SQ_PCC_MASK 0x4
799#define SQ_EDC_MASK 0x8
800
801#define TCP_Enable_MASK 0x100
802#define TCP_IR_MASK 0x200
803#define TCP_PCC_MASK 0x400
804#define TCP_EDC_MASK 0x800
805
806#define TD_Enable_MASK 0x10000
807#define TD_IR_MASK 0x20000
808#define TD_PCC_MASK 0x40000
809#define TD_EDC_MASK 0x80000
810
811#define DB_Enable_MASK 0x1000000
812#define DB_IR_MASK 0x2000000
813#define DB_PCC_MASK 0x4000000
814#define DB_EDC_MASK 0x8000000
815
816#define SQ_Enable_SHIFT 0
817#define SQ_IR_SHIFT 1
818#define SQ_PCC_SHIFT 2
819#define SQ_EDC_SHIFT 3
820
821#define TCP_Enable_SHIFT 8
822#define TCP_IR_SHIFT 9
823#define TCP_PCC_SHIFT 10
824#define TCP_EDC_SHIFT 11
825
826#define TD_Enable_SHIFT 16
827#define TD_IR_SHIFT 17
828#define TD_PCC_SHIFT 18
829#define TD_EDC_SHIFT 19
830
831#define DB_Enable_SHIFT 24
832#define DB_IR_SHIFT 25
833#define DB_PCC_SHIFT 26
834#define DB_EDC_SHIFT 27
835
836#define BTCGB0_Vdroop_Enable_MASK  0x1
837#define BTCGB1_Vdroop_Enable_MASK  0x2
838#define AVFSGB0_Vdroop_Enable_MASK 0x4
839#define AVFSGB1_Vdroop_Enable_MASK 0x8
840
841#define BTCGB0_Vdroop_Enable_SHIFT  0
842#define BTCGB1_Vdroop_Enable_SHIFT  1
843#define AVFSGB0_Vdroop_Enable_SHIFT 2
844#define AVFSGB1_Vdroop_Enable_SHIFT 3
845
846
847#pragma pack(pop)
848
849
850#endif
851
852