1/* $NetBSD: smu73.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3/* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25#ifndef _SMU73_H_ 26#define _SMU73_H_ 27 28#pragma pack(push, 1) 29enum SID_OPTION { 30 SID_OPTION_HI, 31 SID_OPTION_LO, 32 SID_OPTION_COUNT 33}; 34 35enum Poly3rdOrderCoeff { 36 LEAKAGE_TEMPERATURE_SCALAR, 37 LEAKAGE_VOLTAGE_SCALAR, 38 DYNAMIC_VOLTAGE_SCALAR, 39 POLY_3RD_ORDER_COUNT 40}; 41 42struct SMU7_Poly3rdOrder_Data 43{ 44 int32_t a; 45 int32_t b; 46 int32_t c; 47 int32_t d; 48 uint8_t a_shift; 49 uint8_t b_shift; 50 uint8_t c_shift; 51 uint8_t x_shift; 52}; 53 54typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; 55 56struct Power_Calculator_Data 57{ 58 uint16_t NoLoadVoltage; 59 uint16_t LoadVoltage; 60 uint16_t Resistance; 61 uint16_t Temperature; 62 uint16_t BaseLeakage; 63 uint16_t LkgTempScalar; 64 uint16_t LkgVoltScalar; 65 uint16_t LkgAreaScalar; 66 uint16_t LkgPower; 67 uint16_t DynVoltScalar; 68 uint32_t Cac; 69 uint32_t DynPower; 70 uint32_t TotalCurrent; 71 uint32_t TotalPower; 72}; 73 74typedef struct Power_Calculator_Data PowerCalculatorData_t; 75 76struct Gc_Cac_Weight_Data 77{ 78 uint8_t index; 79 uint32_t value; 80}; 81 82typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; 83 84 85typedef struct { 86 uint32_t high; 87 uint32_t low; 88} data_64_t; 89 90typedef struct { 91 data_64_t high; 92 data_64_t low; 93} data_128_t; 94 95#define SMU__NUM_SCLK_DPM_STATE 8 96#define SMU__NUM_MCLK_DPM_LEVELS 4 97#define SMU__NUM_LCLK_DPM_LEVELS 8 98#define SMU__NUM_PCIE_DPM_LEVELS 8 99 100#define SMU7_CONTEXT_ID_SMC 1 101#define SMU7_CONTEXT_ID_VBIOS 2 102 103#define SMU73_MAX_LEVELS_VDDC 16 104#define SMU73_MAX_LEVELS_VDDGFX 16 105#define SMU73_MAX_LEVELS_VDDCI 8 106#define SMU73_MAX_LEVELS_MVDD 4 107 108#define SMU_MAX_SMIO_LEVELS 4 109 110#define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 111#define SMU73_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 112#define SMU73_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 113#define SMU73_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 114#define SMU73_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 115#define SMU73_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 116#define SMU73_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 117#define SMU73_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 118#define SMU73_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 119 120#define DPM_NO_LIMIT 0 121#define DPM_NO_UP 1 122#define DPM_GO_DOWN 2 123#define DPM_GO_UP 3 124 125#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 126#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 127 128#define GPIO_CLAMP_MODE_VRHOT 1 129#define GPIO_CLAMP_MODE_THERM 2 130#define GPIO_CLAMP_MODE_DC 4 131 132#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 133#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 134#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 135#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 136#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 137#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 138#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 139#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 140#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 141#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 142#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 143#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 144#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 145#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 146#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 147#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 148#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 149#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 150#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 151#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 152 153// Virtualization Defines 154#define CG_XDMA_MASK 0x1 155#define CG_XDMA_SHIFT 0 156#define CG_UVD_MASK 0x2 157#define CG_UVD_SHIFT 1 158#define CG_VCE_MASK 0x4 159#define CG_VCE_SHIFT 2 160#define CG_SAMU_MASK 0x8 161#define CG_SAMU_SHIFT 3 162#define CG_GFX_MASK 0x10 163#define CG_GFX_SHIFT 4 164#define CG_SDMA_MASK 0x20 165#define CG_SDMA_SHIFT 5 166#define CG_HDP_MASK 0x40 167#define CG_HDP_SHIFT 6 168#define CG_MC_MASK 0x80 169#define CG_MC_SHIFT 7 170#define CG_DRM_MASK 0x100 171#define CG_DRM_SHIFT 8 172#define CG_ROM_MASK 0x200 173#define CG_ROM_SHIFT 9 174#define CG_BIF_MASK 0x400 175#define CG_BIF_SHIFT 10 176 177#define SMU73_DTE_ITERATIONS 5 178#define SMU73_DTE_SOURCES 3 179#define SMU73_DTE_SINKS 1 180#define SMU73_NUM_CPU_TES 0 181#define SMU73_NUM_GPU_TES 1 182#define SMU73_NUM_NON_TES 2 183#define SMU73_DTE_FAN_SCALAR_MIN 0x100 184#define SMU73_DTE_FAN_SCALAR_MAX 0x166 185#define SMU73_DTE_FAN_TEMP_MAX 93 186#define SMU73_DTE_FAN_TEMP_MIN 83 187 188#define SMU73_THERMAL_INPUT_LOOP_COUNT 6 189#define SMU73_THERMAL_CLAMP_MODE_COUNT 8 190 191 192struct SMU7_HystController_Data 193{ 194 uint16_t waterfall_up; 195 uint16_t waterfall_down; 196 uint16_t waterfall_limit; 197 uint16_t release_cnt; 198 uint16_t release_limit; 199 uint16_t spare; 200}; 201 202typedef struct SMU7_HystController_Data SMU7_HystController_Data; 203 204struct SMU73_PIDController 205{ 206 uint32_t Ki; 207 int32_t LFWindupUpperLim; 208 int32_t LFWindupLowerLim; 209 uint32_t StatePrecision; 210 211 uint32_t LfPrecision; 212 uint32_t LfOffset; 213 uint32_t MaxState; 214 uint32_t MaxLfFraction; 215 uint32_t StateShift; 216}; 217 218typedef struct SMU73_PIDController SMU73_PIDController; 219 220struct SMU7_LocalDpmScoreboard 221{ 222 uint32_t PercentageBusy; 223 224 int32_t PIDError; 225 int32_t PIDIntegral; 226 int32_t PIDOutput; 227 228 uint32_t SigmaDeltaAccum; 229 uint32_t SigmaDeltaOutput; 230 uint32_t SigmaDeltaLevel; 231 232 uint32_t UtilizationSetpoint; 233 234 uint8_t TdpClampMode; 235 uint8_t TdcClampMode; 236 uint8_t ThermClampMode; 237 uint8_t VoltageBusy; 238 239 int8_t CurrLevel; 240 int8_t TargLevel; 241 uint8_t LevelChangeInProgress; 242 uint8_t UpHyst; 243 244 uint8_t DownHyst; 245 uint8_t VoltageDownHyst; 246 uint8_t DpmEnable; 247 uint8_t DpmRunning; 248 249 uint8_t DpmForce; 250 uint8_t DpmForceLevel; 251 uint8_t DisplayWatermark; 252 uint8_t McArbIndex; 253 254 uint32_t MinimumPerfSclk; 255 256 uint8_t AcpiReq; 257 uint8_t AcpiAck; 258 uint8_t GfxClkSlow; 259 uint8_t GpioClampMode; 260 261 uint8_t spare2; 262 uint8_t EnabledLevelsChange; 263 uint8_t DteClampMode; 264 uint8_t FpsClampMode; 265 266 uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_GRAPHICS]; 267 uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_GRAPHICS]; 268 269 void (*TargetStateCalculator)(uint8_t); 270 void (*SavedTargetStateCalculator)(uint8_t); 271 272 uint16_t AutoDpmInterval; 273 uint16_t AutoDpmRange; 274 275 uint8_t FpsEnabled; 276 uint8_t MaxPerfLevel; 277 uint8_t AllowLowClkInterruptToHost; 278 uint8_t FpsRunning; 279 280 uint32_t MaxAllowedFrequency; 281 282 uint32_t FilteredSclkFrequency; 283 uint32_t LastSclkFrequency; 284 uint32_t FilteredSclkFrequencyCnt; 285 286 uint8_t LedEnable; 287 uint8_t LedPin0; 288 uint8_t LedPin1; 289 uint8_t LedPin2; 290 uint32_t LedAndMask; 291 292 uint16_t FpsAlpha; 293 uint16_t DeltaTime; 294 uint32_t CurrentFps; 295 uint32_t FilteredFps; 296 uint32_t FrameCount; 297 uint32_t FrameCountLast; 298 uint16_t FpsTargetScalar; 299 uint16_t FpsWaterfallLimitScalar; 300 uint16_t FpsAlphaScalar; 301 uint16_t spare8; 302 SMU7_HystController_Data HystControllerData; 303}; 304 305typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 306 307#define SMU7_MAX_VOLTAGE_CLIENTS 12 308 309typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); 310 311#define VDDC_MASK 0x00007FFF 312#define VDDC_SHIFT 0 313#define VDDCI_MASK 0x3FFF8000 314#define VDDCI_SHIFT 15 315#define PHASES_MASK 0xC0000000 316#define PHASES_SHIFT 30 317 318typedef uint32_t SMU_VoltageLevel; 319 320struct SMU7_VoltageScoreboard 321{ 322 SMU_VoltageLevel TargetVoltage; 323 uint16_t MaxVid; 324 uint8_t HighestVidOffset; 325 uint8_t CurrentVidOffset; 326 327 uint16_t CurrentVddc; 328 uint16_t CurrentVddci; 329 330 331 uint8_t ControllerBusy; 332 uint8_t CurrentVid; 333 uint8_t CurrentVddciVid; 334 uint8_t padding; 335 336 SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 337 SMU_VoltageLevel TargetVoltageState; 338 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 339 340 uint8_t padding2; 341 uint8_t padding3; 342 uint8_t ControllerEnable; 343 uint8_t ControllerRunning; 344 uint16_t CurrentStdVoltageHiSidd; 345 uint16_t CurrentStdVoltageLoSidd; 346 uint8_t OverrideVoltage; 347 uint8_t padding4; 348 uint8_t padding5; 349 uint8_t CurrentPhases; 350 351 VoltageChangeHandler_t ChangeVddc; 352 353 VoltageChangeHandler_t ChangeVddci; 354 VoltageChangeHandler_t ChangePhase; 355 VoltageChangeHandler_t ChangeMvdd; 356 357 VoltageChangeHandler_t functionLinks[6]; 358 359 uint16_t * VddcFollower1; 360 361 int16_t Driver_OD_RequestedVidOffset1; 362 int16_t Driver_OD_RequestedVidOffset2; 363 364}; 365 366typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 367 368// ------------------------------------------------------------------------------------------------------------------------- 369#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 370 371struct SMU7_PCIeLinkSpeedScoreboard 372{ 373 uint8_t DpmEnable; 374 uint8_t DpmRunning; 375 uint8_t DpmForce; 376 uint8_t DpmForceLevel; 377 378 uint8_t CurrentLinkSpeed; 379 uint8_t EnabledLevelsChange; 380 uint16_t AutoDpmInterval; 381 382 uint16_t AutoDpmRange; 383 uint16_t AutoDpmCount; 384 385 uint8_t DpmMode; 386 uint8_t AcpiReq; 387 uint8_t AcpiAck; 388 uint8_t CurrentLinkLevel; 389 390}; 391 392typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 393 394// -------------------------------------------------------- CAC table ------------------------------------------------------ 395#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 396#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 397 398#define SMU7_SCALE_I 7 399#define SMU7_SCALE_R 12 400 401struct SMU7_PowerScoreboard 402{ 403 uint32_t GpuPower; 404 405 uint32_t VddcPower; 406 uint32_t VddcVoltage; 407 uint32_t VddcCurrent; 408 409 uint32_t MvddPower; 410 uint32_t MvddVoltage; 411 uint32_t MvddCurrent; 412 413 uint32_t RocPower; 414 415 uint16_t Telemetry_1_slope; 416 uint16_t Telemetry_2_slope; 417 int32_t Telemetry_1_offset; 418 int32_t Telemetry_2_offset; 419}; 420typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 421 422// For FeatureEnables: 423#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 424#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 425#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 426#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 427#define SMU7_UVD_DPM_CONFIG_MASK 0x10 428#define SMU7_VCE_DPM_CONFIG_MASK 0x20 429#define SMU7_ACP_DPM_CONFIG_MASK 0x40 430#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 431#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 432 433#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 434#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 435#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 436#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 437#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 438#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 439 440// All 'soft registers' should be uint32_t. 441struct SMU73_SoftRegisters 442{ 443 uint32_t RefClockFrequency; 444 uint32_t PmTimerPeriod; 445 uint32_t FeatureEnables; 446 447 uint32_t PreVBlankGap; 448 uint32_t VBlankTimeout; 449 uint32_t TrainTimeGap; 450 451 uint32_t MvddSwitchTime; 452 uint32_t LongestAcpiTrainTime; 453 uint32_t AcpiDelay; 454 uint32_t G5TrainTime; 455 uint32_t DelayMpllPwron; 456 uint32_t VoltageChangeTimeout; 457 458 uint32_t HandshakeDisables; 459 460 uint8_t DisplayPhy1Config; 461 uint8_t DisplayPhy2Config; 462 uint8_t DisplayPhy3Config; 463 uint8_t DisplayPhy4Config; 464 465 uint8_t DisplayPhy5Config; 466 uint8_t DisplayPhy6Config; 467 uint8_t DisplayPhy7Config; 468 uint8_t DisplayPhy8Config; 469 470 uint32_t AverageGraphicsActivity; 471 uint32_t AverageMemoryActivity; 472 uint32_t AverageGioActivity; 473 474 uint8_t SClkDpmEnabledLevels; 475 uint8_t MClkDpmEnabledLevels; 476 uint8_t LClkDpmEnabledLevels; 477 uint8_t PCIeDpmEnabledLevels; 478 479 uint8_t UVDDpmEnabledLevels; 480 uint8_t SAMUDpmEnabledLevels; 481 uint8_t ACPDpmEnabledLevels; 482 uint8_t VCEDpmEnabledLevels; 483 484 uint32_t DRAM_LOG_ADDR_H; 485 uint32_t DRAM_LOG_ADDR_L; 486 uint32_t DRAM_LOG_PHY_ADDR_H; 487 uint32_t DRAM_LOG_PHY_ADDR_L; 488 uint32_t DRAM_LOG_BUFF_SIZE; 489 uint32_t UlvEnterCount; 490 uint32_t UlvTime; 491 uint32_t UcodeLoadStatus; 492 uint32_t Reserved[2]; 493 494}; 495 496typedef struct SMU73_SoftRegisters SMU73_SoftRegisters; 497 498struct SMU73_Firmware_Header 499{ 500 uint32_t Digest[5]; 501 uint32_t Version; 502 uint32_t HeaderSize; 503 uint32_t Flags; 504 uint32_t EntryPoint; 505 uint32_t CodeSize; 506 uint32_t ImageSize; 507 508 uint32_t Rtos; 509 uint32_t SoftRegisters; 510 uint32_t DpmTable; 511 uint32_t FanTable; 512 uint32_t CacConfigTable; 513 uint32_t CacStatusTable; 514 515 516 uint32_t mcRegisterTable; 517 518 519 uint32_t mcArbDramTimingTable; 520 521 522 523 524 uint32_t PmFuseTable; 525 uint32_t Globals; 526 uint32_t ClockStretcherTable; 527 uint32_t Reserved[41]; 528 uint32_t Signature; 529}; 530 531typedef struct SMU73_Firmware_Header SMU73_Firmware_Header; 532 533#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 534 535enum DisplayConfig { 536 PowerDown = 1, 537 DP54x4, 538 DP54x2, 539 DP54x1, 540 DP27x4, 541 DP27x2, 542 DP27x1, 543 HDMI297, 544 HDMI162, 545 LVDS, 546 DP324x4, 547 DP324x2, 548 DP324x1 549}; 550 551 552#define MC_BLOCK_COUNT 1 553#define CPL_BLOCK_COUNT 5 554#define SE_BLOCK_COUNT 15 555#define GC_BLOCK_COUNT 24 556 557struct SMU7_Local_Cac { 558 uint8_t BlockId; 559 uint8_t SignalId; 560 uint8_t Threshold; 561 uint8_t Padding; 562}; 563 564typedef struct SMU7_Local_Cac SMU7_Local_Cac; 565 566struct SMU7_Local_Cac_Table { 567 568 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 569 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 570 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; 571 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; 572}; 573 574typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 575 576#if !defined(SMC_MICROCODE) 577#pragma pack(pop) 578#endif 579 580// Description of Clock Gating bitmask for Tonga: 581// System Clock Gating 582#define CG_SYS_BITMASK_FIRST_BIT 0 // First bit of Sys CG bitmask 583#define CG_SYS_BITMASK_LAST_BIT 9 // Last bit of Sys CG bitmask 584#define CG_SYS_BIF_MGLS_SHIFT 0 585#define CG_SYS_ROM_SHIFT 1 586#define CG_SYS_MC_MGCG_SHIFT 2 587#define CG_SYS_MC_MGLS_SHIFT 3 588#define CG_SYS_SDMA_MGCG_SHIFT 4 589#define CG_SYS_SDMA_MGLS_SHIFT 5 590#define CG_SYS_DRM_MGCG_SHIFT 6 591#define CG_SYS_HDP_MGCG_SHIFT 7 592#define CG_SYS_HDP_MGLS_SHIFT 8 593#define CG_SYS_DRM_MGLS_SHIFT 9 594 595#define CG_SYS_BIF_MGLS_MASK 0x1 596#define CG_SYS_ROM_MASK 0x2 597#define CG_SYS_MC_MGCG_MASK 0x4 598#define CG_SYS_MC_MGLS_MASK 0x8 599#define CG_SYS_SDMA_MGCG_MASK 0x10 600#define CG_SYS_SDMA_MGLS_MASK 0x20 601#define CG_SYS_DRM_MGCG_MASK 0x40 602#define CG_SYS_HDP_MGCG_MASK 0x80 603#define CG_SYS_HDP_MGLS_MASK 0x100 604#define CG_SYS_DRM_MGLS_MASK 0x200 605 606// Graphics Clock Gating 607#define CG_GFX_BITMASK_FIRST_BIT 16 // First bit of Gfx CG bitmask 608#define CG_GFX_BITMASK_LAST_BIT 20 // Last bit of Gfx CG bitmask 609#define CG_GFX_CGCG_SHIFT 16 610#define CG_GFX_CGLS_SHIFT 17 611#define CG_CPF_MGCG_SHIFT 18 612#define CG_RLC_MGCG_SHIFT 19 613#define CG_GFX_OTHERS_MGCG_SHIFT 20 614 615#define CG_GFX_CGCG_MASK 0x00010000 616#define CG_GFX_CGLS_MASK 0x00020000 617#define CG_CPF_MGCG_MASK 0x00040000 618#define CG_RLC_MGCG_MASK 0x00080000 619#define CG_GFX_OTHERS_MGCG_MASK 0x00100000 620 621 622 623// Voltage Regulator Configuration 624// VR Config info is contained in dpmTable.VRConfig 625 626#define VRCONF_VDDC_MASK 0x000000FF 627#define VRCONF_VDDC_SHIFT 0 628#define VRCONF_VDDGFX_MASK 0x0000FF00 629#define VRCONF_VDDGFX_SHIFT 8 630#define VRCONF_VDDCI_MASK 0x00FF0000 631#define VRCONF_VDDCI_SHIFT 16 632#define VRCONF_MVDD_MASK 0xFF000000 633#define VRCONF_MVDD_SHIFT 24 634 635#define VR_MERGED_WITH_VDDC 0 636#define VR_SVI2_PLANE_1 1 637#define VR_SVI2_PLANE_2 2 638#define VR_SMIO_PATTERN_1 3 639#define VR_SMIO_PATTERN_2 4 640#define VR_STATIC_VOLTAGE 5 641 642// Clock Stretcher Configuration 643 644#define CLOCK_STRETCHER_MAX_ENTRIES 0x4 645#define CKS_LOOKUPTable_MAX_ENTRIES 0x4 646 647// The 'settings' field is subdivided in the following way: 648#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 649#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 650#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E 651#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 652#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 653#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 654 655struct SMU_ClockStretcherDataTableEntry { 656 uint8_t minVID; 657 uint8_t maxVID; 658 659 660 uint16_t setting; 661}; 662typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 663 664struct SMU_ClockStretcherDataTable { 665 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; 666}; 667typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; 668 669struct SMU_CKS_LOOKUPTableEntry { 670 uint16_t minFreq; 671 uint16_t maxFreq; 672 673 uint8_t setting; 674 uint8_t padding[3]; 675}; 676typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; 677 678struct SMU_CKS_LOOKUPTable { 679 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; 680}; 681typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; 682 683struct AgmAvfsData_t { 684 uint16_t avgPsmCount[28]; 685 uint16_t minPsmCount[28]; 686}; 687typedef struct AgmAvfsData_t AgmAvfsData_t; 688 689// AVFS DEFINES 690 691enum VFT_COLUMNS { 692 SCLK0, 693 SCLK1, 694 SCLK2, 695 SCLK3, 696 SCLK4, 697 SCLK5, 698 SCLK6, 699 SCLK7, 700 701 NUM_VFT_COLUMNS 702}; 703 704#define TEMP_RANGE_MAXSTEPS 12 705struct VFT_CELL_t { 706 uint16_t Voltage; 707}; 708 709typedef struct VFT_CELL_t VFT_CELL_t; 710 711struct VFT_TABLE_t { 712 VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; 713 uint16_t AvfsGbv [NUM_VFT_COLUMNS]; 714 uint16_t BtcGbv [NUM_VFT_COLUMNS]; 715 uint16_t Temperature [TEMP_RANGE_MAXSTEPS]; 716 717 uint8_t NumTemperatureSteps; 718 uint8_t padding[3]; 719}; 720typedef struct VFT_TABLE_t VFT_TABLE_t; 721 722#endif 723